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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_hs / 49f6da224c966cf03efa6b52c24559d20b3c27ce^! / .
commit49f6da224c966cf03efa6b52c24559d20b3c27ce[log] [tgz]
authorHunter Lusk <hlusk@okita.ecen.okstate.edu>Thu Sep 03 10:01:51 2020 -0500
committerHunter Lusk <hlusk@okita.ecen.okstate.edu>Thu Sep 03 10:01:51 2020 -0500
tree32dd66780dd26076be82d3872bfd6ffcf01f1bf0
parentd56fe264e9c769c681977be6b94f0f5ef74153bd [diff]
Updates to spice, PEX and PXI files as well as the addition of lvs reports

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.lvs.report b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.lvs.report
new file mode 100644
index 0000000..2ca66c5
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2111o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2111o_1.sp ('sky130_fd_sc_hs__a2111o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice ('sky130_fd_sc_hs__a2111o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:47:47 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2111o_1     sky130_fd_sc_hs__a2111o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2111o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2111o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 D1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pex.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pex.spice
index 9fe1d3b..eed4475 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_1.pex.spice
-* Created: Thu Aug 27 20:22:29 2020
+* Created: Tue Sep  1 19:47:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pxi.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pxi.spice
index 78120a6..d9ab86b 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_1.pxi.spice
-* Created: Thu Aug 27 20:22:29 2020
+* Created: Tue Sep  1 19:47:49 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2111O_1%A1 N_A1_c_74_n N_A1_c_75_n N_A1_c_81_n
 + N_A1_M1010_g N_A1_M1001_g A1 A1 N_A1_c_77_n N_A1_c_78_n N_A1_c_79_n

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice
index 1514d4c..b5b22b5 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_1.spice
-* Created: Thu Aug 27 20:22:29 2020
+* Created: Tue Sep  1 19:47:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.lvs.report b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.lvs.report
new file mode 100644
index 0000000..9295280
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2111o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2111o_2.sp ('sky130_fd_sc_hs__a2111o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice ('sky130_fd_sc_hs__a2111o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:47:52 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2111o_2     sky130_fd_sc_hs__a2111o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2111o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2111o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pex.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pex.spice
index 9629a72..a986651 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_2.pex.spice
-* Created: Thu Aug 27 20:22:37 2020
+* Created: Tue Sep  1 19:47:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pxi.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pxi.spice
index bdfc9e5..f5ad537 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_2.pxi.spice
-* Created: Thu Aug 27 20:22:37 2020
+* Created: Tue Sep  1 19:47:55 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2111O_2%A_91_244# N_A_91_244#_M1010_s N_A_91_244#_M1004_d
 + N_A_91_244#_M1008_d N_A_91_244#_M1001_s N_A_91_244#_c_94_n N_A_91_244#_M1011_g

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice
index 42f49fb..b2578d3 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_2.spice
-* Created: Thu Aug 27 20:22:37 2020
+* Created: Tue Sep  1 19:47:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.lvs.report b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.lvs.report
new file mode 100644
index 0000000..7b40cd6
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2111o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2111o_4.sp ('sky130_fd_sc_hs__a2111o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice ('sky130_fd_sc_hs__a2111o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:47:58 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2111o_4     sky130_fd_sc_hs__a2111o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2111o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2111o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pex.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pex.spice
index cf415c2..765cc15 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_4.pex.spice
-* Created: Thu Aug 27 20:22:44 2020
+* Created: Tue Sep  1 19:48:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pxi.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pxi.spice
index f5c90c5..02bc85f 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_4.pxi.spice
-* Created: Thu Aug 27 20:22:44 2020
+* Created: Tue Sep  1 19:48:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2111O_4%A_137_260# N_A_137_260#_M1017_d
 + N_A_137_260#_M1006_s N_A_137_260#_M1012_s N_A_137_260#_M1001_d

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice
index bb5e367..91a0c6b 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111o_4.spice
-* Created: Thu Aug 27 20:22:44 2020
+* Created: Tue Sep  1 19:48:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.lvs.report b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.lvs.report
new file mode 100644
index 0000000..7990bfe
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2111oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2111oi_1.sp ('sky130_fd_sc_hs__a2111oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice ('sky130_fd_sc_hs__a2111oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:04 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2111oi_1    sky130_fd_sc_hs__a2111oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2111oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2111oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pex.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pex.spice
index 36f2f40..ee4a00f 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_1.pex.spice
-* Created: Thu Aug 27 20:22:52 2020
+* Created: Tue Sep  1 19:48:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pxi.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pxi.spice
index fee591e..4e1c0cc 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_1.pxi.spice
-* Created: Thu Aug 27 20:22:52 2020
+* Created: Tue Sep  1 19:48:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2111OI_1%D1 N_D1_c_54_n N_D1_M1000_g N_D1_M1004_g D1
 + N_D1_c_56_n PM_SKY130_FD_SC_HS__A2111OI_1%D1

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice
index 45f44ca..95a8eae 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_1.spice
-* Created: Thu Aug 27 20:22:52 2020
+* Created: Tue Sep  1 19:48:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.lvs.report b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.lvs.report
new file mode 100644
index 0000000..c94159f
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.lvs.report

@@ -0,0 +1,493 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2111oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2111oi_2.sp ('sky130_fd_sc_hs__a2111oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice ('sky130_fd_sc_hs__a2111oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2111oi_2    sky130_fd_sc_hs__a2111oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2111oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2111oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        18        17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 7.
+     7 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 7.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pex.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pex.spice
index 7ad9a51..14f70de 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_2.pex.spice
-* Created: Thu Aug 27 20:23:00 2020
+* Created: Tue Sep  1 19:48:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pxi.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pxi.spice
index de2cb7a..6a2eabf 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_2.pxi.spice
-* Created: Thu Aug 27 20:23:00 2020
+* Created: Tue Sep  1 19:48:12 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2111OI_2%D1 N_D1_c_92_n N_D1_M1008_g N_D1_M1007_g
 + N_D1_c_93_n N_D1_M1009_g D1 D1 N_D1_c_91_n PM_SKY130_FD_SC_HS__A2111OI_2%D1

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice
index 40ff7be..f8cde81 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_2.spice
-* Created: Thu Aug 27 20:23:00 2020
+* Created: Tue Sep  1 19:48:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.lvs.report b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.lvs.report
new file mode 100644
index 0000000..0135635
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.lvs.report

@@ -0,0 +1,510 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2111oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2111oi_4.sp ('sky130_fd_sc_hs__a2111oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice ('sky130_fd_sc_hs__a2111oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2111oi_4    sky130_fd_sc_hs__a2111oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2111oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2111oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         14        14         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   34 layout mos transistors were reduced to 10.
+     24 mos transistors were deleted by parallel reduction.
+   34 source mos transistors were reduced to 10.
+     24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pex.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pex.spice
index 066cf09..c3faca9 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_4.pex.spice
-* Created: Thu Aug 27 20:23:07 2020
+* Created: Tue Sep  1 19:48:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pxi.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pxi.spice
index 1efc1e1..9c4fd61 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_4.pxi.spice
-* Created: Thu Aug 27 20:23:07 2020
+* Created: Tue Sep  1 19:48:18 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2111OI_4%D1 N_D1_c_140_n N_D1_M1000_g N_D1_c_141_n
 + N_D1_M1001_g N_D1_c_142_n N_D1_M1002_g N_D1_c_136_n N_D1_M1017_g N_D1_c_137_n

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice
index 96b6897..9f1c654 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2111oi_4.spice
-* Created: Thu Aug 27 20:23:07 2020
+* Created: Tue Sep  1 19:48:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_1.lvs.report b/cells/a211o/sky130_fd_sc_hs__a211o_1.lvs.report
new file mode 100644
index 0000000..1655df6
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a211o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a211o_1.sp ('sky130_fd_sc_hs__a211o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_1.spice ('sky130_fd_sc_hs__a211o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a211o_1      sky130_fd_sc_hs__a211o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a211o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a211o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_1.pex.spice b/cells/a211o/sky130_fd_sc_hs__a211o_1.pex.spice
index aa9f7d1..392ff76 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_1.pex.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_1.pex.spice
-* Created: Thu Aug 27 20:23:14 2020
+* Created: Tue Sep  1 19:48:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_1.pxi.spice b/cells/a211o/sky130_fd_sc_hs__a211o_1.pxi.spice
index 86e9203..207202d 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_1.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_1.pxi.spice
-* Created: Thu Aug 27 20:23:14 2020
+* Created: Tue Sep  1 19:48:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__A211O_1%A_81_264# N_A_81_264#_M1009_d N_A_81_264#_M1006_d
 + N_A_81_264#_M1007_d N_A_81_264#_c_71_n N_A_81_264#_M1000_g N_A_81_264#_M1004_g

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_1.spice b/cells/a211o/sky130_fd_sc_hs__a211o_1.spice
index 695bda8..f15c9bc 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_1.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_1.spice
-* Created: Thu Aug 27 20:23:14 2020
+* Created: Tue Sep  1 19:48:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_2.lvs.report b/cells/a211o/sky130_fd_sc_hs__a211o_2.lvs.report
new file mode 100644
index 0000000..009556b
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a211o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a211o_2.sp ('sky130_fd_sc_hs__a211o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_2.spice ('sky130_fd_sc_hs__a211o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:27 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a211o_2      sky130_fd_sc_hs__a211o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a211o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a211o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_2.pex.spice b/cells/a211o/sky130_fd_sc_hs__a211o_2.pex.spice
index 7ea1be2..72d9488 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_2.pex.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_2.pex.spice
-* Created: Thu Aug 27 20:23:22 2020
+* Created: Tue Sep  1 19:48:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_2.pxi.spice b/cells/a211o/sky130_fd_sc_hs__a211o_2.pxi.spice
index 79db408..062d794 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_2.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_2.pxi.spice
-* Created: Thu Aug 27 20:23:22 2020
+* Created: Tue Sep  1 19:48:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__A211O_2%A_85_270# N_A_85_270#_M1000_d N_A_85_270#_M1010_d
 + N_A_85_270#_M1011_d N_A_85_270#_c_75_n N_A_85_270#_c_84_n N_A_85_270#_M1001_g

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_2.spice b/cells/a211o/sky130_fd_sc_hs__a211o_2.spice
index 8ecdb61..7f0e6b1 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_2.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_2.spice
-* Created: Thu Aug 27 20:23:22 2020
+* Created: Tue Sep  1 19:48:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_4.lvs.report b/cells/a211o/sky130_fd_sc_hs__a211o_4.lvs.report
new file mode 100644
index 0000000..2bc3918
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_4.lvs.report

@@ -0,0 +1,502 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a211o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a211o_4.sp ('sky130_fd_sc_hs__a211o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211o/sky130_fd_sc_hs__a211o_4.spice ('sky130_fd_sc_hs__a211o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:33 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a211o_4      sky130_fd_sc_hs__a211o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a211o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a211o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 C1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_4.pex.spice b/cells/a211o/sky130_fd_sc_hs__a211o_4.pex.spice
index 35215f4..afdfea0 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_4.pex.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_4.pex.spice
-* Created: Thu Aug 27 20:23:33 2020
+* Created: Tue Sep  1 19:48:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_4.pxi.spice b/cells/a211o/sky130_fd_sc_hs__a211o_4.pxi.spice
index a5245c1..0b282f6 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_4.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_4.pxi.spice
-* Created: Thu Aug 27 20:23:33 2020
+* Created: Tue Sep  1 19:48:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__A211O_4%A_105_280# N_A_105_280#_M1009_d
 + N_A_105_280#_M1020_d N_A_105_280#_M1004_d N_A_105_280#_M1006_d

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_4.spice b/cells/a211o/sky130_fd_sc_hs__a211o_4.spice
index 847f63c..3aa389b 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_4.spice
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211o_4.spice
-* Created: Thu Aug 27 20:23:33 2020
+* Created: Tue Sep  1 19:48:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.lvs.report b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.lvs.report
new file mode 100644
index 0000000..5e3bfe2
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a211oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a211oi_1.sp ('sky130_fd_sc_hs__a211oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice ('sky130_fd_sc_hs__a211oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:39 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a211oi_1     sky130_fd_sc_hs__a211oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a211oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a211oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pex.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pex.spice
index 909f061..87e2f70 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_1.pex.spice
-* Created: Thu Aug 27 20:23:40 2020
+* Created: Tue Sep  1 19:48:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pxi.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pxi.spice
index 4813857..37e5cdf 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_1.pxi.spice
-* Created: Thu Aug 27 20:23:40 2020
+* Created: Tue Sep  1 19:48:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__A211OI_1%A2 N_A2_c_48_n N_A2_M1000_g N_A2_M1002_g A2
 + N_A2_c_50_n PM_SKY130_FD_SC_HS__A211OI_1%A2

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice
index e23435c..3d2f996 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_1.spice
-* Created: Thu Aug 27 20:23:40 2020
+* Created: Tue Sep  1 19:48:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.lvs.report b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.lvs.report
new file mode 100644
index 0000000..40cdce8
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a211oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a211oi_2.sp ('sky130_fd_sc_hs__a211oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice ('sky130_fd_sc_hs__a211oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a211oi_2     sky130_fd_sc_hs__a211oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a211oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a211oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pex.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pex.spice
index 6649396..313c7ab 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_2.pex.spice
-* Created: Thu Aug 27 20:23:47 2020
+* Created: Tue Sep  1 19:48:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pxi.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pxi.spice
index 909e562..ae66c3d 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_2.pxi.spice
-* Created: Thu Aug 27 20:23:47 2020
+* Created: Tue Sep  1 19:48:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__A211OI_2%A1 N_A1_c_79_n N_A1_M1000_g N_A1_c_75_n
 + N_A1_M1008_g N_A1_c_80_n N_A1_M1001_g N_A1_c_76_n N_A1_M1011_g A1 N_A1_c_78_n

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice
index b483a9b..efefe5f 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_2.spice
-* Created: Thu Aug 27 20:23:47 2020
+* Created: Tue Sep  1 19:48:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.lvs.report b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.lvs.report
new file mode 100644
index 0000000..31323f0
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a211oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a211oi_4.sp ('sky130_fd_sc_hs__a211oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice ('sky130_fd_sc_hs__a211oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a211oi_4     sky130_fd_sc_hs__a211oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a211oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a211oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         12        12         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pex.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pex.spice
index b6835e8..9664813 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_4.pex.spice
-* Created: Thu Aug 27 20:23:54 2020
+* Created: Tue Sep  1 19:48:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pxi.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pxi.spice
index 6f35ea9..314db9d 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_4.pxi.spice
-* Created: Thu Aug 27 20:23:54 2020
+* Created: Tue Sep  1 19:48:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__A211OI_4%A2 N_A2_c_116_n N_A2_M1002_g N_A2_M1004_g
 + N_A2_c_117_n N_A2_M1006_g N_A2_M1005_g N_A2_c_118_n N_A2_M1023_g N_A2_M1013_g

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice
index 879f46b..575eae5 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a211oi_4.spice
-* Created: Thu Aug 27 20:23:54 2020
+* Created: Tue Sep  1 19:48:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.lvs.report b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.lvs.report
new file mode 100644
index 0000000..747119b
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21bo_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21bo_1.sp ('sky130_fd_sc_hs__a21bo_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice ('sky130_fd_sc_hs__a21bo_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:48:56 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21bo_1      sky130_fd_sc_hs__a21bo_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21bo_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21bo_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pex.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pex.spice
index 423d911..96587a8 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_1.pex.spice
-* Created: Thu Aug 27 20:24:01 2020
+* Created: Tue Sep  1 19:48:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pxi.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pxi.spice
index 46cb581..4d7f2f8 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_1.pxi.spice
-* Created: Thu Aug 27 20:24:01 2020
+* Created: Tue Sep  1 19:48:59 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21BO_1%A2 N_A2_c_74_n N_A2_c_75_n N_A2_c_80_n
 + N_A2_M1006_g N_A2_M1000_g N_A2_c_77_n A2 N_A2_c_78_n

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice
index ca18b27..2dd2eb2 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_1.spice
-* Created: Thu Aug 27 20:24:01 2020
+* Created: Tue Sep  1 19:48:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.lvs.report b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.lvs.report
new file mode 100644
index 0000000..10b13f2
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21bo_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21bo_2.sp ('sky130_fd_sc_hs__a21bo_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice ('sky130_fd_sc_hs__a21bo_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:02 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21bo_2      sky130_fd_sc_hs__a21bo_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21bo_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21bo_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pex.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pex.spice
index c35e19e..e15b1c6 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_2.pex.spice
-* Created: Thu Aug 27 20:24:08 2020
+* Created: Tue Sep  1 19:49:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pxi.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pxi.spice
index b5425bd..be12894 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_2.pxi.spice
-* Created: Thu Aug 27 20:24:08 2020
+* Created: Tue Sep  1 19:49:05 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21BO_2%B1_N N_B1_N_c_72_n N_B1_N_M1002_g N_B1_N_c_73_n
 + N_B1_N_M1009_g B1_N N_B1_N_c_74_n PM_SKY130_FD_SC_HS__A21BO_2%B1_N

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice
index 308a749..62a4c9d 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_2.spice
-* Created: Thu Aug 27 20:24:08 2020
+* Created: Tue Sep  1 19:49:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.lvs.report b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.lvs.report
new file mode 100644
index 0000000..593a380
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.lvs.report

@@ -0,0 +1,500 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21bo_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21bo_4.sp ('sky130_fd_sc_hs__a21bo_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice ('sky130_fd_sc_hs__a21bo_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:08 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21bo_4      sky130_fd_sc_hs__a21bo_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21bo_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21bo_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pex.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pex.spice
index c16ad5c..0ebb9a5 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_4.pex.spice
-* Created: Thu Aug 27 20:24:16 2020
+* Created: Tue Sep  1 19:49:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pxi.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pxi.spice
index dd3312d..fcbbb3e 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_4.pxi.spice
-* Created: Thu Aug 27 20:24:16 2020
+* Created: Tue Sep  1 19:49:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21BO_4%B1_N N_B1_N_c_117_n N_B1_N_c_123_n N_B1_N_M1018_g
 + N_B1_N_M1005_g N_B1_N_c_119_n B1_N N_B1_N_c_121_n

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice
index 359671e..ca2b5f9 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21bo_4.spice
-* Created: Thu Aug 27 20:24:16 2020
+* Created: Tue Sep  1 19:49:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.lvs.report b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.lvs.report
new file mode 100644
index 0000000..5567002
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21boi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21boi_1.sp ('sky130_fd_sc_hs__a21boi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice ('sky130_fd_sc_hs__a21boi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:14 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21boi_1     sky130_fd_sc_hs__a21boi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21boi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21boi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pex.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pex.spice
index f70d3db..d04dc24 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_1.pex.spice
-* Created: Thu Aug 27 20:24:23 2020
+* Created: Tue Sep  1 19:49:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pxi.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pxi.spice
index 0200386..3ecd487 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_1.pxi.spice
-* Created: Thu Aug 27 20:24:23 2020
+* Created: Tue Sep  1 19:49:16 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21BOI_1%B1_N N_B1_N_c_58_n N_B1_N_c_64_n N_B1_N_c_65_n
 + N_B1_N_M1002_g N_B1_N_c_59_n N_B1_N_c_60_n N_B1_N_M1001_g B1_N B1_N B1_N

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice
index d604b2d..69a0f21 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_1.spice
-* Created: Thu Aug 27 20:24:23 2020
+* Created: Tue Sep  1 19:49:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.lvs.report b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.lvs.report
new file mode 100644
index 0000000..63070ff
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21boi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21boi_2.sp ('sky130_fd_sc_hs__a21boi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice ('sky130_fd_sc_hs__a21boi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:19 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21boi_2     sky130_fd_sc_hs__a21boi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21boi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21boi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pex.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pex.spice
index ba5b29d..1f4f56c 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_2.pex.spice
-* Created: Thu Aug 27 20:24:33 2020
+* Created: Tue Sep  1 19:49:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pxi.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pxi.spice
index 4011115..244d2e2 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_2.pxi.spice
-* Created: Thu Aug 27 20:24:33 2020
+* Created: Tue Sep  1 19:49:22 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21BOI_2%B1_N N_B1_N_c_80_n N_B1_N_M1012_g N_B1_N_M1002_g
 + N_B1_N_c_82_n B1_N PM_SKY130_FD_SC_HS__A21BOI_2%B1_N

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice
index af779f0..656941d 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_2.spice
-* Created: Thu Aug 27 20:24:33 2020
+* Created: Tue Sep  1 19:49:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.lvs.report b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.lvs.report
new file mode 100644
index 0000000..fab5a73
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.lvs.report

@@ -0,0 +1,505 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21boi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21boi_4.sp ('sky130_fd_sc_hs__a21boi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice ('sky130_fd_sc_hs__a21boi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:25 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21boi_4     sky130_fd_sc_hs__a21boi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21boi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21boi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         13        13         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        28        27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   26 layout mos transistors were reduced to 7.
+     19 mos transistors were deleted by parallel reduction.
+   26 source mos transistors were reduced to 7.
+     19 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pex.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pex.spice
index 11488bb..7badc02 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_4.pex.spice
-* Created: Thu Aug 27 20:24:41 2020
+* Created: Tue Sep  1 19:49:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pxi.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pxi.spice
index fe80840..2a94af1 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_4.pxi.spice
-* Created: Thu Aug 27 20:24:41 2020
+* Created: Tue Sep  1 19:49:28 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21BOI_4%A1 N_A1_c_125_n N_A1_M1015_g N_A1_M1003_g
 + N_A1_c_126_n N_A1_M1017_g N_A1_M1005_g N_A1_c_127_n N_A1_M1018_g N_A1_M1006_g

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice
index 10e6c6a..0364d11 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21boi_4.spice
-* Created: Thu Aug 27 20:24:41 2020
+* Created: Tue Sep  1 19:49:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_hs__a21o_1.lvs.report
new file mode 100644
index 0000000..05038f9
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21o_1.sp ('sky130_fd_sc_hs__a21o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_1.spice ('sky130_fd_sc_hs__a21o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:31 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21o_1       sky130_fd_sc_hs__a21o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_hs__a21o_1.pex.spice
index ed954c9..0102725 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_1.pex.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_1.pex.spice
-* Created: Thu Aug 27 20:24:48 2020
+* Created: Tue Sep  1 19:49:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_hs__a21o_1.pxi.spice
index 5f896d9..3c2f60b 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_1.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_1.pxi.spice
-* Created: Thu Aug 27 20:24:48 2020
+* Created: Tue Sep  1 19:49:34 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21O_1%A_81_264# N_A_81_264#_M1006_d N_A_81_264#_M1001_s
 + N_A_81_264#_c_60_n N_A_81_264#_M1000_g N_A_81_264#_c_61_n N_A_81_264#_c_62_n

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_1.spice b/cells/a21o/sky130_fd_sc_hs__a21o_1.spice
index ba8a837..789a465 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_1.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_1.spice
-* Created: Thu Aug 27 20:24:48 2020
+* Created: Tue Sep  1 19:49:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_2.lvs.report b/cells/a21o/sky130_fd_sc_hs__a21o_2.lvs.report
new file mode 100644
index 0000000..1d1d7d4
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_2.lvs.report

@@ -0,0 +1,488 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21o_2.sp ('sky130_fd_sc_hs__a21o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_2.spice ('sky130_fd_sc_hs__a21o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:37 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21o_2       sky130_fd_sc_hs__a21o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_2.pex.spice b/cells/a21o/sky130_fd_sc_hs__a21o_2.pex.spice
index 0ac015f..68a40c4 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_2.pex.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_2.pex.spice
-* Created: Thu Aug 27 20:24:55 2020
+* Created: Tue Sep  1 19:49:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_2.pxi.spice b/cells/a21o/sky130_fd_sc_hs__a21o_2.pxi.spice
index 528cd03..8a301c7 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_2.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_2.pxi.spice
-* Created: Thu Aug 27 20:24:55 2020
+* Created: Tue Sep  1 19:49:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21O_2%A_84_244# N_A_84_244#_M1004_d N_A_84_244#_M1003_s
 + N_A_84_244#_c_67_n N_A_84_244#_M1001_g N_A_84_244#_c_60_n N_A_84_244#_M1000_g

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_2.spice b/cells/a21o/sky130_fd_sc_hs__a21o_2.spice
index 85f891b..547bb92 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_2.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_2.spice
-* Created: Thu Aug 27 20:24:55 2020
+* Created: Tue Sep  1 19:49:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_4.lvs.report b/cells/a21o/sky130_fd_sc_hs__a21o_4.lvs.report
new file mode 100644
index 0000000..82f89f9
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_4.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21o_4.sp ('sky130_fd_sc_hs__a21o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21o/sky130_fd_sc_hs__a21o_4.spice ('sky130_fd_sc_hs__a21o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21o_4       sky130_fd_sc_hs__a21o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_4.pex.spice b/cells/a21o/sky130_fd_sc_hs__a21o_4.pex.spice
index 5ad8055..c344719 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_4.pex.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_4.pex.spice
-* Created: Thu Aug 27 20:25:02 2020
+* Created: Tue Sep  1 19:49:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_4.pxi.spice b/cells/a21o/sky130_fd_sc_hs__a21o_4.pxi.spice
index f6b6aad..fc6c20a 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_4.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_4.pxi.spice
-* Created: Thu Aug 27 20:25:02 2020
+* Created: Tue Sep  1 19:49:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21O_4%A_91_48# N_A_91_48#_M1011_d N_A_91_48#_M1009_s
 + N_A_91_48#_M1000_s N_A_91_48#_M1006_g N_A_91_48#_c_120_n N_A_91_48#_M1002_g

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_4.spice b/cells/a21o/sky130_fd_sc_hs__a21o_4.spice
index abb8bef..610339c 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_4.spice
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21o_4.spice
-* Created: Thu Aug 27 20:25:02 2020
+* Created: Tue Sep  1 19:49:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.lvs.report
new file mode 100644
index 0000000..079dcec
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21oi_1.sp ('sky130_fd_sc_hs__a21oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice ('sky130_fd_sc_hs__a21oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21oi_1      sky130_fd_sc_hs__a21oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pex.spice
index de027d6..3c8447d 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_1.pex.spice
-* Created: Thu Aug 27 20:25:09 2020
+* Created: Tue Sep  1 19:49:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pxi.spice
index 037e7c7..acac574 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_1.pxi.spice
-* Created: Thu Aug 27 20:25:09 2020
+* Created: Tue Sep  1 19:49:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21OI_1%A2 N_A2_c_36_n N_A2_M1001_g N_A2_c_37_n
 + N_A2_M1005_g A2 PM_SKY130_FD_SC_HS__A21OI_1%A2

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice
index 6c1b186..2cce638 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_1.spice
-* Created: Thu Aug 27 20:25:09 2020
+* Created: Tue Sep  1 19:49:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.lvs.report b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.lvs.report
new file mode 100644
index 0000000..fb498c7
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.lvs.report

@@ -0,0 +1,487 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21oi_2.sp ('sky130_fd_sc_hs__a21oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice ('sky130_fd_sc_hs__a21oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:49:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21oi_2      sky130_fd_sc_hs__a21oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        12        11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pex.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pex.spice
index 359b9a5..6762fce 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_2.pex.spice
-* Created: Thu Aug 27 20:25:18 2020
+* Created: Tue Sep  1 19:49:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pxi.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pxi.spice
index dca9935..e34fc18 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_2.pxi.spice
-* Created: Thu Aug 27 20:25:18 2020
+* Created: Tue Sep  1 19:49:56 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21OI_2%B1 N_B1_M1010_g N_B1_c_70_n N_B1_c_76_n
 + N_B1_M1007_g N_B1_c_71_n N_B1_c_78_n N_B1_M1008_g N_B1_c_72_n B1 N_B1_c_74_n

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice
index 1abe868..335a9b3 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_2.spice
-* Created: Thu Aug 27 20:25:18 2020
+* Created: Tue Sep  1 19:49:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.lvs.report b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.lvs.report
new file mode 100644
index 0000000..575b122
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a21oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a21oi_4.sp ('sky130_fd_sc_hs__a21oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice ('sky130_fd_sc_hs__a21oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a21oi_4      sky130_fd_sc_hs__a21oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a21oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a21oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:         10        10         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   22 layout mos transistors were reduced to 6.
+     16 mos transistors were deleted by parallel reduction.
+   22 source mos transistors were reduced to 6.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pex.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pex.spice
index 81c702c..1aafedf 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_4.pex.spice
-* Created: Thu Aug 27 20:25:25 2020
+* Created: Tue Sep  1 19:50:02 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pxi.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pxi.spice
index aef35fe..5ba9133 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_4.pxi.spice
-* Created: Thu Aug 27 20:25:25 2020
+* Created: Tue Sep  1 19:50:02 2020
 * 
 x_PM_SKY130_FD_SC_HS__A21OI_4%A2 N_A2_c_100_n N_A2_M1007_g N_A2_M1004_g
 + N_A2_c_101_n N_A2_M1011_g N_A2_M1015_g N_A2_c_102_n N_A2_M1013_g N_A2_M1016_g

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice
index bf7c7c2..2ab9a69 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a21oi_4.spice
-* Created: Thu Aug 27 20:25:25 2020
+* Created: Tue Sep  1 19:50:02 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_1.lvs.report b/cells/a221o/sky130_fd_sc_hs__a221o_1.lvs.report
new file mode 100644
index 0000000..064133c
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_1.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a221o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a221o_1.sp ('sky130_fd_sc_hs__a221o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_1.spice ('sky130_fd_sc_hs__a221o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:05 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a221o_1      sky130_fd_sc_hs__a221o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a221o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a221o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_1.pex.spice b/cells/a221o/sky130_fd_sc_hs__a221o_1.pex.spice
index 3885108..55cd18d 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_1.pex.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_1.pex.spice
-* Created: Thu Aug 27 20:25:35 2020
+* Created: Tue Sep  1 19:50:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_1.pxi.spice b/cells/a221o/sky130_fd_sc_hs__a221o_1.pxi.spice
index f6aa06f..8b1e62d 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_1.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_1.pxi.spice
-* Created: Thu Aug 27 20:25:35 2020
+* Created: Tue Sep  1 19:50:08 2020
 * 
 x_PM_SKY130_FD_SC_HS__A221O_1%A_148_260# N_A_148_260#_M1002_d
 + N_A_148_260#_M1000_d N_A_148_260#_M1010_d N_A_148_260#_c_69_n

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_1.spice b/cells/a221o/sky130_fd_sc_hs__a221o_1.spice
index 122dbf6..060b158 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_1.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_1.spice
-* Created: Thu Aug 27 20:25:35 2020
+* Created: Tue Sep  1 19:50:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_2.lvs.report b/cells/a221o/sky130_fd_sc_hs__a221o_2.lvs.report
new file mode 100644
index 0000000..913c14a
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a221o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a221o_2.sp ('sky130_fd_sc_hs__a221o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_2.spice ('sky130_fd_sc_hs__a221o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:11 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a221o_2      sky130_fd_sc_hs__a221o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a221o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a221o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 B2 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_2.pex.spice b/cells/a221o/sky130_fd_sc_hs__a221o_2.pex.spice
index 939e581..af430ee 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_2.pex.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_2.pex.spice
-* Created: Thu Aug 27 20:25:42 2020
+* Created: Tue Sep  1 19:50:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_2.pxi.spice b/cells/a221o/sky130_fd_sc_hs__a221o_2.pxi.spice
index 347d2aa..eac2d51 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_2.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_2.pxi.spice
-* Created: Thu Aug 27 20:25:42 2020
+* Created: Tue Sep  1 19:50:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__A221O_2%A_89_260# N_A_89_260#_M1000_d N_A_89_260#_M1013_d
 + N_A_89_260#_M1012_d N_A_89_260#_c_95_n N_A_89_260#_M1003_g N_A_89_260#_M1001_g

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_2.spice b/cells/a221o/sky130_fd_sc_hs__a221o_2.spice
index bdf91f6..1fb4e06 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_2.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_2.spice
-* Created: Thu Aug 27 20:25:42 2020
+* Created: Tue Sep  1 19:50:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_4.lvs.report b/cells/a221o/sky130_fd_sc_hs__a221o_4.lvs.report
new file mode 100644
index 0000000..91347d3
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_4.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a221o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a221o_4.sp ('sky130_fd_sc_hs__a221o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221o/sky130_fd_sc_hs__a221o_4.spice ('sky130_fd_sc_hs__a221o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a221o_4      sky130_fd_sc_hs__a221o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a221o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a221o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 C1 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_4.pex.spice b/cells/a221o/sky130_fd_sc_hs__a221o_4.pex.spice
index 3ac3f16..0be4020 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_4.pex.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_4.pex.spice
-* Created: Thu Aug 27 20:25:49 2020
+* Created: Tue Sep  1 19:50:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_4.pxi.spice b/cells/a221o/sky130_fd_sc_hs__a221o_4.pxi.spice
index f9c495d..486a16a 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_4.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_4.pxi.spice
-* Created: Thu Aug 27 20:25:49 2020
+* Created: Tue Sep  1 19:50:19 2020
 * 
 x_PM_SKY130_FD_SC_HS__A221O_4%A1 N_A1_M1005_g N_A1_c_160_n N_A1_c_161_n
 + N_A1_c_172_n N_A1_M1001_g N_A1_c_162_n N_A1_c_163_n N_A1_M1007_g N_A1_c_165_n

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_4.spice b/cells/a221o/sky130_fd_sc_hs__a221o_4.spice
index 7b26cc1..5d90f68 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_4.spice
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221o_4.spice
-* Created: Thu Aug 27 20:25:49 2020
+* Created: Tue Sep  1 19:50:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.lvs.report b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.lvs.report
new file mode 100644
index 0000000..7a8e4aa
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a221oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a221oi_1.sp ('sky130_fd_sc_hs__a221oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice ('sky130_fd_sc_hs__a221oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:23 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a221oi_1     sky130_fd_sc_hs__a221oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a221oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a221oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pex.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pex.spice
index 47fbdb7..504f329 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_1.pex.spice
-* Created: Thu Aug 27 20:25:56 2020
+* Created: Tue Sep  1 19:50:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pxi.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pxi.spice
index e9f6614..f80fb24 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_1.pxi.spice
-* Created: Thu Aug 27 20:25:56 2020
+* Created: Tue Sep  1 19:50:25 2020
 * 
 x_PM_SKY130_FD_SC_HS__A221OI_1%C1 N_C1_c_56_n N_C1_M1000_g N_C1_M1002_g C1
 + N_C1_c_54_n N_C1_c_55_n PM_SKY130_FD_SC_HS__A221OI_1%C1

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice
index c77dd96..f0d60b7 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_1.spice
-* Created: Thu Aug 27 20:25:56 2020
+* Created: Tue Sep  1 19:50:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.lvs.report b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.lvs.report
new file mode 100644
index 0000000..069d29b
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a221oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a221oi_2.sp ('sky130_fd_sc_hs__a221oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice ('sky130_fd_sc_hs__a221oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:28 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a221oi_2     sky130_fd_sc_hs__a221oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a221oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a221oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 B2 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pex.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pex.spice
index 777f353..60fce6a 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_2.pex.spice
-* Created: Thu Aug 27 20:26:04 2020
+* Created: Tue Sep  1 19:50:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pxi.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pxi.spice
index 919ef26..c48dc0e 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_2.pxi.spice
-* Created: Thu Aug 27 20:26:04 2020
+* Created: Tue Sep  1 19:50:31 2020
 * 
 x_PM_SKY130_FD_SC_HS__A221OI_2%C1 N_C1_c_102_n N_C1_M1000_g N_C1_M1018_g
 + N_C1_c_103_n N_C1_M1001_g N_C1_M1019_g C1 N_C1_c_100_n N_C1_c_101_n

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice
index 7f7c911..7d0c1ed 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_2.spice
-* Created: Thu Aug 27 20:26:04 2020
+* Created: Tue Sep  1 19:50:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.lvs.report b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.lvs.report
new file mode 100644
index 0000000..c9409ba
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.lvs.report

@@ -0,0 +1,516 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a221oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a221oi_4.sp ('sky130_fd_sc_hs__a221oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice ('sky130_fd_sc_hs__a221oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:34 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a221oi_4     sky130_fd_sc_hs__a221oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a221oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a221oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 A2 A1 B1 B2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pex.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pex.spice
index ee196de..c8eac33 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_4.pex.spice
-* Created: Thu Aug 27 20:26:11 2020
+* Created: Tue Sep  1 19:50:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pxi.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pxi.spice
index 134cabc..087adda 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_4.pxi.spice
-* Created: Thu Aug 27 20:26:11 2020
+* Created: Tue Sep  1 19:50:37 2020
 * 
 x_PM_SKY130_FD_SC_HS__A221OI_4%C1 N_C1_c_158_n N_C1_M1002_g N_C1_M1015_g
 + N_C1_c_159_n N_C1_M1003_g N_C1_M1022_g N_C1_c_160_n N_C1_M1005_g N_C1_M1027_g

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice
index b6cde2c..68539b3 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a221oi_4.spice
-* Created: Thu Aug 27 20:26:11 2020
+* Created: Tue Sep  1 19:50:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_1.lvs.report b/cells/a222o/sky130_fd_sc_hs__a222o_1.lvs.report
new file mode 100644
index 0000000..97a0686
--- /dev/null
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_1.lvs.report

@@ -0,0 +1,487 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a222o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a222o_1.sp ('sky130_fd_sc_hs__a222o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_1.spice ('sky130_fd_sc_hs__a222o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:40 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a222o_1      sky130_fd_sc_hs__a222o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a222o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a222o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              17        17
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              12        12
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SPMP_2_2_2 (8 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 C2 B2 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_1.pex.spice b/cells/a222o/sky130_fd_sc_hs__a222o_1.pex.spice
index f0e4680..f17e44c 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_1.pex.spice
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222o_1.pex.spice
-* Created: Thu Aug 27 20:26:19 2020
+* Created: Tue Sep  1 19:50:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_1.pxi.spice b/cells/a222o/sky130_fd_sc_hs__a222o_1.pxi.spice
index 3abdf8e..fe4df11 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_1.pxi.spice
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222o_1.pxi.spice
-* Created: Thu Aug 27 20:26:19 2020
+* Created: Tue Sep  1 19:50:43 2020
 * 
 x_PM_SKY130_FD_SC_HS__A222O_1%C1 N_C1_c_85_n N_C1_c_90_n N_C1_M1011_g
 + N_C1_M1008_g C1 C1 N_C1_c_86_n N_C1_c_87_n N_C1_c_88_n

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_1.spice b/cells/a222o/sky130_fd_sc_hs__a222o_1.spice
index 2c0b6ca..4d3617b 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_1.spice
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222o_1.spice
-* Created: Thu Aug 27 20:26:19 2020
+* Created: Tue Sep  1 19:50:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_2.lvs.report b/cells/a222o/sky130_fd_sc_hs__a222o_2.lvs.report
new file mode 100644
index 0000000..1cb831b
--- /dev/null
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_2.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a222o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a222o_2.sp ('sky130_fd_sc_hs__a222o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222o/sky130_fd_sc_hs__a222o_2.spice ('sky130_fd_sc_hs__a222o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:46 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a222o_2      sky130_fd_sc_hs__a222o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a222o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a222o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              12        12
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SPMP_2_2_2 (8 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 C2 A1 B1 B2 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_2.pex.spice b/cells/a222o/sky130_fd_sc_hs__a222o_2.pex.spice
index e5a506e..11e49e4 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_2.pex.spice
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222o_2.pex.spice
-* Created: Thu Aug 27 20:26:26 2020
+* Created: Tue Sep  1 19:50:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_2.pxi.spice b/cells/a222o/sky130_fd_sc_hs__a222o_2.pxi.spice
index d0cb58b..6766d9e 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_2.pxi.spice
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222o_2.pxi.spice
-* Created: Thu Aug 27 20:26:26 2020
+* Created: Tue Sep  1 19:50:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__A222O_2%C1 N_C1_M1002_g N_C1_M1006_g N_C1_c_91_n
 + N_C1_c_95_n C1 N_C1_c_92_n N_C1_c_93_n PM_SKY130_FD_SC_HS__A222O_2%C1

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_2.spice b/cells/a222o/sky130_fd_sc_hs__a222o_2.spice
index e01c150..dfd0727 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_2.spice
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222o_2.spice
-* Created: Thu Aug 27 20:26:26 2020
+* Created: Tue Sep  1 19:50:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.lvs.report b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.lvs.report
new file mode 100644
index 0000000..ca5a122
--- /dev/null
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a222oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a222oi_1.sp ('sky130_fd_sc_hs__a222oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice ('sky130_fd_sc_hs__a222oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:52 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a222oi_1     sky130_fd_sc_hs__a222oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a222oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a222oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              16        16
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              11        11
+
+ Instances:          3         3         SMN2 (4 pins)
+                     1         1         SPMP_2_2_2 (8 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           3          3            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 C2 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pex.spice b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pex.spice
index 4b0241e..217c8ca 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pex.spice
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222oi_1.pex.spice
-* Created: Thu Aug 27 20:26:36 2020
+* Created: Tue Sep  1 19:50:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pxi.spice b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pxi.spice
index cc8385e..af90f64 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pxi.spice
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222oi_1.pxi.spice
-* Created: Thu Aug 27 20:26:36 2020
+* Created: Tue Sep  1 19:50:54 2020
 * 
 x_PM_SKY130_FD_SC_HS__A222OI_1%C1 N_C1_c_70_n N_C1_c_75_n N_C1_M1006_g
 + N_C1_M1007_g C1 N_C1_c_71_n N_C1_c_72_n N_C1_c_73_n

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice
index d7623e2..69c04a5 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222oi_1.spice
-* Created: Thu Aug 27 20:26:36 2020
+* Created: Tue Sep  1 19:50:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.lvs.report b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.lvs.report
new file mode 100644
index 0000000..2d2d4c6
--- /dev/null
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a222oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a222oi_2.sp ('sky130_fd_sc_hs__a222oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice ('sky130_fd_sc_hs__a222oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:50:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a222oi_2     sky130_fd_sc_hs__a222oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a222oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a222oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              16        16
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              11        11
+
+ Instances:          3         3         SMN2 (4 pins)
+                     1         1         SPMP_2_2_2 (8 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           3          3            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 12.
+     12 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 12.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C2 C1 B1 B2 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pex.spice b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pex.spice
index a0f6e41..799ccad 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pex.spice
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222oi_2.pex.spice
-* Created: Thu Aug 27 20:26:44 2020
+* Created: Tue Sep  1 19:51:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pxi.spice b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pxi.spice
index bf7a6fa..c4bd7c5 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pxi.spice
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222oi_2.pxi.spice
-* Created: Thu Aug 27 20:26:44 2020
+* Created: Tue Sep  1 19:51:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__A222OI_2%C2 N_C2_c_126_n N_C2_c_136_n N_C2_M1009_g
 + N_C2_M1014_g N_C2_c_137_n N_C2_M1012_g N_C2_M1016_g N_C2_c_128_n N_C2_c_129_n

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice
index b8484d5..cd9f57e 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a222oi_2.spice
-* Created: Thu Aug 27 20:26:44 2020
+* Created: Tue Sep  1 19:51:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_1.lvs.report b/cells/a22o/sky130_fd_sc_hs__a22o_1.lvs.report
new file mode 100644
index 0000000..6d122fa
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a22o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a22o_1.sp ('sky130_fd_sc_hs__a22o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_1.spice ('sky130_fd_sc_hs__a22o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a22o_1       sky130_fd_sc_hs__a22o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a22o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a22o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 B2 B1 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_1.pex.spice b/cells/a22o/sky130_fd_sc_hs__a22o_1.pex.spice
index e22e584..572270a 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_1.pex.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_1.pex.spice
-* Created: Thu Aug 27 20:26:51 2020
+* Created: Tue Sep  1 19:51:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_1.pxi.spice b/cells/a22o/sky130_fd_sc_hs__a22o_1.pxi.spice
index 0052936..81b17b5 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_1.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_1.pxi.spice
-* Created: Thu Aug 27 20:26:51 2020
+* Created: Tue Sep  1 19:51:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__A22O_1%A2 N_A2_c_57_n N_A2_c_58_n N_A2_c_63_n N_A2_M1009_g
 + N_A2_M1002_g A2 N_A2_c_61_n PM_SKY130_FD_SC_HS__A22O_1%A2

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_1.spice b/cells/a22o/sky130_fd_sc_hs__a22o_1.spice
index 7fe1a60..09e532d 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_1.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_1.spice
-* Created: Thu Aug 27 20:26:51 2020
+* Created: Tue Sep  1 19:51:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_2.lvs.report b/cells/a22o/sky130_fd_sc_hs__a22o_2.lvs.report
new file mode 100644
index 0000000..dd69fa2
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a22o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a22o_2.sp ('sky130_fd_sc_hs__a22o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_2.spice ('sky130_fd_sc_hs__a22o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a22o_2       sky130_fd_sc_hs__a22o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a22o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a22o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 B1 B2 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_2.pex.spice b/cells/a22o/sky130_fd_sc_hs__a22o_2.pex.spice
index 6cbf40d..7952c0e 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_2.pex.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_2.pex.spice
-* Created: Thu Aug 27 20:26:58 2020
+* Created: Tue Sep  1 19:51:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_2.pxi.spice b/cells/a22o/sky130_fd_sc_hs__a22o_2.pxi.spice
index 3da4b52..e91b8f8 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_2.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_2.pxi.spice
-* Created: Thu Aug 27 20:26:58 2020
+* Created: Tue Sep  1 19:51:12 2020
 * 
 x_PM_SKY130_FD_SC_HS__A22O_2%A_81_48# N_A_81_48#_M1009_d N_A_81_48#_M1004_d
 + N_A_81_48#_c_66_n N_A_81_48#_M1000_g N_A_81_48#_c_73_n N_A_81_48#_M1001_g

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_2.spice b/cells/a22o/sky130_fd_sc_hs__a22o_2.spice
index 6c84522..09e719e 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_2.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_2.spice
-* Created: Thu Aug 27 20:26:58 2020
+* Created: Tue Sep  1 19:51:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_4.lvs.report b/cells/a22o/sky130_fd_sc_hs__a22o_4.lvs.report
new file mode 100644
index 0000000..43c0045
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_4.lvs.report

@@ -0,0 +1,502 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a22o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a22o_4.sp ('sky130_fd_sc_hs__a22o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22o/sky130_fd_sc_hs__a22o_4.spice ('sky130_fd_sc_hs__a22o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a22o_4       sky130_fd_sc_hs__a22o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a22o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a22o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_4.pex.spice b/cells/a22o/sky130_fd_sc_hs__a22o_4.pex.spice
index 84bab2e..9b7a218 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_4.pex.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_4.pex.spice
-* Created: Thu Aug 27 20:27:05 2020
+* Created: Tue Sep  1 19:51:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_4.pxi.spice b/cells/a22o/sky130_fd_sc_hs__a22o_4.pxi.spice
index c0d941c..0a493d7 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_4.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_4.pxi.spice
-* Created: Thu Aug 27 20:27:05 2020
+* Created: Tue Sep  1 19:51:17 2020
 * 
 x_PM_SKY130_FD_SC_HS__A22O_4%A_95_306# N_A_95_306#_M1004_d N_A_95_306#_M1006_d
 + N_A_95_306#_M1012_d N_A_95_306#_M1016_s N_A_95_306#_c_147_n

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_4.spice b/cells/a22o/sky130_fd_sc_hs__a22o_4.spice
index 28277ad..52b0a45 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_4.spice
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22o_4.spice
-* Created: Thu Aug 27 20:27:05 2020
+* Created: Tue Sep  1 19:51:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.lvs.report b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.lvs.report
new file mode 100644
index 0000000..5011872
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a22oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a22oi_1.sp ('sky130_fd_sc_hs__a22oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice ('sky130_fd_sc_hs__a22oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a22oi_1      sky130_fd_sc_hs__a22oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a22oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a22oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pex.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pex.spice
index 5d9cea3..be7dff4 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_1.pex.spice
-* Created: Thu Aug 27 20:27:12 2020
+* Created: Tue Sep  1 19:51:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pxi.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pxi.spice
index 2451c0d..b110d25 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_1.pxi.spice
-* Created: Thu Aug 27 20:27:12 2020
+* Created: Tue Sep  1 19:51:23 2020
 * 
 x_PM_SKY130_FD_SC_HS__A22OI_1%B2 N_B2_c_49_n N_B2_M1000_g N_B2_M1004_g
 + N_B2_c_46_n N_B2_c_47_n B2 B2 PM_SKY130_FD_SC_HS__A22OI_1%B2

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice
index df17540..7e06e87 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_1.spice
-* Created: Thu Aug 27 20:27:12 2020
+* Created: Tue Sep  1 19:51:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.lvs.report b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.lvs.report
new file mode 100644
index 0000000..c36071b
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a22oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a22oi_2.sp ('sky130_fd_sc_hs__a22oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice ('sky130_fd_sc_hs__a22oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a22oi_2      sky130_fd_sc_hs__a22oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a22oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a22oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pex.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pex.spice
index 574e2a5..f1c6d4b 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_2.pex.spice
-* Created: Thu Aug 27 20:27:20 2020
+* Created: Tue Sep  1 19:51:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pxi.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pxi.spice
index cae33d5..e0fbcf2 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_2.pxi.spice
-* Created: Thu Aug 27 20:27:20 2020
+* Created: Tue Sep  1 19:51:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__A22OI_2%A1 N_A1_M1003_g N_A1_c_81_n N_A1_M1005_g
 + N_A1_M1014_g N_A1_c_87_n N_A1_M1010_g N_A1_c_83_n N_A1_c_89_n N_A1_c_96_p

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice
index f78f10f..c26fa54 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_2.spice
-* Created: Thu Aug 27 20:27:20 2020
+* Created: Tue Sep  1 19:51:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.lvs.report b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.lvs.report
new file mode 100644
index 0000000..8fd1e12
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a22oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a22oi_4.sp ('sky130_fd_sc_hs__a22oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice ('sky130_fd_sc_hs__a22oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a22oi_4      sky130_fd_sc_hs__a22oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a22oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a22oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   32 layout mos transistors were reduced to 8.
+     24 mos transistors were deleted by parallel reduction.
+   32 source mos transistors were reduced to 8.
+     24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pex.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pex.spice
index a137ec9..c056587 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_4.pex.spice
-* Created: Thu Aug 27 20:27:28 2020
+* Created: Tue Sep  1 19:51:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pxi.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pxi.spice
index 0cee209..6814c01 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_4.pxi.spice
-* Created: Thu Aug 27 20:27:28 2020
+* Created: Tue Sep  1 19:51:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__A22OI_4%B2 N_B2_c_125_n N_B2_M1019_g N_B2_M1008_g
 + N_B2_M1013_g N_B2_c_126_n N_B2_M1023_g N_B2_M1016_g N_B2_c_127_n N_B2_M1026_g

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice
index e8607a8..971f844 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a22oi_4.spice
-* Created: Thu Aug 27 20:27:28 2020
+* Created: Tue Sep  1 19:51:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.lvs.report b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.lvs.report
new file mode 100644
index 0000000..dc7325f
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.lvs.report

@@ -0,0 +1,487 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2bb2o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2bb2o_1.sp ('sky130_fd_sc_hs__a2bb2o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice ('sky130_fd_sc_hs__a2bb2o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2bb2o_1     sky130_fd_sc_hs__a2bb2o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2bb2o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2bb2o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pex.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pex.spice
index 3afbeaa..265de46 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_1.pex.spice
-* Created: Thu Aug 27 20:27:38 2020
+* Created: Tue Sep  1 19:51:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pxi.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pxi.spice
index 1b0af3f..5bd51d0 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_1.pxi.spice
-* Created: Thu Aug 27 20:27:38 2020
+* Created: Tue Sep  1 19:51:40 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2BB2O_1%A_93_264# N_A_93_264#_M1001_d N_A_93_264#_M1005_s
 + N_A_93_264#_c_81_n N_A_93_264#_M1002_g N_A_93_264#_M1008_g N_A_93_264#_c_83_n

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice
index 9d454bc..cf7b361 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_1.spice
-* Created: Thu Aug 27 20:27:38 2020
+* Created: Tue Sep  1 19:51:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.lvs.report b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.lvs.report
new file mode 100644
index 0000000..46be55d
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2bb2o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2bb2o_2.sp ('sky130_fd_sc_hs__a2bb2o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice ('sky130_fd_sc_hs__a2bb2o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2bb2o_2     sky130_fd_sc_hs__a2bb2o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2bb2o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2bb2o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pex.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pex.spice
index d23fbae..ebfb4f1 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_2.pex.spice
-* Created: Thu Aug 27 20:27:45 2020
+* Created: Tue Sep  1 19:51:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pxi.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pxi.spice
index d845646..f0f9073 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_2.pxi.spice
-* Created: Thu Aug 27 20:27:45 2020
+* Created: Tue Sep  1 19:51:46 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2BB2O_2%B1 N_B1_c_89_n N_B1_c_95_n N_B1_M1011_g
 + N_B1_c_90_n N_B1_M1008_g N_B1_c_91_n N_B1_c_92_n B1

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice
index b9cfa56..43dcf83 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_2.spice
-* Created: Thu Aug 27 20:27:45 2020
+* Created: Tue Sep  1 19:51:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.lvs.report b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.lvs.report
new file mode 100644
index 0000000..81934de
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.lvs.report

@@ -0,0 +1,503 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2bb2o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2bb2o_4.sp ('sky130_fd_sc_hs__a2bb2o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice ('sky130_fd_sc_hs__a2bb2o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2bb2o_4     sky130_fd_sc_hs__a2bb2o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2bb2o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2bb2o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         11        11         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        24        23
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   18 layout mos transistors were reduced to 7.
+     11 mos transistors were deleted by parallel reduction.
+   18 source mos transistors were reduced to 7.
+     11 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pex.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pex.spice
index f8f969f..235e308 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_4.pex.spice
-* Created: Thu Aug 27 20:27:52 2020
+* Created: Tue Sep  1 19:51:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pxi.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pxi.spice
index 4b0ec3c..697e35b 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_4.pxi.spice
-* Created: Thu Aug 27 20:27:52 2020
+* Created: Tue Sep  1 19:51:52 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2BB2O_4%A_162_48# N_A_162_48#_M1013_d N_A_162_48#_M1003_s
 + N_A_162_48#_M1005_d N_A_162_48#_M1002_g N_A_162_48#_c_157_n

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice
index 20f30f9..b7a426f 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2o_4.spice
-* Created: Thu Aug 27 20:27:52 2020
+* Created: Tue Sep  1 19:51:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.lvs.report b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.lvs.report
new file mode 100644
index 0000000..9d27a3f
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2bb2oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2bb2oi_1.sp ('sky130_fd_sc_hs__a2bb2oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice ('sky130_fd_sc_hs__a2bb2oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:51:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2bb2oi_1    sky130_fd_sc_hs__a2bb2oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2bb2oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2bb2oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pex.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pex.spice
index fe7b2cd..210ffb2 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_1.pex.spice
-* Created: Thu Aug 27 20:27:59 2020
+* Created: Tue Sep  1 19:51:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pxi.spice
index 0b09cee..a6c9729 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_1.pxi.spice
-* Created: Thu Aug 27 20:27:59 2020
+* Created: Tue Sep  1 19:51:58 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2BB2OI_1%A1_N N_A1_N_c_61_n N_A1_N_c_66_n N_A1_N_M1001_g
 + N_A1_N_M1000_g A1_N N_A1_N_c_63_n N_A1_N_c_64_n

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice
index f3e7b68..79ae9ce 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_1.spice
-* Created: Thu Aug 27 20:27:59 2020
+* Created: Tue Sep  1 19:51:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.lvs.report b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.lvs.report
new file mode 100644
index 0000000..3b7feea
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2bb2oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2bb2oi_2.sp ('sky130_fd_sc_hs__a2bb2oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice ('sky130_fd_sc_hs__a2bb2oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2bb2oi_2    sky130_fd_sc_hs__a2bb2oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2bb2oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2bb2oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pex.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pex.spice
index 238da15..ba844b6 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_2.pex.spice
-* Created: Thu Aug 27 20:28:06 2020
+* Created: Tue Sep  1 19:52:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pxi.spice
index 91b1d28..ab85c93 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_2.pxi.spice
-* Created: Thu Aug 27 20:28:06 2020
+* Created: Tue Sep  1 19:52:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2BB2OI_2%A1_N N_A1_N_c_94_n N_A1_N_c_95_n N_A1_N_c_96_n
 + N_A1_N_c_101_n N_A1_N_M1006_g N_A1_N_M1010_g A1_N N_A1_N_c_98_n N_A1_N_c_99_n

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice
index 6b09fff..e994888 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_2.spice
-* Created: Thu Aug 27 20:28:06 2020
+* Created: Tue Sep  1 19:52:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.lvs.report b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.lvs.report
new file mode 100644
index 0000000..8dba019
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.lvs.report

@@ -0,0 +1,508 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a2bb2oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a2bb2oi_4.sp ('sky130_fd_sc_hs__a2bb2oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice ('sky130_fd_sc_hs__a2bb2oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a2bb2oi_4    sky130_fd_sc_hs__a2bb2oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a2bb2oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a2bb2oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         14        14         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2_N A1_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pex.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pex.spice
index 23da81b..7214883 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_4.pex.spice
-* Created: Thu Aug 27 20:28:14 2020
+* Created: Tue Sep  1 19:52:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pxi.spice
index a295462..a31aebf 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_4.pxi.spice
-* Created: Thu Aug 27 20:28:14 2020
+* Created: Tue Sep  1 19:52:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__A2BB2OI_4%A2_N N_A2_N_c_147_n N_A2_N_M1020_g
 + N_A2_N_c_148_n N_A2_N_M1021_g N_A2_N_c_142_n N_A2_N_c_143_n N_A2_N_c_144_n

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice
index d5f5d67..3858c7f 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a2bb2oi_4.spice
-* Created: Thu Aug 27 20:28:14 2020
+* Created: Tue Sep  1 19:52:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_1.lvs.report b/cells/a311o/sky130_fd_sc_hs__a311o_1.lvs.report
new file mode 100644
index 0000000..585eaa5
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_1.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a311o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a311o_1.sp ('sky130_fd_sc_hs__a311o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_1.spice ('sky130_fd_sc_hs__a311o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a311o_1      sky130_fd_sc_hs__a311o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a311o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a311o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_1.pex.spice b/cells/a311o/sky130_fd_sc_hs__a311o_1.pex.spice
index 6e21d51..4c55402 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_1.pex.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_1.pex.spice
-* Created: Thu Aug 27 20:28:22 2020
+* Created: Tue Sep  1 19:52:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_1.pxi.spice b/cells/a311o/sky130_fd_sc_hs__a311o_1.pxi.spice
index 3370d8c..a187f6f 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_1.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_1.pxi.spice
-* Created: Thu Aug 27 20:28:22 2020
+* Created: Tue Sep  1 19:52:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__A311O_1%A_89_270# N_A_89_270#_M1006_d N_A_89_270#_M1001_d
 + N_A_89_270#_M1008_d N_A_89_270#_c_75_n N_A_89_270#_M1007_g N_A_89_270#_c_76_n

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_1.spice b/cells/a311o/sky130_fd_sc_hs__a311o_1.spice
index cbff5b4..d6fd083 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_1.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_1.spice
-* Created: Thu Aug 27 20:28:22 2020
+* Created: Tue Sep  1 19:52:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_2.lvs.report b/cells/a311o/sky130_fd_sc_hs__a311o_2.lvs.report
new file mode 100644
index 0000000..81121ac
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a311o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a311o_2.sp ('sky130_fd_sc_hs__a311o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_2.spice ('sky130_fd_sc_hs__a311o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a311o_2      sky130_fd_sc_hs__a311o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a311o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a311o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_2.pex.spice b/cells/a311o/sky130_fd_sc_hs__a311o_2.pex.spice
index b230d98..9b72bba 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_2.pex.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_2.pex.spice
-* Created: Thu Aug 27 20:28:29 2020
+* Created: Tue Sep  1 19:52:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_2.pxi.spice b/cells/a311o/sky130_fd_sc_hs__a311o_2.pxi.spice
index 5373ef5..38f1fee 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_2.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_2.pxi.spice
-* Created: Thu Aug 27 20:28:29 2020
+* Created: Tue Sep  1 19:52:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__A311O_2%A_21_270# N_A_21_270#_M1013_d N_A_21_270#_M1011_d
 + N_A_21_270#_M1004_d N_A_21_270#_c_93_n N_A_21_270#_M1003_g N_A_21_270#_M1008_g

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_2.spice b/cells/a311o/sky130_fd_sc_hs__a311o_2.spice
index 9613056..4dded4c 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_2.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_2.spice
-* Created: Thu Aug 27 20:28:29 2020
+* Created: Tue Sep  1 19:52:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_4.lvs.report b/cells/a311o/sky130_fd_sc_hs__a311o_4.lvs.report
new file mode 100644
index 0000000..4519bee
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_4.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a311o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a311o_4.sp ('sky130_fd_sc_hs__a311o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311o/sky130_fd_sc_hs__a311o_4.spice ('sky130_fd_sc_hs__a311o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a311o_4      sky130_fd_sc_hs__a311o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a311o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a311o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A3 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_4.pex.spice b/cells/a311o/sky130_fd_sc_hs__a311o_4.pex.spice
index 5b0039f..3990abf 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_4.pex.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_4.pex.spice
-* Created: Thu Aug 27 20:28:39 2020
+* Created: Tue Sep  1 19:52:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_4.pxi.spice b/cells/a311o/sky130_fd_sc_hs__a311o_4.pxi.spice
index def98c6..dfc18d4 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_4.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_4.pxi.spice
-* Created: Thu Aug 27 20:28:39 2020
+* Created: Tue Sep  1 19:52:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__A311O_4%C1 N_C1_c_142_n N_C1_M1006_g N_C1_M1014_g
 + N_C1_c_143_n N_C1_M1007_g N_C1_M1025_g C1 N_C1_c_141_n

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_4.spice b/cells/a311o/sky130_fd_sc_hs__a311o_4.spice
index 37c6b6b..382c38f 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_4.spice
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311o_4.spice
-* Created: Thu Aug 27 20:28:39 2020
+* Created: Tue Sep  1 19:52:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.lvs.report b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.lvs.report
new file mode 100644
index 0000000..be785fd
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a311oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a311oi_1.sp ('sky130_fd_sc_hs__a311oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice ('sky130_fd_sc_hs__a311oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a311oi_1     sky130_fd_sc_hs__a311oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a311oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a311oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pex.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pex.spice
index 1cabe45..2785634 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_1.pex.spice
-* Created: Thu Aug 27 20:28:46 2020
+* Created: Tue Sep  1 19:52:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pxi.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pxi.spice
index a9754ad..cd84e5c 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_1.pxi.spice
-* Created: Thu Aug 27 20:28:46 2020
+* Created: Tue Sep  1 19:52:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__A311OI_1%A3 N_A3_c_60_n N_A3_M1000_g N_A3_M1004_g
 + N_A3_c_57_n N_A3_c_58_n A3 A3 PM_SKY130_FD_SC_HS__A311OI_1%A3

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice
index c52453f..81a2c12 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_1.spice
-* Created: Thu Aug 27 20:28:46 2020
+* Created: Tue Sep  1 19:52:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.lvs.report b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.lvs.report
new file mode 100644
index 0000000..e0bcace
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a311oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a311oi_2.sp ('sky130_fd_sc_hs__a311oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice ('sky130_fd_sc_hs__a311oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a311oi_2     sky130_fd_sc_hs__a311oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a311oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a311oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pex.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pex.spice
index 71210a4..8aeae23 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_2.pex.spice
-* Created: Thu Aug 27 20:28:54 2020
+* Created: Tue Sep  1 19:52:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pxi.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pxi.spice
index 7d5b1c2..cad7fdd 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_2.pxi.spice
-* Created: Thu Aug 27 20:28:54 2020
+* Created: Tue Sep  1 19:52:38 2020
 * 
 x_PM_SKY130_FD_SC_HS__A311OI_2%A3 N_A3_c_93_n N_A3_M1001_g N_A3_c_89_n
 + N_A3_M1008_g N_A3_c_90_n N_A3_M1009_g N_A3_c_94_n N_A3_M1002_g A3 N_A3_c_92_n

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice
index 5890db8..f5e16ca 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_2.spice
-* Created: Thu Aug 27 20:28:54 2020
+* Created: Tue Sep  1 19:52:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.lvs.report b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.lvs.report
new file mode 100644
index 0000000..04a7e70
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.lvs.report

@@ -0,0 +1,512 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a311oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a311oi_4.sp ('sky130_fd_sc_hs__a311oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice ('sky130_fd_sc_hs__a311oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:41 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a311oi_4     sky130_fd_sc_hs__a311oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a311oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a311oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         16        16         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        37        36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   36 layout mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+   36 source mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pex.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pex.spice
index 9abd2d0..eca10a9 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_4.pex.spice
-* Created: Thu Aug 27 20:29:01 2020
+* Created: Tue Sep  1 19:52:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pxi.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pxi.spice
index 8c64e59..d270e20 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_4.pxi.spice
-* Created: Thu Aug 27 20:29:01 2020
+* Created: Tue Sep  1 19:52:44 2020
 * 
 x_PM_SKY130_FD_SC_HS__A311OI_4%A3 N_A3_c_155_n N_A3_M1003_g N_A3_M1009_g
 + N_A3_c_156_n N_A3_M1004_g N_A3_M1027_g N_A3_M1032_g N_A3_c_157_n N_A3_M1007_g

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice
index b9c47ee..aac51e1 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a311oi_4.spice
-* Created: Thu Aug 27 20:29:01 2020
+* Created: Tue Sep  1 19:52:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_1.lvs.report b/cells/a31o/sky130_fd_sc_hs__a31o_1.lvs.report
new file mode 100644
index 0000000..ef1d064
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a31o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a31o_1.sp ('sky130_fd_sc_hs__a31o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_1.spice ('sky130_fd_sc_hs__a31o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:47 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a31o_1       sky130_fd_sc_hs__a31o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a31o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a31o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_1.pex.spice b/cells/a31o/sky130_fd_sc_hs__a31o_1.pex.spice
index 06ebcb2..4f0fa03 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_1.pex.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_1.pex.spice
-* Created: Thu Aug 27 20:29:08 2020
+* Created: Tue Sep  1 19:52:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_1.pxi.spice b/cells/a31o/sky130_fd_sc_hs__a31o_1.pxi.spice
index 94919ee..2075f54 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_1.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_1.pxi.spice
-* Created: Thu Aug 27 20:29:08 2020
+* Created: Tue Sep  1 19:52:50 2020
 * 
 x_PM_SKY130_FD_SC_HS__A31O_1%A_81_270# N_A_81_270#_M1009_d N_A_81_270#_M1005_d
 + N_A_81_270#_c_57_n N_A_81_270#_M1000_g N_A_81_270#_c_58_n N_A_81_270#_M1007_g

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_1.spice b/cells/a31o/sky130_fd_sc_hs__a31o_1.spice
index c90fda2..56feb2d 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_1.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_1.spice
-* Created: Thu Aug 27 20:29:08 2020
+* Created: Tue Sep  1 19:52:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_2.lvs.report b/cells/a31o/sky130_fd_sc_hs__a31o_2.lvs.report
new file mode 100644
index 0000000..104be72
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a31o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a31o_2.sp ('sky130_fd_sc_hs__a31o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_2.spice ('sky130_fd_sc_hs__a31o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:53 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a31o_2       sky130_fd_sc_hs__a31o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a31o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a31o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_2.pex.spice b/cells/a31o/sky130_fd_sc_hs__a31o_2.pex.spice
index 2c9a693..03b3055 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_2.pex.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_2.pex.spice
-* Created: Thu Aug 27 20:29:15 2020
+* Created: Tue Sep  1 19:52:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_2.pxi.spice b/cells/a31o/sky130_fd_sc_hs__a31o_2.pxi.spice
index 5c8ec0b..ecf3a39 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_2.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_2.pxi.spice
-* Created: Thu Aug 27 20:29:15 2020
+* Created: Tue Sep  1 19:52:56 2020
 * 
 x_PM_SKY130_FD_SC_HS__A31O_2%A_97_296# N_A_97_296#_M1007_d N_A_97_296#_M1001_d
 + N_A_97_296#_M1005_g N_A_97_296#_c_62_n N_A_97_296#_M1008_g N_A_97_296#_M1006_g

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_2.spice b/cells/a31o/sky130_fd_sc_hs__a31o_2.spice
index 9638182..00f0b74 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_2.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_2.spice
-* Created: Thu Aug 27 20:29:15 2020
+* Created: Tue Sep  1 19:52:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_4.lvs.report b/cells/a31o/sky130_fd_sc_hs__a31o_4.lvs.report
new file mode 100644
index 0000000..21a77a0
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_4.lvs.report

@@ -0,0 +1,502 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a31o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a31o_4.sp ('sky130_fd_sc_hs__a31o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31o/sky130_fd_sc_hs__a31o_4.spice ('sky130_fd_sc_hs__a31o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:52:59 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a31o_4       sky130_fd_sc_hs__a31o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a31o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a31o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 A3 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_4.pex.spice b/cells/a31o/sky130_fd_sc_hs__a31o_4.pex.spice
index 58b5fa3..7bf251b 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_4.pex.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_4.pex.spice
-* Created: Thu Aug 27 20:29:23 2020
+* Created: Tue Sep  1 19:53:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_4.pxi.spice b/cells/a31o/sky130_fd_sc_hs__a31o_4.pxi.spice
index 4351c2f..9835f81 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_4.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_4.pxi.spice
-* Created: Thu Aug 27 20:29:23 2020
+* Created: Tue Sep  1 19:53:01 2020
 * 
 x_PM_SKY130_FD_SC_HS__A31O_4%A_83_274# N_A_83_274#_M1002_d N_A_83_274#_M1007_d
 + N_A_83_274#_M1013_d N_A_83_274#_M1000_s N_A_83_274#_c_140_n

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_4.spice b/cells/a31o/sky130_fd_sc_hs__a31o_4.spice
index 825750c..237dc79 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_4.spice
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31o_4.spice
-* Created: Thu Aug 27 20:29:23 2020
+* Created: Tue Sep  1 19:53:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.lvs.report b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.lvs.report
new file mode 100644
index 0000000..7f602e2
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a31oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a31oi_1.sp ('sky130_fd_sc_hs__a31oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice ('sky130_fd_sc_hs__a31oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:05 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a31oi_1      sky130_fd_sc_hs__a31oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a31oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a31oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pex.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pex.spice
index 25624d6..4e12722 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_1.pex.spice
-* Created: Thu Aug 27 20:29:31 2020
+* Created: Tue Sep  1 19:53:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pxi.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pxi.spice
index 1bcc47a..71d80cc 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_1.pxi.spice
-* Created: Thu Aug 27 20:29:31 2020
+* Created: Tue Sep  1 19:53:07 2020
 * 
 x_PM_SKY130_FD_SC_HS__A31OI_1%A3 N_A3_c_44_n N_A3_M1000_g N_A3_c_45_n
 + N_A3_M1007_g N_A3_c_46_n A3 PM_SKY130_FD_SC_HS__A31OI_1%A3

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice
index 0af7663..b71c30b 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_1.spice
-* Created: Thu Aug 27 20:29:31 2020
+* Created: Tue Sep  1 19:53:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.lvs.report b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.lvs.report
new file mode 100644
index 0000000..8db684f
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.lvs.report

@@ -0,0 +1,491 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a31oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a31oi_2.sp ('sky130_fd_sc_hs__a31oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice ('sky130_fd_sc_hs__a31oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a31oi_2      sky130_fd_sc_hs__a31oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a31oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a31oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          7         7         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        16        15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 7.
+     7 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 7.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 B1 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pex.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pex.spice
index 9e8021e..876672e 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_2.pex.spice
-* Created: Thu Aug 27 20:29:41 2020
+* Created: Tue Sep  1 19:53:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pxi.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pxi.spice
index 74987fb..084232f 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_2.pxi.spice
-* Created: Thu Aug 27 20:29:41 2020
+* Created: Tue Sep  1 19:53:13 2020
 * 
 x_PM_SKY130_FD_SC_HS__A31OI_2%A3 N_A3_c_71_n N_A3_M1011_g N_A3_c_72_n
 + N_A3_M1008_g N_A3_c_73_n N_A3_M1013_g N_A3_c_74_n N_A3_M1010_g N_A3_c_75_n

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice
index 9a01ed2..8bd49b9 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_2.spice
-* Created: Thu Aug 27 20:29:41 2020
+* Created: Tue Sep  1 19:53:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.lvs.report b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.lvs.report
new file mode 100644
index 0000000..7eb5e02
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a31oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a31oi_4.sp ('sky130_fd_sc_hs__a31oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice ('sky130_fd_sc_hs__a31oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:16 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a31oi_4      sky130_fd_sc_hs__a31oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a31oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a31oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         14        14         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   30 layout mos transistors were reduced to 8.
+     22 mos transistors were deleted by parallel reduction.
+   30 source mos transistors were reduced to 8.
+     22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pex.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pex.spice
index d15a175..98663fd 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_4.pex.spice
-* Created: Thu Aug 27 20:29:48 2020
+* Created: Tue Sep  1 19:53:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pxi.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pxi.spice
index 54ebd15..d13097b 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_4.pxi.spice
-* Created: Thu Aug 27 20:29:48 2020
+* Created: Tue Sep  1 19:53:19 2020
 * 
 x_PM_SKY130_FD_SC_HS__A31OI_4%A3 N_A3_c_129_n N_A3_M1006_g N_A3_M1005_g
 + N_A3_M1007_g N_A3_c_130_n N_A3_M1010_g N_A3_M1028_g N_A3_c_131_n N_A3_M1011_g

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice
index 760ee79..04e9a65 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a31oi_4.spice
-* Created: Thu Aug 27 20:29:48 2020
+* Created: Tue Sep  1 19:53:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_1.lvs.report b/cells/a32o/sky130_fd_sc_hs__a32o_1.lvs.report
new file mode 100644
index 0000000..e21063f
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_1.lvs.report

@@ -0,0 +1,487 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a32o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a32o_1.sp ('sky130_fd_sc_hs__a32o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_1.spice ('sky130_fd_sc_hs__a32o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:22 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a32o_1       sky130_fd_sc_hs__a32o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a32o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a32o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_2 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_1.pex.spice b/cells/a32o/sky130_fd_sc_hs__a32o_1.pex.spice
index 7be6427..38c8d66 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_1.pex.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_1.pex.spice
-* Created: Thu Aug 27 20:29:56 2020
+* Created: Tue Sep  1 19:53:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_1.pxi.spice b/cells/a32o/sky130_fd_sc_hs__a32o_1.pxi.spice
index 5e2d1ed..7625c96 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_1.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_1.pxi.spice
-* Created: Thu Aug 27 20:29:56 2020
+* Created: Tue Sep  1 19:53:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__A32O_1%A_84_48# N_A_84_48#_M1011_d N_A_84_48#_M1008_d
 + N_A_84_48#_M1010_g N_A_84_48#_c_55_n N_A_84_48#_M1000_g N_A_84_48#_c_56_n

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_1.spice b/cells/a32o/sky130_fd_sc_hs__a32o_1.spice
index a0a8892..0121329 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_1.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_1.spice
-* Created: Thu Aug 27 20:29:56 2020
+* Created: Tue Sep  1 19:53:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_2.lvs.report b/cells/a32o/sky130_fd_sc_hs__a32o_2.lvs.report
new file mode 100644
index 0000000..d7d206a
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_2.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a32o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a32o_2.sp ('sky130_fd_sc_hs__a32o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_2.spice ('sky130_fd_sc_hs__a32o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:28 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a32o_2       sky130_fd_sc_hs__a32o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a32o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a32o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_2 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A3 A2 A1 B1 B2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_2.pex.spice b/cells/a32o/sky130_fd_sc_hs__a32o_2.pex.spice
index 62157b0..2989843 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_2.pex.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_2.pex.spice
-* Created: Thu Aug 27 20:30:03 2020
+* Created: Tue Sep  1 19:53:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_2.pxi.spice b/cells/a32o/sky130_fd_sc_hs__a32o_2.pxi.spice
index 66301e4..ff07f14 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_2.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_2.pxi.spice
-* Created: Thu Aug 27 20:30:03 2020
+* Created: Tue Sep  1 19:53:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__A32O_2%A_45_264# N_A_45_264#_M1013_d N_A_45_264#_M1006_d
 + N_A_45_264#_c_78_n N_A_45_264#_M1010_g N_A_45_264#_M1003_g N_A_45_264#_c_79_n

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_2.spice b/cells/a32o/sky130_fd_sc_hs__a32o_2.spice
index 0af0262..7ee4c3f 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_2.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_2.spice
-* Created: Thu Aug 27 20:30:03 2020
+* Created: Tue Sep  1 19:53:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_4.lvs.report b/cells/a32o/sky130_fd_sc_hs__a32o_4.lvs.report
new file mode 100644
index 0000000..c74bc52
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_4.lvs.report

@@ -0,0 +1,508 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a32o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a32o_4.sp ('sky130_fd_sc_hs__a32o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32o/sky130_fd_sc_hs__a32o_4.spice ('sky130_fd_sc_hs__a32o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:33 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a32o_4       sky130_fd_sc_hs__a32o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a32o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a32o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_2 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A2 A1 A3 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_4.pex.spice b/cells/a32o/sky130_fd_sc_hs__a32o_4.pex.spice
index 9f7cb72..7bec616 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_4.pex.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_4.pex.spice
-* Created: Thu Aug 27 20:30:10 2020
+* Created: Tue Sep  1 19:53:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_4.pxi.spice b/cells/a32o/sky130_fd_sc_hs__a32o_4.pxi.spice
index 570174a..7b02d1f 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_4.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_4.pxi.spice
-* Created: Thu Aug 27 20:30:10 2020
+* Created: Tue Sep  1 19:53:36 2020
 * 
 x_PM_SKY130_FD_SC_HS__A32O_4%A_83_283# N_A_83_283#_M1001_d N_A_83_283#_M1026_d
 + N_A_83_283#_M1021_s N_A_83_283#_M1023_d N_A_83_283#_c_146_n

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_4.spice b/cells/a32o/sky130_fd_sc_hs__a32o_4.spice
index 7597daf..e6f8269 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_4.spice
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32o_4.spice
-* Created: Thu Aug 27 20:30:10 2020
+* Created: Tue Sep  1 19:53:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.lvs.report b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.lvs.report
new file mode 100644
index 0000000..0e7ba75
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a32oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a32oi_1.sp ('sky130_fd_sc_hs__a32oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice ('sky130_fd_sc_hs__a32oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:39 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a32oi_1      sky130_fd_sc_hs__a32oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a32oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a32oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_2 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pex.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pex.spice
index ca9e0a9..4969652 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_1.pex.spice
-* Created: Thu Aug 27 20:30:18 2020
+* Created: Tue Sep  1 19:53:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pxi.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pxi.spice
index e9fd3d9..11472a8 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_1.pxi.spice
-* Created: Thu Aug 27 20:30:18 2020
+* Created: Tue Sep  1 19:53:42 2020
 * 
 x_PM_SKY130_FD_SC_HS__A32OI_1%B2 N_B2_c_46_n N_B2_M1004_g N_B2_c_47_n
 + N_B2_M1002_g B2 PM_SKY130_FD_SC_HS__A32OI_1%B2

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice
index d6fa5f3..65c2a67 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_1.spice
-* Created: Thu Aug 27 20:30:18 2020
+* Created: Tue Sep  1 19:53:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.lvs.report b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.lvs.report
new file mode 100644
index 0000000..3563447
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a32oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a32oi_2.sp ('sky130_fd_sc_hs__a32oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice ('sky130_fd_sc_hs__a32oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:45 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a32oi_2      sky130_fd_sc_hs__a32oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a32oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a32oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_2 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pex.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pex.spice
index 98292e7..34db433 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_2.pex.spice
-* Created: Thu Aug 27 20:30:26 2020
+* Created: Tue Sep  1 19:53:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pxi.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pxi.spice
index d6a8374..f074e47 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_2.pxi.spice
-* Created: Thu Aug 27 20:30:26 2020
+* Created: Tue Sep  1 19:53:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__A32OI_2%B2 N_B2_M1015_g N_B2_c_104_n N_B2_M1004_g
 + N_B2_M1018_g N_B2_c_105_n N_B2_M1010_g N_B2_c_101_n B2 N_B2_c_102_n

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice
index d557ed6..a66506d 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_2.spice
-* Created: Thu Aug 27 20:30:26 2020
+* Created: Tue Sep  1 19:53:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.lvs.report b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.lvs.report
new file mode 100644
index 0000000..64b757b
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.lvs.report

@@ -0,0 +1,516 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a32oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a32oi_4.sp ('sky130_fd_sc_hs__a32oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice ('sky130_fd_sc_hs__a32oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:51 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a32oi_4      sky130_fd_sc_hs__a32oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a32oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a32oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SPMP_3_2 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SPMP_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pex.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pex.spice
index a4b351c..11f9a6d 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_4.pex.spice
-* Created: Thu Aug 27 20:30:33 2020
+* Created: Tue Sep  1 19:53:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pxi.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pxi.spice
index f8d7291..573f246 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_4.pxi.spice
-* Created: Thu Aug 27 20:30:33 2020
+* Created: Tue Sep  1 19:53:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__A32OI_4%B2 N_B2_M1004_g N_B2_c_150_n N_B2_M1005_g
 + N_B2_M1006_g N_B2_c_151_n N_B2_M1010_g N_B2_M1025_g N_B2_c_152_n N_B2_M1015_g

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice
index b09e57b..d487b20 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a32oi_4.spice
-* Created: Thu Aug 27 20:30:33 2020
+* Created: Tue Sep  1 19:53:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_1.lvs.report b/cells/a41o/sky130_fd_sc_hs__a41o_1.lvs.report
new file mode 100644
index 0000000..50d1e92
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_1.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a41o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a41o_1.sp ('sky130_fd_sc_hs__a41o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_1.spice ('sky130_fd_sc_hs__a41o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:53:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a41o_1       sky130_fd_sc_hs__a41o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a41o_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a41o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                     1         1         SPMP_4_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                        1          1            0            0    SPMP_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 A3 A4 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_1.pex.spice b/cells/a41o/sky130_fd_sc_hs__a41o_1.pex.spice
index 4c7ea58..71c6b7d 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_1.pex.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_1.pex.spice
-* Created: Thu Aug 27 20:30:43 2020
+* Created: Tue Sep  1 19:53:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_1.pxi.spice b/cells/a41o/sky130_fd_sc_hs__a41o_1.pxi.spice
index e45a7fc..bfcbb62 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_1.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_1.pxi.spice
-* Created: Thu Aug 27 20:30:43 2020
+* Created: Tue Sep  1 19:53:59 2020
 * 
 x_PM_SKY130_FD_SC_HS__A41O_1%A_83_244# N_A_83_244#_M1008_d N_A_83_244#_M1003_s
 + N_A_83_244#_c_81_n N_A_83_244#_M1007_g N_A_83_244#_c_73_n N_A_83_244#_M1005_g

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_1.spice b/cells/a41o/sky130_fd_sc_hs__a41o_1.spice
index b9a45b1..8c841c0 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_1.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_1.spice
-* Created: Thu Aug 27 20:30:43 2020
+* Created: Tue Sep  1 19:53:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_2.lvs.report b/cells/a41o/sky130_fd_sc_hs__a41o_2.lvs.report
new file mode 100644
index 0000000..4adc42f
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a41o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a41o_2.sp ('sky130_fd_sc_hs__a41o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_2.spice ('sky130_fd_sc_hs__a41o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:02 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a41o_2       sky130_fd_sc_hs__a41o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a41o_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a41o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                     1         1         SPMP_4_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                        1          1            0            0    SPMP_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A4 A3 A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_2.pex.spice b/cells/a41o/sky130_fd_sc_hs__a41o_2.pex.spice
index 5e55bed..35f4c93 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_2.pex.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_2.pex.spice
-* Created: Thu Aug 27 20:30:51 2020
+* Created: Tue Sep  1 19:54:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_2.pxi.spice b/cells/a41o/sky130_fd_sc_hs__a41o_2.pxi.spice
index 925e6e5..0eeb7e1 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_2.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_2.pxi.spice
-* Created: Thu Aug 27 20:30:51 2020
+* Created: Tue Sep  1 19:54:05 2020
 * 
 x_PM_SKY130_FD_SC_HS__A41O_2%A4 N_A4_c_81_n N_A4_c_86_n N_A4_M1005_g N_A4_c_82_n
 + N_A4_M1007_g A4 N_A4_c_84_n PM_SKY130_FD_SC_HS__A41O_2%A4

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_2.spice b/cells/a41o/sky130_fd_sc_hs__a41o_2.spice
index 122dbdb..d53e2b1 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_2.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_2.spice
-* Created: Thu Aug 27 20:30:51 2020
+* Created: Tue Sep  1 19:54:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_4.lvs.report b/cells/a41o/sky130_fd_sc_hs__a41o_4.lvs.report
new file mode 100644
index 0000000..02a8d36
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_4.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a41o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a41o_4.sp ('sky130_fd_sc_hs__a41o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41o/sky130_fd_sc_hs__a41o_4.spice ('sky130_fd_sc_hs__a41o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:08 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a41o_4       sky130_fd_sc_hs__a41o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a41o_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a41o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                     1         1         SPMP_4_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                        1          1            0            0    SPMP_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 A3 A4 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_4.pex.spice b/cells/a41o/sky130_fd_sc_hs__a41o_4.pex.spice
index 8b9b1c4..7c363e1 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_4.pex.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_4.pex.spice
-* Created: Thu Aug 27 20:30:58 2020
+* Created: Tue Sep  1 19:54:11 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_4.pxi.spice b/cells/a41o/sky130_fd_sc_hs__a41o_4.pxi.spice
index a12c500..25e3ee3 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_4.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_4.pxi.spice
-* Created: Thu Aug 27 20:30:58 2020
+* Created: Tue Sep  1 19:54:11 2020
 * 
 x_PM_SKY130_FD_SC_HS__A41O_4%B1 N_B1_M1012_g N_B1_c_139_n N_B1_M1006_g
 + N_B1_M1017_g N_B1_c_140_n N_B1_M1010_g B1 N_B1_c_137_n N_B1_c_138_n

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_4.spice b/cells/a41o/sky130_fd_sc_hs__a41o_4.spice
index eeaf6ce..859045c 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_4.spice
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41o_4.spice
-* Created: Thu Aug 27 20:30:58 2020
+* Created: Tue Sep  1 19:54:11 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.lvs.report b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.lvs.report
new file mode 100644
index 0000000..dcc9800
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a41oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a41oi_1.sp ('sky130_fd_sc_hs__a41oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice ('sky130_fd_sc_hs__a41oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:14 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a41oi_1      sky130_fd_sc_hs__a41oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a41oi_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__a41oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN4 (6 pins)
+                     1         1         SPMP_4_1 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN4
+                        1          1            0            0    SPMP_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A4 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pex.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pex.spice
index 770c35f..758ecaa 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_1.pex.spice
-* Created: Thu Aug 27 20:31:05 2020
+* Created: Tue Sep  1 19:54:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pxi.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pxi.spice
index 2f7860f..687ba00 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_1.pxi.spice
-* Created: Thu Aug 27 20:31:05 2020
+* Created: Tue Sep  1 19:54:17 2020
 * 
 x_PM_SKY130_FD_SC_HS__A41OI_1%B1 N_B1_M1008_g N_B1_c_50_n N_B1_M1006_g B1
 + N_B1_c_51_n PM_SKY130_FD_SC_HS__A41OI_1%B1

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice
index da7053d..0569873 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_1.spice
-* Created: Thu Aug 27 20:31:05 2020
+* Created: Tue Sep  1 19:54:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.lvs.report b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.lvs.report
new file mode 100644
index 0000000..10c8580
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.lvs.report

@@ -0,0 +1,495 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a41oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a41oi_2.sp ('sky130_fd_sc_hs__a41oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice ('sky130_fd_sc_hs__a41oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a41oi_2      sky130_fd_sc_hs__a41oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a41oi_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__a41oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          9         9         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        20        19
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN4 (6 pins)
+                     1         1         SPMP_4_1 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN4
+                        1          1            0            0    SPMP_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   18 layout mos transistors were reduced to 9.
+     9 mos transistors were deleted by parallel reduction.
+   18 source mos transistors were reduced to 9.
+     9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pex.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pex.spice
index 709d4de..d547911 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_2.pex.spice
-* Created: Thu Aug 27 20:31:13 2020
+* Created: Tue Sep  1 19:54:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pxi.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pxi.spice
index 47e1371..b1470a6 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_2.pxi.spice
-* Created: Thu Aug 27 20:31:13 2020
+* Created: Tue Sep  1 19:54:22 2020
 * 
 x_PM_SKY130_FD_SC_HS__A41OI_2%B1 N_B1_c_93_n N_B1_M1008_g N_B1_M1012_g
 + N_B1_c_94_n N_B1_M1011_g B1 B1 N_B1_c_91_n N_B1_c_92_n

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice
index fe74d60..9037e7e 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_2.spice
-* Created: Thu Aug 27 20:31:13 2020
+* Created: Tue Sep  1 19:54:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.lvs.report b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.lvs.report
new file mode 100644
index 0000000..a2f6f6f
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.lvs.report

@@ -0,0 +1,514 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__a41oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__a41oi_4.sp ('sky130_fd_sc_hs__a41oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice ('sky130_fd_sc_hs__a41oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__a41oi_4      sky130_fd_sc_hs__a41oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__a41oi_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__a41oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         18        18         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN4 (6 pins)
+                     1         1         SPMP_4_1 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN4
+                        1          1            0            0    SPMP_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   38 layout mos transistors were reduced to 10.
+     28 mos transistors were deleted by parallel reduction.
+   38 source mos transistors were reduced to 10.
+     28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pex.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pex.spice
index 1ba4e1a..f93da80 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_4.pex.spice
-* Created: Thu Aug 27 20:31:20 2020
+* Created: Tue Sep  1 19:54:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pxi.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pxi.spice
index c990b46..89c0efa 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_4.pxi.spice
-* Created: Thu Aug 27 20:31:20 2020
+* Created: Tue Sep  1 19:54:28 2020
 * 
 x_PM_SKY130_FD_SC_HS__A41OI_4%B1 N_B1_M1016_g N_B1_c_154_n N_B1_M1014_g
 + N_B1_M1035_g N_B1_c_155_n N_B1_M1018_g N_B1_c_156_n N_B1_M1019_g N_B1_c_151_n

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice
index 385ed86..5e36fe9 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__a41oi_4.spice
-* Created: Thu Aug 27 20:31:20 2020
+* Created: Tue Sep  1 19:54:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and2/sky130_fd_sc_hs__and2_1.lvs.report b/cells/and2/sky130_fd_sc_hs__and2_1.lvs.report
new file mode 100644
index 0000000..fb690bb
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_hs__and2_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and2_1.sp ('sky130_fd_sc_hs__and2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_1.spice ('sky130_fd_sc_hs__and2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and2_1       sky130_fd_sc_hs__and2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and2/sky130_fd_sc_hs__and2_1.pex.spice b/cells/and2/sky130_fd_sc_hs__and2_1.pex.spice
index 1cb9cbf..85e2794 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_1.pex.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_1.pex.spice
-* Created: Thu Aug 27 20:31:28 2020
+* Created: Tue Sep  1 19:54:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and2/sky130_fd_sc_hs__and2_1.pxi.spice b/cells/and2/sky130_fd_sc_hs__and2_1.pxi.spice
index 244548f..c7d6f7c 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_1.pxi.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_1.pxi.spice
-* Created: Thu Aug 27 20:31:28 2020
+* Created: Tue Sep  1 19:54:34 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND2_1%A N_A_c_47_n N_A_M1003_g N_A_c_49_n N_A_c_54_n
 + N_A_M1004_g N_A_c_50_n A A N_A_c_52_n PM_SKY130_FD_SC_HS__AND2_1%A

diff --git a/cells/and2/sky130_fd_sc_hs__and2_1.spice b/cells/and2/sky130_fd_sc_hs__and2_1.spice
index 9b2c50c..8bdbabc 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_1.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_1.spice
-* Created: Thu Aug 27 20:31:28 2020
+* Created: Tue Sep  1 19:54:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and2/sky130_fd_sc_hs__and2_2.lvs.report b/cells/and2/sky130_fd_sc_hs__and2_2.lvs.report
new file mode 100644
index 0000000..dc2f785
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_hs__and2_2.lvs.report

@@ -0,0 +1,484 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and2_2.sp ('sky130_fd_sc_hs__and2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_2.spice ('sky130_fd_sc_hs__and2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:37 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and2_2       sky130_fd_sc_hs__and2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and2/sky130_fd_sc_hs__and2_2.pex.spice b/cells/and2/sky130_fd_sc_hs__and2_2.pex.spice
index 2f55bf9..b98f8cc 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_2.pex.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_2.pex.spice
-* Created: Thu Aug 27 20:31:36 2020
+* Created: Tue Sep  1 19:54:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and2/sky130_fd_sc_hs__and2_2.pxi.spice b/cells/and2/sky130_fd_sc_hs__and2_2.pxi.spice
index 3cb05e1..54003ac 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_2.pxi.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_2.pxi.spice
-* Created: Thu Aug 27 20:31:36 2020
+* Created: Tue Sep  1 19:54:40 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND2_2%A N_A_c_52_n N_A_c_57_n N_A_M1001_g N_A_M1006_g A
 + N_A_c_54_n N_A_c_55_n PM_SKY130_FD_SC_HS__AND2_2%A

diff --git a/cells/and2/sky130_fd_sc_hs__and2_2.spice b/cells/and2/sky130_fd_sc_hs__and2_2.spice
index 126d74c..07e0b0e 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_2.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_2.spice
-* Created: Thu Aug 27 20:31:36 2020
+* Created: Tue Sep  1 19:54:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and2/sky130_fd_sc_hs__and2_4.lvs.report b/cells/and2/sky130_fd_sc_hs__and2_4.lvs.report
new file mode 100644
index 0000000..0224a3c
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_hs__and2_4.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and2_4.sp ('sky130_fd_sc_hs__and2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2/sky130_fd_sc_hs__and2_4.spice ('sky130_fd_sc_hs__and2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and2_4       sky130_fd_sc_hs__and2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and2/sky130_fd_sc_hs__and2_4.pex.spice b/cells/and2/sky130_fd_sc_hs__and2_4.pex.spice
index c2e6ec4..445702a 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_4.pex.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_4.pex.spice
-* Created: Thu Aug 27 20:31:46 2020
+* Created: Tue Sep  1 19:54:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and2/sky130_fd_sc_hs__and2_4.pxi.spice b/cells/and2/sky130_fd_sc_hs__and2_4.pxi.spice
index 8ab9b79..4f5c893 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_4.pxi.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_4.pxi.spice
-* Created: Thu Aug 27 20:31:46 2020
+* Created: Tue Sep  1 19:54:46 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND2_4%A_83_269# N_A_83_269#_M1005_d N_A_83_269#_M1000_d
 + N_A_83_269#_M1007_d N_A_83_269#_c_84_n N_A_83_269#_M1002_g N_A_83_269#_c_94_n

diff --git a/cells/and2/sky130_fd_sc_hs__and2_4.spice b/cells/and2/sky130_fd_sc_hs__and2_4.spice
index 376d998..a976d58 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_4.spice
+++ b/cells/and2/sky130_fd_sc_hs__and2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2_4.spice
-* Created: Thu Aug 27 20:31:46 2020
+* Created: Tue Sep  1 19:54:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_1.lvs.report b/cells/and2b/sky130_fd_sc_hs__and2b_1.lvs.report
new file mode 100644
index 0000000..ae242b6
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and2b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and2b_1.sp ('sky130_fd_sc_hs__and2b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_1.spice ('sky130_fd_sc_hs__and2b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and2b_1      sky130_fd_sc_hs__and2b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and2b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_1.pex.spice b/cells/and2b/sky130_fd_sc_hs__and2b_1.pex.spice
index 0c95e82..4fb3599 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_1.pex.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_1.pex.spice
-* Created: Thu Aug 27 20:31:53 2020
+* Created: Tue Sep  1 19:54:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_1.pxi.spice b/cells/and2b/sky130_fd_sc_hs__and2b_1.pxi.spice
index 158c17c..5df4ecb 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_1.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_1.pxi.spice
-* Created: Thu Aug 27 20:31:53 2020
+* Created: Tue Sep  1 19:54:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND2B_1%A_N N_A_N_M1007_g N_A_N_c_62_n N_A_N_c_66_n
 + N_A_N_M1002_g A_N A_N N_A_N_c_63_n N_A_N_c_64_n

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_1.spice b/cells/and2b/sky130_fd_sc_hs__and2b_1.spice
index 3f39b79..3ca8f8e 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_1.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_1.spice
-* Created: Thu Aug 27 20:31:53 2020
+* Created: Tue Sep  1 19:54:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_2.lvs.report b/cells/and2b/sky130_fd_sc_hs__and2b_2.lvs.report
new file mode 100644
index 0000000..782ad33
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_2.lvs.report

@@ -0,0 +1,486 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and2b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and2b_2.sp ('sky130_fd_sc_hs__and2b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_2.spice ('sky130_fd_sc_hs__and2b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:54:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and2b_2      sky130_fd_sc_hs__and2b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and2b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_2.pex.spice b/cells/and2b/sky130_fd_sc_hs__and2b_2.pex.spice
index 4449aa5..6a82836 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_2.pex.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_2.pex.spice
-* Created: Thu Aug 27 20:32:00 2020
+* Created: Tue Sep  1 19:54:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_2.pxi.spice b/cells/and2b/sky130_fd_sc_hs__and2b_2.pxi.spice
index 2903071..5e25a9a 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_2.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_2.pxi.spice
-* Created: Thu Aug 27 20:32:00 2020
+* Created: Tue Sep  1 19:54:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND2B_2%A_N N_A_N_M1008_g N_A_N_c_59_n N_A_N_M1004_g A_N
 + N_A_N_c_60_n PM_SKY130_FD_SC_HS__AND2B_2%A_N

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_2.spice b/cells/and2b/sky130_fd_sc_hs__and2b_2.spice
index 0aba092..e0ba95a 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_2.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_2.spice
-* Created: Thu Aug 27 20:32:00 2020
+* Created: Tue Sep  1 19:54:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_4.lvs.report b/cells/and2b/sky130_fd_sc_hs__and2b_4.lvs.report
new file mode 100644
index 0000000..a39558f
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_4.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and2b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and2b_4.sp ('sky130_fd_sc_hs__and2b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and2b/sky130_fd_sc_hs__and2b_4.spice ('sky130_fd_sc_hs__and2b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and2b_4      sky130_fd_sc_hs__and2b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and2b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_4.pex.spice b/cells/and2b/sky130_fd_sc_hs__and2b_4.pex.spice
index 9c2797e..78dd4c3 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_4.pex.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_4.pex.spice
-* Created: Thu Aug 27 20:32:08 2020
+* Created: Tue Sep  1 19:55:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_4.pxi.spice b/cells/and2b/sky130_fd_sc_hs__and2b_4.pxi.spice
index bdb6e9a..b3200db 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_4.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_4.pxi.spice
-* Created: Thu Aug 27 20:32:08 2020
+* Created: Tue Sep  1 19:55:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND2B_4%A_N N_A_N_c_109_n N_A_N_M1016_g N_A_N_M1011_g A_N
 + PM_SKY130_FD_SC_HS__AND2B_4%A_N

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_4.spice b/cells/and2b/sky130_fd_sc_hs__and2b_4.spice
index 08ad6ec..7b9ac10 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_4.spice
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and2b_4.spice
-* Created: Thu Aug 27 20:32:08 2020
+* Created: Tue Sep  1 19:55:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and3/sky130_fd_sc_hs__and3_1.lvs.report b/cells/and3/sky130_fd_sc_hs__and3_1.lvs.report
new file mode 100644
index 0000000..7914186
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_hs__and3_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and3_1.sp ('sky130_fd_sc_hs__and3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_1.spice ('sky130_fd_sc_hs__and3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and3_1       sky130_fd_sc_hs__and3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and3/sky130_fd_sc_hs__and3_1.pex.spice b/cells/and3/sky130_fd_sc_hs__and3_1.pex.spice
index eb101a6..00480f1 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_1.pex.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_1.pex.spice
-* Created: Thu Aug 27 20:32:15 2020
+* Created: Tue Sep  1 19:55:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and3/sky130_fd_sc_hs__and3_1.pxi.spice b/cells/and3/sky130_fd_sc_hs__and3_1.pxi.spice
index 2eec396..874a08c 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_1.pxi.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_1.pxi.spice
-* Created: Thu Aug 27 20:32:15 2020
+* Created: Tue Sep  1 19:55:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND3_1%A N_A_c_54_n N_A_c_62_n N_A_M1002_g N_A_c_55_n
 + N_A_M1003_g N_A_c_57_n N_A_c_58_n A N_A_c_60_n PM_SKY130_FD_SC_HS__AND3_1%A

diff --git a/cells/and3/sky130_fd_sc_hs__and3_1.spice b/cells/and3/sky130_fd_sc_hs__and3_1.spice
index 9da721f..ed3f7a5 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_1.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_1.spice
-* Created: Thu Aug 27 20:32:15 2020
+* Created: Tue Sep  1 19:55:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and3/sky130_fd_sc_hs__and3_2.lvs.report b/cells/and3/sky130_fd_sc_hs__and3_2.lvs.report
new file mode 100644
index 0000000..c0422b2
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_hs__and3_2.lvs.report

@@ -0,0 +1,486 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and3_2.sp ('sky130_fd_sc_hs__and3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_2.spice ('sky130_fd_sc_hs__and3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and3_2       sky130_fd_sc_hs__and3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and3/sky130_fd_sc_hs__and3_2.pex.spice b/cells/and3/sky130_fd_sc_hs__and3_2.pex.spice
index 4fc67b7..c70b03a 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_2.pex.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_2.pex.spice
-* Created: Thu Aug 27 20:32:22 2020
+* Created: Tue Sep  1 19:55:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and3/sky130_fd_sc_hs__and3_2.pxi.spice b/cells/and3/sky130_fd_sc_hs__and3_2.pxi.spice
index 86c18d7..667e627 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_2.pxi.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_2.pxi.spice
-* Created: Thu Aug 27 20:32:22 2020
+* Created: Tue Sep  1 19:55:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND3_2%A N_A_c_56_n N_A_c_57_n N_A_c_63_n N_A_M1002_g
 + N_A_c_58_n N_A_M1008_g A A A N_A_c_61_n PM_SKY130_FD_SC_HS__AND3_2%A

diff --git a/cells/and3/sky130_fd_sc_hs__and3_2.spice b/cells/and3/sky130_fd_sc_hs__and3_2.spice
index 63e385d..94a1b75 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_2.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_2.spice
-* Created: Thu Aug 27 20:32:22 2020
+* Created: Tue Sep  1 19:55:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and3/sky130_fd_sc_hs__and3_4.lvs.report b/cells/and3/sky130_fd_sc_hs__and3_4.lvs.report
new file mode 100644
index 0000000..e2eaa37
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_hs__and3_4.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and3_4.sp ('sky130_fd_sc_hs__and3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3/sky130_fd_sc_hs__and3_4.spice ('sky130_fd_sc_hs__and3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and3_4       sky130_fd_sc_hs__and3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and3/sky130_fd_sc_hs__and3_4.pex.spice b/cells/and3/sky130_fd_sc_hs__and3_4.pex.spice
index 7b1939e..0bed69b 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_4.pex.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_4.pex.spice
-* Created: Thu Aug 27 20:32:30 2020
+* Created: Tue Sep  1 19:55:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and3/sky130_fd_sc_hs__and3_4.pxi.spice b/cells/and3/sky130_fd_sc_hs__and3_4.pxi.spice
index 9ee8c85..8ed2444 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_4.pxi.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_4.pxi.spice
-* Created: Thu Aug 27 20:32:30 2020
+* Created: Tue Sep  1 19:55:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND3_4%A_83_260# N_A_83_260#_M1005_d N_A_83_260#_M1011_d
 + N_A_83_260#_M1004_s N_A_83_260#_M1002_s N_A_83_260#_c_119_n

diff --git a/cells/and3/sky130_fd_sc_hs__and3_4.spice b/cells/and3/sky130_fd_sc_hs__and3_4.spice
index 2ba7f87..18cbfde 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_4.spice
+++ b/cells/and3/sky130_fd_sc_hs__and3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3_4.spice
-* Created: Thu Aug 27 20:32:30 2020
+* Created: Tue Sep  1 19:55:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_1.lvs.report b/cells/and3b/sky130_fd_sc_hs__and3b_1.lvs.report
new file mode 100644
index 0000000..abb1892
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and3b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and3b_1.sp ('sky130_fd_sc_hs__and3b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_1.spice ('sky130_fd_sc_hs__and3b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and3b_1      sky130_fd_sc_hs__and3b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and3b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_1.pex.spice b/cells/and3b/sky130_fd_sc_hs__and3b_1.pex.spice
index 2ae7eed..50082c9 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_1.pex.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_1.pex.spice
-* Created: Thu Aug 27 20:32:38 2020
+* Created: Tue Sep  1 19:55:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_1.pxi.spice b/cells/and3b/sky130_fd_sc_hs__and3b_1.pxi.spice
index dd39fc3..133bd23 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_1.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_1.pxi.spice
-* Created: Thu Aug 27 20:32:38 2020
+* Created: Tue Sep  1 19:55:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND3B_1%A_N N_A_N_M1008_g N_A_N_M1006_g N_A_N_c_69_n
 + N_A_N_c_70_n N_A_N_c_74_n N_A_N_c_75_n A_N A_N N_A_N_c_71_n N_A_N_c_72_n

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_1.spice b/cells/and3b/sky130_fd_sc_hs__and3b_1.spice
index 8b90150..97b8d77 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_1.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_1.spice
-* Created: Thu Aug 27 20:32:38 2020
+* Created: Tue Sep  1 19:55:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_2.lvs.report b/cells/and3b/sky130_fd_sc_hs__and3b_2.lvs.report
new file mode 100644
index 0000000..a218b85
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_2.lvs.report

@@ -0,0 +1,488 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and3b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and3b_2.sp ('sky130_fd_sc_hs__and3b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_2.spice ('sky130_fd_sc_hs__and3b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and3b_2      sky130_fd_sc_hs__and3b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and3b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_2.pex.spice b/cells/and3b/sky130_fd_sc_hs__and3b_2.pex.spice
index 8bed705..3dfea16 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_2.pex.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_2.pex.spice
-* Created: Thu Aug 27 20:32:48 2020
+* Created: Tue Sep  1 19:55:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_2.pxi.spice b/cells/and3b/sky130_fd_sc_hs__and3b_2.pxi.spice
index af186bf..f4b911b 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_2.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_2.pxi.spice
-* Created: Thu Aug 27 20:32:48 2020
+* Created: Tue Sep  1 19:55:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND3B_2%A_N N_A_N_c_76_n N_A_N_M1010_g N_A_N_c_81_n
 + N_A_N_M1008_g A_N N_A_N_c_78_n N_A_N_c_79_n PM_SKY130_FD_SC_HS__AND3B_2%A_N

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_2.spice b/cells/and3b/sky130_fd_sc_hs__and3b_2.spice
index c7d1509..99baf7b 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_2.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_2.spice
-* Created: Thu Aug 27 20:32:48 2020
+* Created: Tue Sep  1 19:55:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_4.lvs.report b/cells/and3b/sky130_fd_sc_hs__and3b_4.lvs.report
new file mode 100644
index 0000000..cd0e847
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_4.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and3b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and3b_4.sp ('sky130_fd_sc_hs__and3b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and3b/sky130_fd_sc_hs__and3b_4.spice ('sky130_fd_sc_hs__and3b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:35 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and3b_4      sky130_fd_sc_hs__and3b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and3b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_4.pex.spice b/cells/and3b/sky130_fd_sc_hs__and3b_4.pex.spice
index 3884879..986605e 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_4.pex.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_4.pex.spice
-* Created: Thu Aug 27 20:32:55 2020
+* Created: Tue Sep  1 19:55:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_4.pxi.spice b/cells/and3b/sky130_fd_sc_hs__and3b_4.pxi.spice
index c73145b..d47e826 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_4.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_4.pxi.spice
-* Created: Thu Aug 27 20:32:55 2020
+* Created: Tue Sep  1 19:55:38 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND3B_4%A_N N_A_N_M1020_g N_A_N_c_125_n N_A_N_M1010_g A_N
 + PM_SKY130_FD_SC_HS__AND3B_4%A_N

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_4.spice b/cells/and3b/sky130_fd_sc_hs__and3b_4.spice
index cb6ee16..f7b2666 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_4.spice
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and3b_4.spice
-* Created: Thu Aug 27 20:32:55 2020
+* Created: Tue Sep  1 19:55:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4/sky130_fd_sc_hs__and4_1.lvs.report b/cells/and4/sky130_fd_sc_hs__and4_1.lvs.report
new file mode 100644
index 0000000..daa398c
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_hs__and4_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4_1.sp ('sky130_fd_sc_hs__and4_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_1.spice ('sky130_fd_sc_hs__and4_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:41 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4_1       sky130_fd_sc_hs__and4_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4/sky130_fd_sc_hs__and4_1.pex.spice b/cells/and4/sky130_fd_sc_hs__and4_1.pex.spice
index 6e431b6..7f9edc8 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_1.pex.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_1.pex.spice
-* Created: Thu Aug 27 20:33:02 2020
+* Created: Tue Sep  1 19:55:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4/sky130_fd_sc_hs__and4_1.pxi.spice b/cells/and4/sky130_fd_sc_hs__and4_1.pxi.spice
index 70a3bbf..09f0d51 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_1.pxi.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_1.pxi.spice
-* Created: Thu Aug 27 20:33:02 2020
+* Created: Tue Sep  1 19:55:44 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4_1%A N_A_c_76_n N_A_c_77_n N_A_M1005_g N_A_M1009_g
 + N_A_c_71_n N_A_c_72_n N_A_c_73_n A A N_A_c_74_n N_A_c_75_n

diff --git a/cells/and4/sky130_fd_sc_hs__and4_1.spice b/cells/and4/sky130_fd_sc_hs__and4_1.spice
index da411a0..5bebbc8 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_1.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_1.spice
-* Created: Thu Aug 27 20:33:02 2020
+* Created: Tue Sep  1 19:55:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4/sky130_fd_sc_hs__and4_2.lvs.report b/cells/and4/sky130_fd_sc_hs__and4_2.lvs.report
new file mode 100644
index 0000000..b6837f2
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_hs__and4_2.lvs.report

@@ -0,0 +1,488 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4_2.sp ('sky130_fd_sc_hs__and4_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_2.spice ('sky130_fd_sc_hs__and4_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:47 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4_2       sky130_fd_sc_hs__and4_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4/sky130_fd_sc_hs__and4_2.pex.spice b/cells/and4/sky130_fd_sc_hs__and4_2.pex.spice
index de63a95..e265301 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_2.pex.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_2.pex.spice
-* Created: Thu Aug 27 20:33:10 2020
+* Created: Tue Sep  1 19:55:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4/sky130_fd_sc_hs__and4_2.pxi.spice b/cells/and4/sky130_fd_sc_hs__and4_2.pxi.spice
index 69b96b0..0e34662 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_2.pxi.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_2.pxi.spice
-* Created: Thu Aug 27 20:33:10 2020
+* Created: Tue Sep  1 19:55:50 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4_2%A N_A_c_69_n N_A_c_75_n N_A_M1006_g N_A_M1005_g
 + N_A_c_71_n N_A_c_72_n A N_A_c_73_n PM_SKY130_FD_SC_HS__AND4_2%A

diff --git a/cells/and4/sky130_fd_sc_hs__and4_2.spice b/cells/and4/sky130_fd_sc_hs__and4_2.spice
index b5c8188..4c0d890 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_2.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_2.spice
-* Created: Thu Aug 27 20:33:10 2020
+* Created: Tue Sep  1 19:55:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4/sky130_fd_sc_hs__and4_4.lvs.report b/cells/and4/sky130_fd_sc_hs__and4_4.lvs.report
new file mode 100644
index 0000000..43c9f02
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_hs__and4_4.lvs.report

@@ -0,0 +1,500 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4_4.sp ('sky130_fd_sc_hs__and4_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4/sky130_fd_sc_hs__and4_4.spice ('sky130_fd_sc_hs__and4_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:53 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4_4       sky130_fd_sc_hs__and4_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B D C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4/sky130_fd_sc_hs__and4_4.pex.spice b/cells/and4/sky130_fd_sc_hs__and4_4.pex.spice
index 4fe205d..ee4bb2a 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_4.pex.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_4.pex.spice
-* Created: Thu Aug 27 20:33:17 2020
+* Created: Tue Sep  1 19:55:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4/sky130_fd_sc_hs__and4_4.pxi.spice b/cells/and4/sky130_fd_sc_hs__and4_4.pxi.spice
index 37875dc..62d53f1 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_4.pxi.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_4.pxi.spice
-* Created: Thu Aug 27 20:33:17 2020
+* Created: Tue Sep  1 19:55:56 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4_4%A N_A_M1000_g N_A_c_136_n N_A_M1006_g N_A_M1002_g
 + N_A_c_137_n N_A_M1007_g A N_A_c_135_n PM_SKY130_FD_SC_HS__AND4_4%A

diff --git a/cells/and4/sky130_fd_sc_hs__and4_4.spice b/cells/and4/sky130_fd_sc_hs__and4_4.spice
index f1a9ce7..bd97d9a 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_4.spice
+++ b/cells/and4/sky130_fd_sc_hs__and4_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4_4.spice
-* Created: Thu Aug 27 20:33:17 2020
+* Created: Tue Sep  1 19:55:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_1.lvs.report b/cells/and4b/sky130_fd_sc_hs__and4b_1.lvs.report
new file mode 100644
index 0000000..e4ab77a
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4b_1.sp ('sky130_fd_sc_hs__and4b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_1.spice ('sky130_fd_sc_hs__and4b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:55:59 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4b_1      sky130_fd_sc_hs__and4b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B C D VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_1.pex.spice b/cells/and4b/sky130_fd_sc_hs__and4b_1.pex.spice
index c7d824d..4a4e8e8 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_1.pex.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_1.pex.spice
-* Created: Thu Aug 27 20:33:24 2020
+* Created: Tue Sep  1 19:56:02 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_1.pxi.spice b/cells/and4b/sky130_fd_sc_hs__and4b_1.pxi.spice
index e9b79b4..883e70a 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_1.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_1.pxi.spice
-* Created: Thu Aug 27 20:33:24 2020
+* Created: Tue Sep  1 19:56:02 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4B_1%A_N N_A_N_M1010_g N_A_N_c_85_n N_A_N_M1009_g
 + N_A_N_c_82_n A_N N_A_N_c_83_n N_A_N_c_84_n PM_SKY130_FD_SC_HS__AND4B_1%A_N

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_1.spice b/cells/and4b/sky130_fd_sc_hs__and4b_1.spice
index b244702..a2cbbd3 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_1.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_1.spice
-* Created: Thu Aug 27 20:33:24 2020
+* Created: Tue Sep  1 19:56:02 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_2.lvs.report b/cells/and4b/sky130_fd_sc_hs__and4b_2.lvs.report
new file mode 100644
index 0000000..58bc77b
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4b_2.sp ('sky130_fd_sc_hs__and4b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_2.spice ('sky130_fd_sc_hs__and4b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:05 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4b_2      sky130_fd_sc_hs__and4b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N D C B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_2.pex.spice b/cells/and4b/sky130_fd_sc_hs__and4b_2.pex.spice
index e4f8297..65ac488 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_2.pex.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_2.pex.spice
-* Created: Thu Aug 27 20:33:32 2020
+* Created: Tue Sep  1 19:56:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_2.pxi.spice b/cells/and4b/sky130_fd_sc_hs__and4b_2.pxi.spice
index bc66872..0512b28 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_2.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_2.pxi.spice
-* Created: Thu Aug 27 20:33:32 2020
+* Created: Tue Sep  1 19:56:07 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4B_2%A_N N_A_N_M1006_g N_A_N_c_73_n N_A_N_M1007_g A_N
 + N_A_N_c_74_n PM_SKY130_FD_SC_HS__AND4B_2%A_N

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_2.spice b/cells/and4b/sky130_fd_sc_hs__and4b_2.spice
index a97cca9..08f9f0f 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_2.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_2.spice
-* Created: Thu Aug 27 20:33:32 2020
+* Created: Tue Sep  1 19:56:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_4.lvs.report b/cells/and4b/sky130_fd_sc_hs__and4b_4.lvs.report
new file mode 100644
index 0000000..6a5da1b
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_4.lvs.report

@@ -0,0 +1,502 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4b_4.sp ('sky130_fd_sc_hs__and4b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4b/sky130_fd_sc_hs__and4b_4.spice ('sky130_fd_sc_hs__and4b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4b_4      sky130_fd_sc_hs__and4b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N D C B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_4.pex.spice b/cells/and4b/sky130_fd_sc_hs__and4b_4.pex.spice
index a7fc9ac..e5fc14a 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_4.pex.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_4.pex.spice
-* Created: Thu Aug 27 20:33:40 2020
+* Created: Tue Sep  1 19:56:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_4.pxi.spice b/cells/and4b/sky130_fd_sc_hs__and4b_4.pxi.spice
index 4358375..a10ccf8 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_4.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_4.pxi.spice
-* Created: Thu Aug 27 20:33:40 2020
+* Created: Tue Sep  1 19:56:13 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4B_4%A_N N_A_N_c_137_n N_A_N_M1012_g N_A_N_c_138_n
 + N_A_N_M1013_g A_N PM_SKY130_FD_SC_HS__AND4B_4%A_N

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_4.spice b/cells/and4b/sky130_fd_sc_hs__and4b_4.spice
index d392d4f..49b561c 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_4.spice
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4b_4.spice
-* Created: Thu Aug 27 20:33:40 2020
+* Created: Tue Sep  1 19:56:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.lvs.report b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.lvs.report
new file mode 100644
index 0000000..cc2b963
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4bb_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4bb_1.sp ('sky130_fd_sc_hs__and4bb_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice ('sky130_fd_sc_hs__and4bb_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4bb_1     sky130_fd_sc_hs__and4bb_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4bb_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          3         3         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:        11        11
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:         11         11            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N C D B_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pex.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pex.spice
index ee7f596..5ce3455 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_1.pex.spice
-* Created: Thu Aug 27 20:33:50 2020
+* Created: Tue Sep  1 19:56:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pxi.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pxi.spice
index 184982a..daab671 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_1.pxi.spice
-* Created: Thu Aug 27 20:33:50 2020
+* Created: Tue Sep  1 19:56:19 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4BB_1%A_N N_A_N_M1011_g N_A_N_c_98_n N_A_N_M1008_g A_N
 + N_A_N_c_99_n PM_SKY130_FD_SC_HS__AND4BB_1%A_N

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice
index 9cecd97..d32d3b5 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_1.spice
-* Created: Thu Aug 27 20:33:50 2020
+* Created: Tue Sep  1 19:56:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.lvs.report b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.lvs.report
new file mode 100644
index 0000000..d4db4cf
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4bb_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4bb_2.sp ('sky130_fd_sc_hs__and4bb_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice ('sky130_fd_sc_hs__and4bb_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:22 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4bb_2     sky130_fd_sc_hs__and4bb_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4bb_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          3         3         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:        11        11
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:         11         11            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N C D B_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pex.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pex.spice
index 7f07fe6..59327cc 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_2.pex.spice
-* Created: Thu Aug 27 20:33:57 2020
+* Created: Tue Sep  1 19:56:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pxi.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pxi.spice
index c3a5bb1..749df98 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_2.pxi.spice
-* Created: Thu Aug 27 20:33:57 2020
+* Created: Tue Sep  1 19:56:25 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4BB_2%A_N N_A_N_M1015_g N_A_N_c_97_n N_A_N_M1005_g A_N
 + N_A_N_c_98_n PM_SKY130_FD_SC_HS__AND4BB_2%A_N

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice
index b02f66d..0cbc101 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_2.spice
-* Created: Thu Aug 27 20:33:57 2020
+* Created: Tue Sep  1 19:56:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.lvs.report b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.lvs.report
new file mode 100644
index 0000000..4611db0
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__and4bb_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__and4bb_4.sp ('sky130_fd_sc_hs__and4bb_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice ('sky130_fd_sc_hs__and4bb_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:28 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__and4bb_4     sky130_fd_sc_hs__and4bb_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__and4bb_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__and4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          3         3         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:        11        11
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:         11         11            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B_N A_N C D VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pex.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pex.spice
index 66e58a9..9d2dfd8 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_4.pex.spice
-* Created: Thu Aug 27 20:34:05 2020
+* Created: Tue Sep  1 19:56:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pxi.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pxi.spice
index 653ea2b..001a8a5 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_4.pxi.spice
-* Created: Thu Aug 27 20:34:05 2020
+* Created: Tue Sep  1 19:56:31 2020
 * 
 x_PM_SKY130_FD_SC_HS__AND4BB_4%B_N N_B_N_M1020_g N_B_N_c_153_n N_B_N_M1010_g B_N
 + B_N PM_SKY130_FD_SC_HS__AND4BB_4%B_N

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice
index 12d0b53..afbc106 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__and4bb_4.spice
-* Created: Thu Aug 27 20:34:05 2020
+* Created: Tue Sep  1 19:56:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/buf/sky130_fd_sc_hs__buf_1.lvs.report b/cells/buf/sky130_fd_sc_hs__buf_1.lvs.report
new file mode 100644
index 0000000..c03ea02
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hs__buf_1.lvs.report

@@ -0,0 +1,473 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__buf_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__buf_1.sp ('sky130_fd_sc_hs__buf_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_1.spice ('sky130_fd_sc_hs__buf_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:40 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__buf_1        sky130_fd_sc_hs__buf_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__buf_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__buf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         5         4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/buf/sky130_fd_sc_hs__buf_1.pex.spice b/cells/buf/sky130_fd_sc_hs__buf_1.pex.spice
index 96178d6..69c623d 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_1.pex.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_1.pex.spice
-* Created: Thu Aug 27 20:34:19 2020
+* Created: Tue Sep  1 19:56:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/buf/sky130_fd_sc_hs__buf_1.pxi.spice b/cells/buf/sky130_fd_sc_hs__buf_1.pxi.spice
index 2986517..76209cd 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_1.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_1.pxi.spice
-* Created: Thu Aug 27 20:34:19 2020
+* Created: Tue Sep  1 19:56:42 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUF_1%A N_A_M1002_g N_A_c_37_n N_A_M1001_g N_A_c_38_n A A
 + PM_SKY130_FD_SC_HS__BUF_1%A

diff --git a/cells/buf/sky130_fd_sc_hs__buf_1.spice b/cells/buf/sky130_fd_sc_hs__buf_1.spice
index 8dbe65f..680685a 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_1.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_1.spice
-* Created: Thu Aug 27 20:34:19 2020
+* Created: Tue Sep  1 19:56:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/buf/sky130_fd_sc_hs__buf_16.lvs.report b/cells/buf/sky130_fd_sc_hs__buf_16.lvs.report
new file mode 100644
index 0000000..210a420
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hs__buf_16.lvs.report

@@ -0,0 +1,518 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 99 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 101 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 103 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 105 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__buf_16.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__buf_16.sp ('sky130_fd_sc_hs__buf_16')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_16.spice ('sky130_fd_sc_hs__buf_16')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:34 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__buf_16       sky130_fd_sc_hs__buf_16
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__buf_16
+SOURCE CELL NAME:         sky130_fd_sc_hs__buf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:         22        22         MN (4 pins)
+                    22        22         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        45        44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   44 layout mos transistors were reduced to 4.
+     40 mos transistors were deleted by parallel reduction.
+   44 source mos transistors were reduced to 4.
+     40 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/buf/sky130_fd_sc_hs__buf_16.pex.spice b/cells/buf/sky130_fd_sc_hs__buf_16.pex.spice
index 53d61e0..c99f577 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_16.pex.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_16.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_16.pex.spice
-* Created: Thu Aug 27 20:34:12 2020
+* Created: Tue Sep  1 19:56:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/buf/sky130_fd_sc_hs__buf_16.pxi.spice b/cells/buf/sky130_fd_sc_hs__buf_16.pxi.spice
index 9aa9ca1..1ecd16b 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_16.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_16.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_16.pxi.spice
-* Created: Thu Aug 27 20:34:12 2020
+* Created: Tue Sep  1 19:56:37 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUF_16%A_83_260# N_A_83_260#_M1002_d N_A_83_260#_M1011_d
 + N_A_83_260#_M1013_d N_A_83_260#_M1000_d N_A_83_260#_M1028_d

diff --git a/cells/buf/sky130_fd_sc_hs__buf_16.spice b/cells/buf/sky130_fd_sc_hs__buf_16.spice
index f25e98d..59fd31e 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_16.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_16.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_16.spice
-* Created: Thu Aug 27 20:34:12 2020
+* Created: Tue Sep  1 19:56:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/buf/sky130_fd_sc_hs__buf_2.lvs.report b/cells/buf/sky130_fd_sc_hs__buf_2.lvs.report
new file mode 100644
index 0000000..4040787
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hs__buf_2.lvs.report

@@ -0,0 +1,480 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__buf_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__buf_2.sp ('sky130_fd_sc_hs__buf_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_2.spice ('sky130_fd_sc_hs__buf_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:46 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__buf_2        sky130_fd_sc_hs__buf_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__buf_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__buf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/buf/sky130_fd_sc_hs__buf_2.pex.spice b/cells/buf/sky130_fd_sc_hs__buf_2.pex.spice
index 204a10a..c3001a9 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_2.pex.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_2.pex.spice
-* Created: Thu Aug 27 20:34:26 2020
+* Created: Tue Sep  1 19:56:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/buf/sky130_fd_sc_hs__buf_2.pxi.spice b/cells/buf/sky130_fd_sc_hs__buf_2.pxi.spice
index 89ceb94..6c82eab 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_2.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_2.pxi.spice
-* Created: Thu Aug 27 20:34:26 2020
+* Created: Tue Sep  1 19:56:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUF_2%A_21_260# N_A_21_260#_M1001_d N_A_21_260#_M1005_d
 + N_A_21_260#_c_53_n N_A_21_260#_M1002_g N_A_21_260#_M1000_g N_A_21_260#_M1004_g

diff --git a/cells/buf/sky130_fd_sc_hs__buf_2.spice b/cells/buf/sky130_fd_sc_hs__buf_2.spice
index ab3eefa..f036c05 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_2.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_2.spice
-* Created: Thu Aug 27 20:34:26 2020
+* Created: Tue Sep  1 19:56:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/buf/sky130_fd_sc_hs__buf_4.lvs.report b/cells/buf/sky130_fd_sc_hs__buf_4.lvs.report
new file mode 100644
index 0000000..f277a29
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hs__buf_4.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__buf_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__buf_4.sp ('sky130_fd_sc_hs__buf_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_4.spice ('sky130_fd_sc_hs__buf_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:51 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__buf_4        sky130_fd_sc_hs__buf_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__buf_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__buf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          5         5         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        12        11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/buf/sky130_fd_sc_hs__buf_4.pex.spice b/cells/buf/sky130_fd_sc_hs__buf_4.pex.spice
index 82d514f..dd777bc 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_4.pex.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_4.pex.spice
-* Created: Thu Aug 27 20:34:35 2020
+* Created: Tue Sep  1 19:56:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/buf/sky130_fd_sc_hs__buf_4.pxi.spice b/cells/buf/sky130_fd_sc_hs__buf_4.pxi.spice
index aae901b..57e5494 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_4.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_4.pxi.spice
-* Created: Thu Aug 27 20:34:35 2020
+* Created: Tue Sep  1 19:56:54 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUF_4%A_86_260# N_A_86_260#_M1004_d N_A_86_260#_M1003_d
 + N_A_86_260#_c_63_n N_A_86_260#_c_78_n N_A_86_260#_M1006_g N_A_86_260#_M1000_g

diff --git a/cells/buf/sky130_fd_sc_hs__buf_4.spice b/cells/buf/sky130_fd_sc_hs__buf_4.spice
index f514932..36bace0 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_4.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_4.spice
-* Created: Thu Aug 27 20:34:35 2020
+* Created: Tue Sep  1 19:56:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/buf/sky130_fd_sc_hs__buf_8.lvs.report b/cells/buf/sky130_fd_sc_hs__buf_8.lvs.report
new file mode 100644
index 0000000..346cffc
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_hs__buf_8.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__buf_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__buf_8.sp ('sky130_fd_sc_hs__buf_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/buf/sky130_fd_sc_hs__buf_8.spice ('sky130_fd_sc_hs__buf_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:56:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__buf_8        sky130_fd_sc_hs__buf_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__buf_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__buf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   22 layout mos transistors were reduced to 4.
+     18 mos transistors were deleted by parallel reduction.
+   22 source mos transistors were reduced to 4.
+     18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/buf/sky130_fd_sc_hs__buf_8.pex.spice b/cells/buf/sky130_fd_sc_hs__buf_8.pex.spice
index 8947179..ab878b2 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_8.pex.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_8.pex.spice
-* Created: Thu Aug 27 20:34:42 2020
+* Created: Tue Sep  1 19:57:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/buf/sky130_fd_sc_hs__buf_8.pxi.spice b/cells/buf/sky130_fd_sc_hs__buf_8.pxi.spice
index 32f068c..bf99cdc 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_8.pxi.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_8.pxi.spice
-* Created: Thu Aug 27 20:34:42 2020
+* Created: Tue Sep  1 19:57:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUF_8%A N_A_M1001_g N_A_c_108_n N_A_M1004_g N_A_c_109_n
 + N_A_M1005_g N_A_M1015_g N_A_M1019_g N_A_c_110_n N_A_M1007_g A A A N_A_c_106_n

diff --git a/cells/buf/sky130_fd_sc_hs__buf_8.spice b/cells/buf/sky130_fd_sc_hs__buf_8.spice
index 774959a..3caa231 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_8.spice
+++ b/cells/buf/sky130_fd_sc_hs__buf_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__buf_8.spice
-* Created: Thu Aug 27 20:34:42 2020
+* Created: Tue Sep  1 19:57:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.lvs.report b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.lvs.report
new file mode 100644
index 0000000..1f0e750
--- /dev/null
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.lvs.report

@@ -0,0 +1,526 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 99 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 101 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 103 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 105 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 107 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 109 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 111 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 113 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 115 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 117 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 119 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 121 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__bufbuf_16.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__bufbuf_16.sp ('sky130_fd_sc_hs__bufbuf_16')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice ('sky130_fd_sc_hs__bufbuf_16')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__bufbuf_16    sky130_fd_sc_hs__bufbuf_16
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__bufbuf_16
+SOURCE CELL NAME:         sky130_fd_sc_hs__bufbuf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:         26        26         MN (4 pins)
+                    26        26         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        53        52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   50 layout mos transistors were reduced to 6.
+     44 mos transistors were deleted by parallel reduction.
+   50 source mos transistors were reduced to 6.
+     44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pex.spice b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pex.spice
index 20f91de..8b052ba 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pex.spice
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufbuf_16.pex.spice
-* Created: Thu Aug 27 20:34:52 2020
+* Created: Tue Sep  1 19:57:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pxi.spice b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pxi.spice
index 97590fa..82fa3e1 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pxi.spice
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufbuf_16.pxi.spice
-* Created: Thu Aug 27 20:34:52 2020
+* Created: Tue Sep  1 19:57:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUFBUF_16%A N_A_c_235_n N_A_M1022_g N_A_M1050_g A
 + N_A_c_237_n PM_SKY130_FD_SC_HS__BUFBUF_16%A

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice
index a21d167..1e8d00f 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufbuf_16.spice
-* Created: Thu Aug 27 20:34:52 2020
+* Created: Tue Sep  1 19:57:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.lvs.report b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.lvs.report
new file mode 100644
index 0000000..1ed09c0
--- /dev/null
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.lvs.report

@@ -0,0 +1,500 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__bufbuf_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__bufbuf_8.sp ('sky130_fd_sc_hs__bufbuf_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice ('sky130_fd_sc_hs__bufbuf_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__bufbuf_8     sky130_fd_sc_hs__bufbuf_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__bufbuf_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__bufbuf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   22 layout mos transistors were reduced to 4.
+     18 mos transistors were deleted by parallel reduction.
+   22 source mos transistors were reduced to 4.
+     18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pex.spice b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pex.spice
index 72dad39..1b550ec 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pex.spice
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufbuf_8.pex.spice
-* Created: Thu Aug 27 20:35:00 2020
+* Created: Tue Sep  1 19:57:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pxi.spice b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pxi.spice
index 2cd95fc..b726251 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pxi.spice
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufbuf_8.pxi.spice
-* Created: Thu Aug 27 20:35:00 2020
+* Created: Tue Sep  1 19:57:12 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUFBUF_8%A N_A_M1020_g N_A_c_126_n N_A_M1021_g A
 + N_A_c_127_n PM_SKY130_FD_SC_HS__BUFBUF_8%A

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice
index fb22b96..acf538d 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufbuf_8.spice
-* Created: Thu Aug 27 20:35:00 2020
+* Created: Tue Sep  1 19:57:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.lvs.report b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.lvs.report
new file mode 100644
index 0000000..5721ce0
--- /dev/null
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.lvs.report

@@ -0,0 +1,524 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 99 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 101 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 103 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 105 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 107 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 109 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 111 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 113 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 115 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 117 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__bufinv_16.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__bufinv_16.sp ('sky130_fd_sc_hs__bufinv_16')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice ('sky130_fd_sc_hs__bufinv_16')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__bufinv_16    sky130_fd_sc_hs__bufinv_16
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__bufinv_16
+SOURCE CELL NAME:         sky130_fd_sc_hs__bufinv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:         25        25         MN (4 pins)
+                    25        25         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        51        50
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   50 layout mos transistors were reduced to 6.
+     44 mos transistors were deleted by parallel reduction.
+   50 source mos transistors were reduced to 6.
+     44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pex.spice b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pex.spice
index 03381d6..72cfef5 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pex.spice
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufinv_16.pex.spice
-* Created: Thu Aug 27 20:35:07 2020
+* Created: Tue Sep  1 19:57:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pxi.spice b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pxi.spice
index 66602ee..ce0c545 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pxi.spice
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufinv_16.pxi.spice
-* Created: Thu Aug 27 20:35:07 2020
+* Created: Tue Sep  1 19:57:18 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUFINV_16%A N_A_M1002_g N_A_c_218_n N_A_M1015_g
 + N_A_c_219_n N_A_M1017_g N_A_M1030_g N_A_c_220_n N_A_M1022_g N_A_M1043_g A A A

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice
index 341e5f8..e46cd55 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufinv_16.spice
-* Created: Thu Aug 27 20:35:07 2020
+* Created: Tue Sep  1 19:57:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.lvs.report b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.lvs.report
new file mode 100644
index 0000000..287bb91
--- /dev/null
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__bufinv_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__bufinv_8.sp ('sky130_fd_sc_hs__bufinv_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice ('sky130_fd_sc_hs__bufinv_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__bufinv_8     sky130_fd_sc_hs__bufinv_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__bufinv_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__bufinv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   22 layout mos transistors were reduced to 4.
+     18 mos transistors were deleted by parallel reduction.
+   22 source mos transistors were reduced to 4.
+     18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pex.spice b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pex.spice
index 28c7000..ebac19f 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pex.spice
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufinv_8.pex.spice
-* Created: Thu Aug 27 20:35:14 2020
+* Created: Tue Sep  1 19:57:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pxi.spice b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pxi.spice
index ff2c743..f33ec0b 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pxi.spice
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufinv_8.pxi.spice
-* Created: Thu Aug 27 20:35:14 2020
+* Created: Tue Sep  1 19:57:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__BUFINV_8%A N_A_c_106_n N_A_M1008_g N_A_M1023_g A
 + N_A_c_108_n PM_SKY130_FD_SC_HS__BUFINV_8%A

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice
index 4091326..2032c11 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__bufinv_8.spice
-* Created: Thu Aug 27 20:35:14 2020
+* Created: Tue Sep  1 19:57:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.lvs.report b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.lvs.report
new file mode 100644
index 0000000..c4aef5f
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.lvs.report

@@ -0,0 +1,473 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkbuf_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkbuf_1.sp ('sky130_fd_sc_hs__clkbuf_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice ('sky130_fd_sc_hs__clkbuf_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:33 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkbuf_1     sky130_fd_sc_hs__clkbuf_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkbuf_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkbuf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         5         4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pex.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pex.spice
index 010237d..3d0aa7c 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_1.pex.spice
-* Created: Thu Aug 27 20:35:29 2020
+* Created: Tue Sep  1 19:57:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pxi.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pxi.spice
index 850b142..f31859b 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_1.pxi.spice
-* Created: Thu Aug 27 20:35:29 2020
+* Created: Tue Sep  1 19:57:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKBUF_1%A N_A_M1002_g N_A_c_40_n N_A_M1003_g A A
 + N_A_c_39_n PM_SKY130_FD_SC_HS__CLKBUF_1%A

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice
index 57db3aa..4066c40 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_1.spice
-* Created: Thu Aug 27 20:35:29 2020
+* Created: Tue Sep  1 19:57:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.lvs.report b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.lvs.report
new file mode 100644
index 0000000..af44158
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.lvs.report

@@ -0,0 +1,514 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkbuf_16.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkbuf_16.sp ('sky130_fd_sc_hs__clkbuf_16')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice ('sky130_fd_sc_hs__clkbuf_16')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:27 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkbuf_16    sky130_fd_sc_hs__clkbuf_16
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkbuf_16
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkbuf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 4.
+     36 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 4.
+     36 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pex.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pex.spice
index 10f044e..c2aa2ca 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_16.pex.spice
-* Created: Thu Aug 27 20:35:22 2020
+* Created: Tue Sep  1 19:57:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pxi.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pxi.spice
index 2e16c42..b9bbcb7 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_16.pxi.spice
-* Created: Thu Aug 27 20:35:22 2020
+* Created: Tue Sep  1 19:57:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKBUF_16%A N_A_M1000_g N_A_c_202_n N_A_M1013_g
 + N_A_M1028_g N_A_c_203_n N_A_M1015_g N_A_M1034_g N_A_c_204_n N_A_M1017_g

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice
index d2c649e..e4bee58 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_16.spice
-* Created: Thu Aug 27 20:35:22 2020
+* Created: Tue Sep  1 19:57:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.lvs.report b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.lvs.report
new file mode 100644
index 0000000..9d8a015
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.lvs.report

@@ -0,0 +1,480 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkbuf_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkbuf_2.sp ('sky130_fd_sc_hs__clkbuf_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice ('sky130_fd_sc_hs__clkbuf_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkbuf_2     sky130_fd_sc_hs__clkbuf_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkbuf_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkbuf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pex.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pex.spice
index 9e12b1f..6fdf84f 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_2.pex.spice
-* Created: Thu Aug 27 20:35:37 2020
+* Created: Tue Sep  1 19:57:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pxi.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pxi.spice
index cc4ccc0..3d6e06f 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_2.pxi.spice
-* Created: Thu Aug 27 20:35:37 2020
+* Created: Tue Sep  1 19:57:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKBUF_2%A_43_192# N_A_43_192#_M1003_d N_A_43_192#_M1002_d
 + N_A_43_192#_M1004_g N_A_43_192#_c_50_n N_A_43_192#_M1000_g N_A_43_192#_M1005_g

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice
index 968ae1a..fcafb68 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_2.spice
-* Created: Thu Aug 27 20:35:37 2020
+* Created: Tue Sep  1 19:57:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.lvs.report b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.lvs.report
new file mode 100644
index 0000000..0d49018
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.lvs.report

@@ -0,0 +1,484 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkbuf_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkbuf_4.sp ('sky130_fd_sc_hs__clkbuf_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice ('sky130_fd_sc_hs__clkbuf_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkbuf_4     sky130_fd_sc_hs__clkbuf_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkbuf_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkbuf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pex.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pex.spice
index dd3794a..b413e31 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_4.pex.spice
-* Created: Thu Aug 27 20:35:44 2020
+* Created: Tue Sep  1 19:57:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pxi.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pxi.spice
index 1ac69f7..5067908 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_4.pxi.spice
-* Created: Thu Aug 27 20:35:44 2020
+* Created: Tue Sep  1 19:57:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKBUF_4%A_83_270# N_A_83_270#_M1001_d N_A_83_270#_M1006_d
 + N_A_83_270#_c_64_n N_A_83_270#_M1002_g N_A_83_270#_M1000_g N_A_83_270#_M1003_g

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice
index 48780b1..6aee1a9 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_4.spice
-* Created: Thu Aug 27 20:35:44 2020
+* Created: Tue Sep  1 19:57:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.lvs.report b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.lvs.report
new file mode 100644
index 0000000..369bdd0
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkbuf_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkbuf_8.sp ('sky130_fd_sc_hs__clkbuf_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice ('sky130_fd_sc_hs__clkbuf_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkbuf_8     sky130_fd_sc_hs__clkbuf_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkbuf_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkbuf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 4.
+     16 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 4.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pex.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pex.spice
index 6b7357a..6302c10 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_8.pex.spice
-* Created: Thu Aug 27 20:35:55 2020
+* Created: Tue Sep  1 19:57:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pxi.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pxi.spice
index d93ecdf..6d4523c 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_8.pxi.spice
-* Created: Thu Aug 27 20:35:55 2020
+* Created: Tue Sep  1 19:57:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKBUF_8%A N_A_c_116_n N_A_M1011_g N_A_M1007_g N_A_M1010_g
 + N_A_c_117_n N_A_M1016_g A A N_A_c_114_n N_A_c_115_n

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice
index a6b0462..d922a6d 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkbuf_8.spice
-* Created: Thu Aug 27 20:35:55 2020
+* Created: Tue Sep  1 19:57:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.lvs.report b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.lvs.report
new file mode 100644
index 0000000..cc84488
--- /dev/null
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.lvs.report

@@ -0,0 +1,475 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkdlyinv3sd1_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkdlyinv3sd1_1.sp ('sky130_fd_sc_hs__clkdlyinv3sd1_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice ('sky130_fd_sc_hs__clkdlyinv3sd1_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:57:56 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkdlyinv3sd1_1 sky130_fd_sc_hs__clkdlyinv3sd1_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkdlyinv3sd1_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkdlyinv3sd1_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pex.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pex.spice
index 6869d3f..2fdad5a 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pex.spice
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd1_1.pex.spice
-* Created: Thu Aug 27 20:36:02 2020
+* Created: Tue Sep  1 19:57:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pxi.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pxi.spice
index d5c5db8..158b908 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pxi.spice
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd1_1.pxi.spice
-* Created: Thu Aug 27 20:36:02 2020
+* Created: Tue Sep  1 19:57:59 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKDLYINV3SD1_1%A N_A_M1003_g N_A_c_51_n N_A_c_55_n
 + N_A_M1000_g A A N_A_c_53_n PM_SKY130_FD_SC_HS__CLKDLYINV3SD1_1%A

diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice
index 4341666..4576948 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd1_1.spice
-* Created: Thu Aug 27 20:36:02 2020
+* Created: Tue Sep  1 19:57:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.lvs.report b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.lvs.report
new file mode 100644
index 0000000..9b0cdfd
--- /dev/null
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.lvs.report

@@ -0,0 +1,475 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkdlyinv3sd2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkdlyinv3sd2_1.sp ('sky130_fd_sc_hs__clkdlyinv3sd2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice ('sky130_fd_sc_hs__clkdlyinv3sd2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:02 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkdlyinv3sd2_1 sky130_fd_sc_hs__clkdlyinv3sd2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkdlyinv3sd2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkdlyinv3sd2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pex.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pex.spice
index 22c587d..2d2e620 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pex.spice
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd2_1.pex.spice
-* Created: Thu Aug 27 20:36:09 2020
+* Created: Tue Sep  1 19:58:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pxi.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pxi.spice
index 738e665..5f531ac 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pxi.spice
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd2_1.pxi.spice
-* Created: Thu Aug 27 20:36:09 2020
+* Created: Tue Sep  1 19:58:05 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKDLYINV3SD2_1%A N_A_M1003_g N_A_c_51_n N_A_c_55_n
 + N_A_M1000_g A A N_A_c_53_n PM_SKY130_FD_SC_HS__CLKDLYINV3SD2_1%A

diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice
index 9241849..d5d7fd4 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd2_1.spice
-* Created: Thu Aug 27 20:36:09 2020
+* Created: Tue Sep  1 19:58:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.lvs.report b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.lvs.report
new file mode 100644
index 0000000..f7e19b1
--- /dev/null
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.lvs.report

@@ -0,0 +1,475 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkdlyinv3sd3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkdlyinv3sd3_1.sp ('sky130_fd_sc_hs__clkdlyinv3sd3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice ('sky130_fd_sc_hs__clkdlyinv3sd3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:08 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkdlyinv3sd3_1 sky130_fd_sc_hs__clkdlyinv3sd3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkdlyinv3sd3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkdlyinv3sd3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pex.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pex.spice
index 7836572..74a1c26 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pex.spice
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd3_1.pex.spice
-* Created: Thu Aug 27 20:36:17 2020
+* Created: Tue Sep  1 19:58:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pxi.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pxi.spice
index 39a73da..d081773 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pxi.spice
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd3_1.pxi.spice
-* Created: Thu Aug 27 20:36:17 2020
+* Created: Tue Sep  1 19:58:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKDLYINV3SD3_1%A N_A_M1004_g N_A_c_50_n N_A_c_54_n
 + N_A_M1000_g A A N_A_c_52_n PM_SKY130_FD_SC_HS__CLKDLYINV3SD3_1%A

diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice
index 1a1abdb..4dfc4ac 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv3sd3_1.spice
-* Created: Thu Aug 27 20:36:17 2020
+* Created: Tue Sep  1 19:58:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.lvs.report b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.lvs.report
new file mode 100644
index 0000000..e7f53d5
--- /dev/null
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkdlyinv5sd1_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkdlyinv5sd1_1.sp ('sky130_fd_sc_hs__clkdlyinv5sd1_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice ('sky130_fd_sc_hs__clkdlyinv5sd1_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:14 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkdlyinv5sd1_1 sky130_fd_sc_hs__clkdlyinv5sd1_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkdlyinv5sd1_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkdlyinv5sd1_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                ------    ------
+ Total Inst:        10        10
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         10         10            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pex.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pex.spice
index 12f6589..6f9008d 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pex.spice
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd1_1.pex.spice
-* Created: Thu Aug 27 20:36:24 2020
+* Created: Tue Sep  1 19:58:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pxi.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pxi.spice
index a345b94..8f9da8e 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pxi.spice
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd1_1.pxi.spice
-* Created: Thu Aug 27 20:36:24 2020
+* Created: Tue Sep  1 19:58:16 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKDLYINV5SD1_1%A N_A_M1008_g N_A_c_81_n N_A_c_85_n
 + N_A_M1001_g A A N_A_c_83_n PM_SKY130_FD_SC_HS__CLKDLYINV5SD1_1%A

diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice
index 3b9d8d3..f30e900 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd1_1.spice
-* Created: Thu Aug 27 20:36:24 2020
+* Created: Tue Sep  1 19:58:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.lvs.report b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.lvs.report
new file mode 100644
index 0000000..ee7ee5e
--- /dev/null
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkdlyinv5sd2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkdlyinv5sd2_1.sp ('sky130_fd_sc_hs__clkdlyinv5sd2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice ('sky130_fd_sc_hs__clkdlyinv5sd2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkdlyinv5sd2_1 sky130_fd_sc_hs__clkdlyinv5sd2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkdlyinv5sd2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkdlyinv5sd2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                ------    ------
+ Total Inst:        10        10
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         10         10            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pex.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pex.spice
index 60108b2..2a13b72 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pex.spice
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd2_1.pex.spice
-* Created: Thu Aug 27 20:36:31 2020
+* Created: Tue Sep  1 19:58:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pxi.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pxi.spice
index f27a6f8..dd9e8ce 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pxi.spice
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd2_1.pxi.spice
-* Created: Thu Aug 27 20:36:31 2020
+* Created: Tue Sep  1 19:58:22 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKDLYINV5SD2_1%A N_A_M1008_g N_A_c_78_n N_A_c_82_n
 + N_A_M1000_g A A N_A_c_80_n PM_SKY130_FD_SC_HS__CLKDLYINV5SD2_1%A

diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice
index 32e4165..8f7e022 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd2_1.spice
-* Created: Thu Aug 27 20:36:31 2020
+* Created: Tue Sep  1 19:58:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.lvs.report b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.lvs.report
new file mode 100644
index 0000000..99e1111
--- /dev/null
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkdlyinv5sd3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkdlyinv5sd3_1.sp ('sky130_fd_sc_hs__clkdlyinv5sd3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice ('sky130_fd_sc_hs__clkdlyinv5sd3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkdlyinv5sd3_1 sky130_fd_sc_hs__clkdlyinv5sd3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkdlyinv5sd3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkdlyinv5sd3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                ------    ------
+ Total Inst:        10        10
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         10         10            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pex.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pex.spice
index 2068c36..33c27cf 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pex.spice
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd3_1.pex.spice
-* Created: Thu Aug 27 20:36:40 2020
+* Created: Tue Sep  1 19:58:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pxi.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pxi.spice
index 2e969dd..43cd19a 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pxi.spice
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd3_1.pxi.spice
-* Created: Thu Aug 27 20:36:40 2020
+* Created: Tue Sep  1 19:58:28 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKDLYINV5SD3_1%A N_A_M1009_g N_A_c_77_n N_A_c_81_n
 + N_A_M1001_g A A N_A_c_79_n PM_SKY130_FD_SC_HS__CLKDLYINV5SD3_1%A

diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice
index b183fe9..0ec913a 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkdlyinv5sd3_1.spice
-* Created: Thu Aug 27 20:36:40 2020
+* Created: Tue Sep  1 19:58:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.lvs.report b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.lvs.report
new file mode 100644
index 0000000..8489248
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkinv_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkinv_1.sp ('sky130_fd_sc_hs__clkinv_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice ('sky130_fd_sc_hs__clkinv_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:37 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkinv_1     sky130_fd_sc_hs__clkinv_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkinv_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkinv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         4         3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   2 layout mos transistors were reduced to 1.
+     1 mos transistor was deleted by parallel reduction.
+   2 source mos transistors were reduced to 1.
+     1 mos transistor was deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pex.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pex.spice
index 332d0a3..329bf25 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_1.pex.spice
-* Created: Thu Aug 27 20:36:57 2020
+* Created: Tue Sep  1 19:58:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pxi.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pxi.spice
index b6b3498..4be9cf1 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_1.pxi.spice
-* Created: Thu Aug 27 20:36:57 2020
+* Created: Tue Sep  1 19:58:40 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKINV_1%A N_A_c_31_n N_A_M1000_g N_A_M1002_g N_A_c_32_n
 + N_A_M1001_g A A N_A_c_28_n N_A_c_29_n N_A_c_30_n

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice
index a0fbb98..45234df 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_1.spice
-* Created: Thu Aug 27 20:36:57 2020
+* Created: Tue Sep  1 19:58:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.lvs.report b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.lvs.report
new file mode 100644
index 0000000..a51817f
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.lvs.report

@@ -0,0 +1,514 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkinv_16.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkinv_16.sp ('sky130_fd_sc_hs__clkinv_16')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice ('sky130_fd_sc_hs__clkinv_16')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:31 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkinv_16    sky130_fd_sc_hs__clkinv_16
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkinv_16
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkinv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:         16        16         MN (4 pins)
+                    24        24         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 2.
+     38 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 2.
+     38 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pex.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pex.spice
index b6ca4f4..fea4a09 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_16.pex.spice
-* Created: Thu Aug 27 20:36:47 2020
+* Created: Tue Sep  1 19:58:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pxi.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pxi.spice
index 0ceb327..83283fb 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_16.pxi.spice
-* Created: Thu Aug 27 20:36:47 2020
+* Created: Tue Sep  1 19:58:34 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKINV_16%A N_A_M1000_g N_A_c_182_n N_A_M1002_g
 + N_A_M1001_g N_A_c_183_n N_A_M1003_g N_A_M1005_g N_A_c_184_n N_A_M1004_g

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice
index 1dafed1..015a75e 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_16.spice
-* Created: Thu Aug 27 20:36:47 2020
+* Created: Tue Sep  1 19:58:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.lvs.report b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.lvs.report
new file mode 100644
index 0000000..6220236
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkinv_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkinv_2.sp ('sky130_fd_sc_hs__clkinv_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice ('sky130_fd_sc_hs__clkinv_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkinv_2     sky130_fd_sc_hs__clkinv_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkinv_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkinv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          2         2         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         6         5
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   5 layout mos transistors were reduced to 2.
+     3 mos transistors were deleted by parallel reduction.
+   5 source mos transistors were reduced to 2.
+     3 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pex.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pex.spice
index 356330b..24dc99a 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_2.pex.spice
-* Created: Thu Aug 27 20:37:05 2020
+* Created: Tue Sep  1 19:58:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pxi.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pxi.spice
index 1c34b50..bf5b2d9 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_2.pxi.spice
-* Created: Thu Aug 27 20:37:05 2020
+* Created: Tue Sep  1 19:58:46 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKINV_2%A N_A_M1000_g N_A_c_35_n N_A_M1002_g N_A_c_36_n
 + N_A_M1003_g N_A_c_37_n N_A_M1004_g N_A_M1001_g A A A N_A_c_34_n

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice
index 30ccd62..3ca298f 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_2.spice
-* Created: Thu Aug 27 20:37:05 2020
+* Created: Tue Sep  1 19:58:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.lvs.report b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.lvs.report
new file mode 100644
index 0000000..fe82fb5
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.lvs.report

@@ -0,0 +1,484 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkinv_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkinv_4.sp ('sky130_fd_sc_hs__clkinv_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice ('sky130_fd_sc_hs__clkinv_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkinv_4     sky130_fd_sc_hs__clkinv_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkinv_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkinv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 2.
+     8 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 2.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pex.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pex.spice
index 47a643e..1a06a7e 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_4.pex.spice
-* Created: Thu Aug 27 20:37:12 2020
+* Created: Tue Sep  1 19:58:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pxi.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pxi.spice
index 373c997..93ee01e 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_4.pxi.spice
-* Created: Thu Aug 27 20:37:12 2020
+* Created: Tue Sep  1 19:58:52 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKINV_4%A N_A_c_63_n N_A_M1003_g N_A_c_55_n N_A_M1000_g
 + N_A_c_65_n N_A_M1004_g N_A_c_66_n N_A_M1005_g N_A_M1001_g N_A_c_67_n

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice
index 55f9688..4b9cd39 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_4.spice
-* Created: Thu Aug 27 20:37:12 2020
+* Created: Tue Sep  1 19:58:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.lvs.report b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.lvs.report
new file mode 100644
index 0000000..a01ec32
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__clkinv_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__clkinv_8.sp ('sky130_fd_sc_hs__clkinv_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice ('sky130_fd_sc_hs__clkinv_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:58:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__clkinv_8     sky130_fd_sc_hs__clkinv_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__clkinv_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__clkinv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          8         8         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 2.
+     18 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 2.
+     18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pex.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pex.spice
index 08c53ae..1964461 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_8.pex.spice
-* Created: Thu Aug 27 20:37:19 2020
+* Created: Tue Sep  1 19:58:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pxi.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pxi.spice
index d2ef660..0585a52 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_8.pxi.spice
-* Created: Thu Aug 27 20:37:19 2020
+* Created: Tue Sep  1 19:58:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__CLKINV_8%A N_A_M1000_g N_A_c_92_n N_A_M1002_g N_A_c_93_n
 + N_A_M1003_g N_A_c_94_n N_A_M1007_g N_A_c_95_n N_A_M1008_g N_A_c_96_n

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice
index c06d67b..beaa2f0 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__clkinv_8.spice
-* Created: Thu Aug 27 20:37:19 2020
+* Created: Tue Sep  1 19:58:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/conb/sky130_fd_sc_hs__conb_1.lvs.report b/cells/conb/sky130_fd_sc_hs__conb_1.lvs.report
new file mode 100644
index 0000000..ebc3986
--- /dev/null
+++ b/cells/conb/sky130_fd_sc_hs__conb_1.lvs.report

@@ -0,0 +1,478 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/conb/sky130_fd_sc_hs__conb_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/conb/sky130_fd_sc_hs__conb_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 20 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/conb/sky130_fd_sc_hs__conb_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__conb_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__conb_1.sp ('sky130_fd_sc_hs__conb_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/conb/sky130_fd_sc_hs__conb_1.spice ('sky130_fd_sc_hs__conb_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__conb_1       sky130_fd_sc_hs__conb_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__conb_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__conb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          2         2         R (2 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         3         2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          2         2         R (2 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           2          2            0            0    R(SHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   2 passthrough layout nets were found.
+   2 passthrough source nets were found.
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+      (Layout nets which are connected only to ports).
+
+   VPB (port: VPB), VNB (port: VNB),
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB HI VPWR VGND LO
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/conb/sky130_fd_sc_hs__conb_1.pex.spice b/cells/conb/sky130_fd_sc_hs__conb_1.pex.spice
index 17ef894..aa04708 100644
--- a/cells/conb/sky130_fd_sc_hs__conb_1.pex.spice
+++ b/cells/conb/sky130_fd_sc_hs__conb_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__conb_1.pex.spice
-* Created: Thu Aug 27 20:37:26 2020
+* Created: Tue Sep  1 19:59:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/conb/sky130_fd_sc_hs__conb_1.pxi.spice b/cells/conb/sky130_fd_sc_hs__conb_1.pxi.spice
index 0c854e5..5724600 100644
--- a/cells/conb/sky130_fd_sc_hs__conb_1.pxi.spice
+++ b/cells/conb/sky130_fd_sc_hs__conb_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__conb_1.pxi.spice
-* Created: Thu Aug 27 20:37:26 2020
+* Created: Tue Sep  1 19:59:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__CONB_1%HI HI HI HI HI HI N_HI_R0_pos N_HI_c_24_n
 + N_HI_c_25_n HI PM_SKY130_FD_SC_HS__CONB_1%HI

diff --git a/cells/conb/sky130_fd_sc_hs__conb_1.spice b/cells/conb/sky130_fd_sc_hs__conb_1.spice
index 1e4f61b..9cbcd47 100644
--- a/cells/conb/sky130_fd_sc_hs__conb_1.spice
+++ b/cells/conb/sky130_fd_sc_hs__conb_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__conb_1.spice
-* Created: Thu Aug 27 20:37:26 2020
+* Created: Tue Sep  1 19:59:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/decap/sky130_fd_sc_hs__decap_4.lvs.report b/cells/decap/sky130_fd_sc_hs__decap_4.lvs.report
new file mode 100644
index 0000000..392a0a7
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_hs__decap_4.lvs.report

@@ -0,0 +1,471 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__decap_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__decap_4.sp ('sky130_fd_sc_hs__decap_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_4.spice ('sky130_fd_sc_hs__decap_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__decap_4      sky130_fd_sc_hs__decap_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__decap_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__decap_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              4         4
+
+ Nets:               4         4
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         3         2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              4         4
+
+ Nets:               4         4
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               4          4            0            0
+
+   Nets:                4          4            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/decap/sky130_fd_sc_hs__decap_4.pex.spice b/cells/decap/sky130_fd_sc_hs__decap_4.pex.spice
index d37c9d7..d02d2b8 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_4.pex.spice
+++ b/cells/decap/sky130_fd_sc_hs__decap_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__decap_4.pex.spice
-* Created: Thu Aug 27 20:37:33 2020
+* Created: Tue Sep  1 19:59:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/decap/sky130_fd_sc_hs__decap_4.pxi.spice b/cells/decap/sky130_fd_sc_hs__decap_4.pxi.spice
index 09fd3f1..23bb33b 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_4.pxi.spice
+++ b/cells/decap/sky130_fd_sc_hs__decap_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__decap_4.pxi.spice
-* Created: Thu Aug 27 20:37:33 2020
+* Created: Tue Sep  1 19:59:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__DECAP_4%VGND N_VGND_M1001_s N_VGND_M1000_g N_VGND_c_20_n
 + N_VGND_c_21_n N_VGND_c_22_n N_VGND_c_23_n N_VGND_c_24_n VGND N_VGND_c_25_n

diff --git a/cells/decap/sky130_fd_sc_hs__decap_4.spice b/cells/decap/sky130_fd_sc_hs__decap_4.spice
index 1c511d3..809038a 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_4.spice
+++ b/cells/decap/sky130_fd_sc_hs__decap_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__decap_4.spice
-* Created: Thu Aug 27 20:37:33 2020
+* Created: Tue Sep  1 19:59:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/decap/sky130_fd_sc_hs__decap_8.lvs.report b/cells/decap/sky130_fd_sc_hs__decap_8.lvs.report
new file mode 100644
index 0000000..01201ad
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_hs__decap_8.lvs.report

@@ -0,0 +1,478 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_8.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__decap_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__decap_8.sp ('sky130_fd_sc_hs__decap_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/decap/sky130_fd_sc_hs__decap_8.spice ('sky130_fd_sc_hs__decap_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__decap_8      sky130_fd_sc_hs__decap_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__decap_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__decap_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              4         4
+
+ Nets:               4         4
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         5         4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              4         4
+
+ Nets:               4         4
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               4          4            0            0
+
+   Nets:                4          4            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/decap/sky130_fd_sc_hs__decap_8.pex.spice b/cells/decap/sky130_fd_sc_hs__decap_8.pex.spice
index 869b34f..a3afc62 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_8.pex.spice
+++ b/cells/decap/sky130_fd_sc_hs__decap_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__decap_8.pex.spice
-* Created: Thu Aug 27 20:37:42 2020
+* Created: Tue Sep  1 19:59:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/decap/sky130_fd_sc_hs__decap_8.pxi.spice b/cells/decap/sky130_fd_sc_hs__decap_8.pxi.spice
index 223d5f9..c5a68f7 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_8.pxi.spice
+++ b/cells/decap/sky130_fd_sc_hs__decap_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__decap_8.pxi.spice
-* Created: Thu Aug 27 20:37:42 2020
+* Created: Tue Sep  1 19:59:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__DECAP_8%VGND N_VGND_M1001_s N_VGND_M1000_g N_VGND_M1002_g
 + N_VGND_c_30_n N_VGND_c_31_n N_VGND_c_32_n N_VGND_c_33_n N_VGND_c_34_n

diff --git a/cells/decap/sky130_fd_sc_hs__decap_8.spice b/cells/decap/sky130_fd_sc_hs__decap_8.spice
index ca5cea2..05d6a50 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_8.spice
+++ b/cells/decap/sky130_fd_sc_hs__decap_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__decap_8.spice
-* Created: Thu Aug 27 20:37:42 2020
+* Created: Tue Sep  1 19:59:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.lvs.report b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.lvs.report
new file mode 100644
index 0000000..ead0dfe
--- /dev/null
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.lvs.report

@@ -0,0 +1,515 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfbbn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfbbn_1.sp ('sky130_fd_sc_hs__dfbbn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice ('sky130_fd_sc_hs__dfbbn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfbbn_1      sky130_fd_sc_hs__dfbbn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfbbn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfbbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              29        29
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     5         5         SMP2 (4 pins)
+                     2         2         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        5          5            0            0    SMP2
+                        2          2            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pex.spice b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pex.spice
index 64698cb..f1b620b 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pex.spice
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbn_1.pex.spice
-* Created: Thu Aug 27 20:37:49 2020
+* Created: Tue Sep  1 19:59:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pxi.spice b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pxi.spice
index b46a46a..ccab346 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pxi.spice
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbn_1.pxi.spice
-* Created: Thu Aug 27 20:37:49 2020
+* Created: Tue Sep  1 19:59:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFBBN_1%CLK_N N_CLK_N_M1035_g N_CLK_N_c_276_n
 + N_CLK_N_M1002_g CLK_N N_CLK_N_c_277_n PM_SKY130_FD_SC_HS__DFBBN_1%CLK_N

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice
index 416b2bf..7e633b0 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbn_1.spice
-* Created: Thu Aug 27 20:37:49 2020
+* Created: Tue Sep  1 19:59:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.lvs.report b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.lvs.report
new file mode 100644
index 0000000..2031d94
--- /dev/null
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.lvs.report

@@ -0,0 +1,524 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 99 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 101 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 103 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 105 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfbbn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfbbn_2.sp ('sky130_fd_sc_hs__dfbbn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice ('sky130_fd_sc_hs__dfbbn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfbbn_2      sky130_fd_sc_hs__dfbbn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfbbn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfbbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              29        29
+
+ Instances:         22        22         MN (4 pins)
+                    22        22         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        45        44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     5         5         SMP2 (4 pins)
+                     2         2         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        5          5            0            0    SMP2
+                        2          2            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pex.spice b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pex.spice
index 7990fc8..c2db094 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pex.spice
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbn_2.pex.spice
-* Created: Thu Aug 27 20:38:00 2020
+* Created: Tue Sep  1 19:59:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pxi.spice b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pxi.spice
index 2b404e5..385d3ad 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pxi.spice
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbn_2.pxi.spice
-* Created: Thu Aug 27 20:38:00 2020
+* Created: Tue Sep  1 19:59:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFBBN_2%CLK_N N_CLK_N_M1034_g N_CLK_N_c_293_n
 + N_CLK_N_M1000_g CLK_N N_CLK_N_c_294_n PM_SKY130_FD_SC_HS__DFBBN_2%CLK_N

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice
index a75d527..d2cd7fb 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbn_2.spice
-* Created: Thu Aug 27 20:38:00 2020
+* Created: Tue Sep  1 19:59:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.lvs.report b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.lvs.report
new file mode 100644
index 0000000..e0e9016
--- /dev/null
+++ b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.lvs.report

@@ -0,0 +1,515 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfbbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfbbp_1.sp ('sky130_fd_sc_hs__dfbbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice ('sky130_fd_sc_hs__dfbbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfbbp_1      sky130_fd_sc_hs__dfbbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfbbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfbbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              29        29
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     5         5         SMP2 (4 pins)
+                     2         2         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        5          5            0            0    SMP2
+                        2          2            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pex.spice b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pex.spice
index 879b963..dc57f54 100644
--- a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pex.spice
+++ b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbp_1.pex.spice
-* Created: Thu Aug 27 20:38:07 2020
+* Created: Tue Sep  1 19:59:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pxi.spice b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pxi.spice
index e0c462c..db31261 100644
--- a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pxi.spice
+++ b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbp_1.pxi.spice
-* Created: Thu Aug 27 20:38:07 2020
+* Created: Tue Sep  1 19:59:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFBBP_1%CLK N_CLK_c_267_n N_CLK_M1028_g N_CLK_c_268_n
 + N_CLK_M1022_g CLK PM_SKY130_FD_SC_HS__DFBBP_1%CLK

diff --git a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice
index f5af583..2bc1bf9 100644
--- a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice
+++ b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfbbp_1.spice
-* Created: Thu Aug 27 20:38:07 2020
+* Created: Tue Sep  1 19:59:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.lvs.report b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.lvs.report
new file mode 100644
index 0000000..a043bb1
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.lvs.report

@@ -0,0 +1,509 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfrbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfrbp_1.sp ('sky130_fd_sc_hs__dfrbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice ('sky130_fd_sc_hs__dfrbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:37 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfrbp_1      sky130_fd_sc_hs__dfrbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfrbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              24        24
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                    13        13         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        27        27
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       13         13            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         27         27            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pex.spice b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pex.spice
index aeb5931..ff9d149 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrbp_1.pex.spice
-* Created: Thu Aug 27 20:38:15 2020
+* Created: Tue Sep  1 19:59:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pxi.spice b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pxi.spice
index 294bd09..14259cc 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrbp_1.pxi.spice
-* Created: Thu Aug 27 20:38:15 2020
+* Created: Tue Sep  1 19:59:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFRBP_1%D N_D_c_241_n N_D_M1000_g N_D_M1011_g N_D_c_242_n
 + D D D N_D_c_238_n N_D_c_239_n N_D_c_240_n PM_SKY130_FD_SC_HS__DFRBP_1%D

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice
index 969e9c0..8a5dd1a 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrbp_1.spice
-* Created: Thu Aug 27 20:38:15 2020
+* Created: Tue Sep  1 19:59:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.lvs.report b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.lvs.report
new file mode 100644
index 0000000..97601cf
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.lvs.report

@@ -0,0 +1,518 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfrbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfrbp_2.sp ('sky130_fd_sc_hs__dfrbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice ('sky130_fd_sc_hs__dfrbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfrbp_2      sky130_fd_sc_hs__dfrbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfrbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              24        24
+
+ Instances:         19        19         MN (4 pins)
+                    19        19         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                    13        13         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        27        27
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       13         13            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         27         27            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pex.spice b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pex.spice
index 12ed58c..8b50cca 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrbp_2.pex.spice
-* Created: Thu Aug 27 20:38:22 2020
+* Created: Tue Sep  1 19:59:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pxi.spice b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pxi.spice
index 3bd6e3f..86662e9 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrbp_2.pxi.spice
-* Created: Thu Aug 27 20:38:22 2020
+* Created: Tue Sep  1 19:59:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFRBP_2%D N_D_c_267_n N_D_c_274_n N_D_M1006_g N_D_M1014_g
 + N_D_c_268_n N_D_c_269_n N_D_c_270_n D D N_D_c_272_n

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice
index 4701baf..99af50a 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrbp_2.spice
-* Created: Thu Aug 27 20:38:22 2020
+* Created: Tue Sep  1 19:59:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.lvs.report b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.lvs.report
new file mode 100644
index 0000000..c38e18d
--- /dev/null
+++ b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.lvs.report

@@ -0,0 +1,507 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfrtn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfrtn_1.sp ('sky130_fd_sc_hs__dfrtn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice ('sky130_fd_sc_hs__dfrtn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfrtn_1      sky130_fd_sc_hs__dfrtn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfrtn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              23        23
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    12        12         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        25        25
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         25         25            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D RESET_B CLK_N VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pex.spice b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pex.spice
index 47fce53..b69be08 100644
--- a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pex.spice
+++ b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtn_1.pex.spice
-* Created: Thu Aug 27 20:38:30 2020
+* Created: Tue Sep  1 19:59:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pxi.spice b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pxi.spice
index 15b660d..46b1ece 100644
--- a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pxi.spice
+++ b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtn_1.pxi.spice
-* Created: Thu Aug 27 20:38:30 2020
+* Created: Tue Sep  1 19:59:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFRTN_1%D N_D_c_240_n N_D_c_247_n N_D_c_248_n N_D_c_249_n
 + N_D_M1008_g N_D_M1029_g N_D_c_242_n N_D_c_243_n D D D N_D_c_244_n N_D_c_245_n

diff --git a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice
index 5580282..5d82ca3 100644
--- a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice
+++ b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtn_1.spice
-* Created: Thu Aug 27 20:38:30 2020
+* Created: Tue Sep  1 19:59:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.lvs.report b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.lvs.report
new file mode 100644
index 0000000..1a91f27
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.lvs.report

@@ -0,0 +1,507 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfrtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfrtp_1.sp ('sky130_fd_sc_hs__dfrtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice ('sky130_fd_sc_hs__dfrtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 19:59:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfrtp_1      sky130_fd_sc_hs__dfrtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfrtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              23        23
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    12        12         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        25        25
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         25         25            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pex.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pex.spice
index 864f91a..db1f4fa 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_1.pex.spice
-* Created: Thu Aug 27 20:38:37 2020
+* Created: Tue Sep  1 19:59:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pxi.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pxi.spice
index bb4ab6a..7304997 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_1.pxi.spice
-* Created: Thu Aug 27 20:38:37 2020
+* Created: Tue Sep  1 19:59:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFRTP_1%D N_D_c_236_n N_D_c_241_n N_D_c_242_n N_D_M1013_g
 + N_D_M1025_g D D D N_D_c_238_n N_D_c_239_n N_D_c_244_n

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice
index ff75c17..295b5b1 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_1.spice
-* Created: Thu Aug 27 20:38:37 2020
+* Created: Tue Sep  1 19:59:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.lvs.report b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.lvs.report
new file mode 100644
index 0000000..008225b
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.lvs.report

@@ -0,0 +1,514 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfrtp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfrtp_2.sp ('sky130_fd_sc_hs__dfrtp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice ('sky130_fd_sc_hs__dfrtp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfrtp_2      sky130_fd_sc_hs__dfrtp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfrtp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              23        23
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    12        12         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        25        25
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         25         25            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pex.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pex.spice
index c0d86a8..77ff5a4 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_2.pex.spice
-* Created: Thu Aug 27 20:38:45 2020
+* Created: Tue Sep  1 20:00:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pxi.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pxi.spice
index 7f6c7c9..9c04df5 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_2.pxi.spice
-* Created: Thu Aug 27 20:38:45 2020
+* Created: Tue Sep  1 20:00:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFRTP_2%D N_D_c_243_n N_D_c_248_n N_D_c_249_n N_D_M1016_g
 + N_D_M1030_g D D D N_D_c_245_n N_D_c_246_n N_D_c_251_n

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice
index da096d5..e1dceb0 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_2.spice
-* Created: Thu Aug 27 20:38:45 2020
+* Created: Tue Sep  1 20:00:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.lvs.report b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.lvs.report
new file mode 100644
index 0000000..c03ecf7
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.lvs.report

@@ -0,0 +1,519 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfrtp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfrtp_4.sp ('sky130_fd_sc_hs__dfrtp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice ('sky130_fd_sc_hs__dfrtp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfrtp_4      sky130_fd_sc_hs__dfrtp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfrtp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              23        23
+
+ Instances:         19        19         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        40        39
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    12        12         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        25        25
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         25         25            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pex.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pex.spice
index 8c25e04..8836ed6 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_4.pex.spice
-* Created: Thu Aug 27 20:38:53 2020
+* Created: Tue Sep  1 20:00:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pxi.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pxi.spice
index 5ead0d5..f05a4fb 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_4.pxi.spice
-* Created: Thu Aug 27 20:38:53 2020
+* Created: Tue Sep  1 20:00:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFRTP_4%D N_D_c_280_n N_D_c_285_n N_D_c_286_n N_D_M1016_g
 + N_D_M1021_g D D D N_D_c_282_n N_D_c_283_n N_D_c_288_n

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice
index f3096f6..59a6fc8 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfrtp_4.spice
-* Created: Thu Aug 27 20:38:53 2020
+* Created: Tue Sep  1 20:00:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.lvs.report b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.lvs.report
new file mode 100644
index 0000000..570f6ae
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.lvs.report

@@ -0,0 +1,509 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfsbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfsbp_1.sp ('sky130_fd_sc_hs__dfsbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice ('sky130_fd_sc_hs__dfsbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfsbp_1      sky130_fd_sc_hs__dfsbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfsbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              25        25
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                    11        11         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        26        26
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         26         26            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pex.spice b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pex.spice
index def3681..a93c32b 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfsbp_1.pex.spice
-* Created: Thu Aug 27 20:39:03 2020
+* Created: Tue Sep  1 20:00:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pxi.spice b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pxi.spice
index 51bad90..4cc7ba5 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfsbp_1.pxi.spice
-* Created: Thu Aug 27 20:39:03 2020
+* Created: Tue Sep  1 20:00:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFSBP_1%D N_D_c_270_n N_D_c_275_n N_D_M1007_g N_D_c_276_n
 + N_D_M1000_g D D N_D_c_272_n N_D_c_273_n N_D_c_278_n

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice
index 06878a0..31cc180 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfsbp_1.spice
-* Created: Thu Aug 27 20:39:03 2020
+* Created: Tue Sep  1 20:00:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.lvs.report b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.lvs.report
new file mode 100644
index 0000000..ac49b9b
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.lvs.report

@@ -0,0 +1,518 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfsbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfsbp_2.sp ('sky130_fd_sc_hs__dfsbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice ('sky130_fd_sc_hs__dfsbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfsbp_2      sky130_fd_sc_hs__dfsbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfsbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfsbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              25        25
+
+ Instances:         19        19         MN (4 pins)
+                    19        19         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                    11        11         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        26        26
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         26         26            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pex.spice b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pex.spice
index c442509..216dd3b 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfsbp_2.pex.spice
-* Created: Thu Aug 27 20:39:11 2020
+* Created: Tue Sep  1 20:00:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pxi.spice b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pxi.spice
index 31b5ff4..6ec38bc 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfsbp_2.pxi.spice
-* Created: Thu Aug 27 20:39:11 2020
+* Created: Tue Sep  1 20:00:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFSBP_2%D N_D_c_278_n N_D_c_283_n N_D_M1031_g N_D_c_284_n
 + N_D_M1000_g D D N_D_c_280_n N_D_c_281_n N_D_c_286_n

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice
index 54e0f68..8d134e4 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfsbp_2.spice
-* Created: Thu Aug 27 20:39:11 2020
+* Created: Tue Sep  1 20:00:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.lvs.report b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.lvs.report
new file mode 100644
index 0000000..475729a
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.lvs.report

@@ -0,0 +1,507 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfstp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfstp_1.sp ('sky130_fd_sc_hs__dfstp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice ('sky130_fd_sc_hs__dfstp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfstp_1      sky130_fd_sc_hs__dfstp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfstp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              24        24
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pex.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pex.spice
index 04fd7bd..a911312 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_1.pex.spice
-* Created: Thu Aug 27 20:39:18 2020
+* Created: Tue Sep  1 20:00:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pxi.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pxi.spice
index 16a4494..0720bcb 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_1.pxi.spice
-* Created: Thu Aug 27 20:39:18 2020
+* Created: Tue Sep  1 20:00:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFSTP_1%D N_D_c_240_n N_D_c_245_n N_D_M1029_g N_D_c_246_n
 + N_D_M1012_g D D N_D_c_242_n N_D_c_243_n N_D_c_248_n

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice
index 5605238..a197502 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_1.spice
-* Created: Thu Aug 27 20:39:18 2020
+* Created: Tue Sep  1 20:00:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.lvs.report b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.lvs.report
new file mode 100644
index 0000000..a9a5ae3
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.lvs.report

@@ -0,0 +1,514 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfstp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfstp_2.sp ('sky130_fd_sc_hs__dfstp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice ('sky130_fd_sc_hs__dfstp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfstp_2      sky130_fd_sc_hs__dfstp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfstp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfstp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              24        24
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pex.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pex.spice
index cb069d7..96134e0 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_2.pex.spice
-* Created: Thu Aug 27 20:39:26 2020
+* Created: Tue Sep  1 20:00:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pxi.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pxi.spice
index 69b327b..6ed11f9 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_2.pxi.spice
-* Created: Thu Aug 27 20:39:26 2020
+* Created: Tue Sep  1 20:00:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFSTP_2%D N_D_c_245_n N_D_c_250_n N_D_M1030_g N_D_c_251_n
 + N_D_M1000_g D D N_D_c_247_n N_D_c_248_n N_D_c_253_n

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice
index be2ad16..9e5699e 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_2.spice
-* Created: Thu Aug 27 20:39:26 2020
+* Created: Tue Sep  1 20:00:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.lvs.report b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.lvs.report
new file mode 100644
index 0000000..57a0509
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.lvs.report

@@ -0,0 +1,519 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfstp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfstp_4.sp ('sky130_fd_sc_hs__dfstp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice ('sky130_fd_sc_hs__dfstp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfstp_4      sky130_fd_sc_hs__dfstp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfstp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfstp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              24        24
+
+ Instances:         19        19         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        40        39
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        1          1            0            0    SMN3
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pex.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pex.spice
index ca48f66..dd70318 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_4.pex.spice
-* Created: Thu Aug 27 20:39:33 2020
+* Created: Tue Sep  1 20:00:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pxi.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pxi.spice
index a2a7337..a819087 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_4.pxi.spice
-* Created: Thu Aug 27 20:39:33 2020
+* Created: Tue Sep  1 20:00:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFSTP_4%D N_D_c_270_n N_D_c_275_n N_D_M1033_g N_D_c_276_n
 + N_D_M1009_g D D N_D_c_272_n N_D_c_273_n N_D_c_278_n

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice
index 6214556..3c43219 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfstp_4.spice
-* Created: Thu Aug 27 20:39:33 2020
+* Created: Tue Sep  1 20:00:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.lvs.report b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.lvs.report
new file mode 100644
index 0000000..c34b613
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.lvs.report

@@ -0,0 +1,501 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfxbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfxbp_1.sp ('sky130_fd_sc_hs__dfxbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice ('sky130_fd_sc_hs__dfxbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfxbp_1      sky130_fd_sc_hs__dfxbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfxbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              20        20
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:          10         10            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK D VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pex.spice b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pex.spice
index ea70a38..a75f231 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxbp_1.pex.spice
-* Created: Thu Aug 27 20:39:41 2020
+* Created: Tue Sep  1 20:00:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pxi.spice b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pxi.spice
index f11d533..0633958 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxbp_1.pxi.spice
-* Created: Thu Aug 27 20:39:41 2020
+* Created: Tue Sep  1 20:00:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFXBP_1%CLK N_CLK_c_204_n N_CLK_M1024_g N_CLK_c_205_n
 + N_CLK_M1021_g CLK N_CLK_c_206_n PM_SKY130_FD_SC_HS__DFXBP_1%CLK

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice
index b486f31..e6f86c8 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxbp_1.spice
-* Created: Thu Aug 27 20:39:41 2020
+* Created: Tue Sep  1 20:00:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.lvs.report b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.lvs.report
new file mode 100644
index 0000000..a270e0f
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.lvs.report

@@ -0,0 +1,511 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfxbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfxbp_2.sp ('sky130_fd_sc_hs__dfxbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice ('sky130_fd_sc_hs__dfxbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfxbp_2      sky130_fd_sc_hs__dfxbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfxbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              20        20
+
+ Instances:         16        16         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        34        33
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:          10         10            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK D VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pex.spice b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pex.spice
index 615a2c1..8a44099 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxbp_2.pex.spice
-* Created: Thu Aug 27 20:39:49 2020
+* Created: Tue Sep  1 20:00:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pxi.spice b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pxi.spice
index edc3ca3..1370d54 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxbp_2.pxi.spice
-* Created: Thu Aug 27 20:39:49 2020
+* Created: Tue Sep  1 20:00:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFXBP_2%CLK N_CLK_c_221_n N_CLK_M1025_g N_CLK_c_222_n
 + N_CLK_M1017_g CLK N_CLK_c_223_n PM_SKY130_FD_SC_HS__DFXBP_2%CLK

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice
index 5fd2a6d..7a3219e 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxbp_2.spice
-* Created: Thu Aug 27 20:39:49 2020
+* Created: Tue Sep  1 20:00:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.lvs.report b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.lvs.report
new file mode 100644
index 0000000..2a9961e
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.lvs.report

@@ -0,0 +1,497 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfxtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfxtp_1.sp ('sky130_fd_sc_hs__dfxtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice ('sky130_fd_sc_hs__dfxtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:00:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfxtp_1      sky130_fd_sc_hs__dfxtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfxtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              18        18
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              14        14
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        20        20
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         20         20            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pex.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pex.spice
index 27bf83b..daa2003 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_1.pex.spice
-* Created: Thu Aug 27 20:39:57 2020
+* Created: Tue Sep  1 20:00:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pxi.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pxi.spice
index a7de5a2..9353217 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_1.pxi.spice
-* Created: Thu Aug 27 20:39:57 2020
+* Created: Tue Sep  1 20:00:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFXTP_1%CLK N_CLK_M1021_g N_CLK_c_183_n N_CLK_M1016_g CLK
 + N_CLK_c_184_n PM_SKY130_FD_SC_HS__DFXTP_1%CLK

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice
index 0df2dae..0794f78 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_1.spice
-* Created: Thu Aug 27 20:39:57 2020
+* Created: Tue Sep  1 20:00:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.lvs.report b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.lvs.report
new file mode 100644
index 0000000..77e7efd
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfxtp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfxtp_2.sp ('sky130_fd_sc_hs__dfxtp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice ('sky130_fd_sc_hs__dfxtp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfxtp_2      sky130_fd_sc_hs__dfxtp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfxtp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              18        18
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              14        14
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        20        20
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         20         20            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pex.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pex.spice
index ef53d87..2fc0973 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_2.pex.spice
-* Created: Thu Aug 27 20:40:07 2020
+* Created: Tue Sep  1 20:01:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pxi.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pxi.spice
index 527ada7..350ffcb 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_2.pxi.spice
-* Created: Thu Aug 27 20:40:07 2020
+* Created: Tue Sep  1 20:01:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFXTP_2%CLK N_CLK_M1022_g N_CLK_c_189_n N_CLK_M1017_g CLK
 + N_CLK_c_190_n PM_SKY130_FD_SC_HS__DFXTP_2%CLK

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice
index 27eee05..6b06eb7 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_2.spice
-* Created: Thu Aug 27 20:40:07 2020
+* Created: Tue Sep  1 20:01:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.lvs.report b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.lvs.report
new file mode 100644
index 0000000..113347a
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.lvs.report

@@ -0,0 +1,509 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dfxtp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dfxtp_4.sp ('sky130_fd_sc_hs__dfxtp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice ('sky130_fd_sc_hs__dfxtp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dfxtp_4      sky130_fd_sc_hs__dfxtp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dfxtp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              18        18
+
+ Instances:         15        15         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        32        31
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              14        14
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        20        20
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         20         20            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pex.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pex.spice
index 459a7cf..25ab0c6 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_4.pex.spice
-* Created: Thu Aug 27 20:40:14 2020
+* Created: Tue Sep  1 20:01:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pxi.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pxi.spice
index f34d501..4cb800e 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_4.pxi.spice
-* Created: Thu Aug 27 20:40:14 2020
+* Created: Tue Sep  1 20:01:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__DFXTP_4%CLK N_CLK_M1027_g N_CLK_c_214_n N_CLK_M1015_g CLK
 + N_CLK_c_215_n PM_SKY130_FD_SC_HS__DFXTP_4%CLK

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice
index 64c77aa..6c97ef1 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dfxtp_4.spice
-* Created: Thu Aug 27 20:40:14 2020
+* Created: Tue Sep  1 20:01:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/diode/sky130_fd_sc_hs__diode_2.lvs.report b/cells/diode/sky130_fd_sc_hs__diode_2.lvs.report
new file mode 100644
index 0000000..4d1b3b3
--- /dev/null
+++ b/cells/diode/sky130_fd_sc_hs__diode_2.lvs.report

@@ -0,0 +1,497 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__diode_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__diode_2.sp ('sky130_fd_sc_hs__diode_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/diode/sky130_fd_sc_hs__diode_2.spice ('sky130_fd_sc_hs__diode_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:13 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                  #   #         #####################  
+                   # #          #                   #  
+                    #           #     INCORRECT     #  
+                   # #          #                   #  
+                  #   #         #####################  
+
+
+  Error:    Different numbers of instances.
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  INCORRECT      sky130_fd_sc_hs__diode_2      sky130_fd_sc_hs__diode_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                  #   #         #####################  
+                   # #          #                   #  
+                    #           #     INCORRECT     #  
+                   # #          #                   #  
+                  #   #         #####################  
+
+
+  Error:    Different numbers of instances (see below).
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__diode_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__diode_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              5         5
+
+ Nets:               5         5
+
+ Instances:          0         1    *    D (2 pins): p n
+                     1         0    *    D (2 pins): p n
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         2         1
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              5         5
+
+ Nets:               5         5
+
+ Instances:          1         0    *    D (2 pins): p n
+                ------    ------
+ Total Inst:         1         0
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                                 INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+  ne  = Naming Error (same layout name found in source
+        circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+                                 INCORRECT INSTANCES
+
+DISC#  LAYOUT NAME                                               SOURCE NAME
+**************************************************************************************************************
+
+  1    D0(0.135,0.320)  D(NDIODE)                                ** missing instance **
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               5          5            0            0
+
+   Nets:                5          5            0            0
+
+   Instances:           0          0            1            0    D(NDIODE)
+                  -------    -------    ---------    ---------
+   Total Inst:          0          0            1            0
+
+
+o Statistics:
+
+   3 passthrough layout nets were found.
+   5 passthrough source nets were found.
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+   1 source instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+      (Layout nets which are connected only to ports).
+
+   VPWR (port: VPWR), VGND (port: VGND), VPB (port: VPB),
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB DIODE VGND VPWR
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/diode/sky130_fd_sc_hs__diode_2.pex.spice b/cells/diode/sky130_fd_sc_hs__diode_2.pex.spice
index 7109875..75ae94b 100644
--- a/cells/diode/sky130_fd_sc_hs__diode_2.pex.spice
+++ b/cells/diode/sky130_fd_sc_hs__diode_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__diode_2.pex.spice
-* Created: Thu Aug 27 20:40:22 2020
+* Created: Tue Sep  1 20:01:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/diode/sky130_fd_sc_hs__diode_2.pxi.spice b/cells/diode/sky130_fd_sc_hs__diode_2.pxi.spice
index 7a20474..7235a5a 100644
--- a/cells/diode/sky130_fd_sc_hs__diode_2.pxi.spice
+++ b/cells/diode/sky130_fd_sc_hs__diode_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__diode_2.pxi.spice
-* Created: Thu Aug 27 20:40:22 2020
+* Created: Tue Sep  1 20:01:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__DIODE_2%DIODE N_DIODE_D0_noxref_neg DIODE DIODE DIODE
 + DIODE DIODE DIODE DIODE N_DIODE_c_7_n PM_SKY130_FD_SC_HS__DIODE_2%DIODE

diff --git a/cells/diode/sky130_fd_sc_hs__diode_2.spice b/cells/diode/sky130_fd_sc_hs__diode_2.spice
index 8b2b1ce..fb2805d 100644
--- a/cells/diode/sky130_fd_sc_hs__diode_2.spice
+++ b/cells/diode/sky130_fd_sc_hs__diode_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__diode_2.spice
-* Created: Thu Aug 27 20:40:22 2020
+* Created: Tue Sep  1 20:01:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.lvs.report b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.lvs.report
new file mode 100644
index 0000000..24d8ccc
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.lvs.report

@@ -0,0 +1,493 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlclkp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlclkp_1.sp ('sky130_fd_sc_hs__dlclkp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice ('sky130_fd_sc_hs__dlclkp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:19 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlclkp_1     sky130_fd_sc_hs__dlclkp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlclkp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              17        17
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pex.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pex.spice
index cd7612b..8af8c3c 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_1.pex.spice
-* Created: Thu Aug 27 20:40:29 2020
+* Created: Tue Sep  1 20:01:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pxi.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pxi.spice
index a7fe9b0..83ae65b 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_1.pxi.spice
-* Created: Thu Aug 27 20:40:29 2020
+* Created: Tue Sep  1 20:01:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLCLKP_1%A_83_260# N_A_83_260#_M1019_d N_A_83_260#_M1013_d
 + N_A_83_260#_M1017_g N_A_83_260#_c_122_n N_A_83_260#_M1008_g

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice
index b1ac8da..0bc727e 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_1.spice
-* Created: Thu Aug 27 20:40:29 2020
+* Created: Tue Sep  1 20:01:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.lvs.report b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.lvs.report
new file mode 100644
index 0000000..5de3b7d
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.lvs.report

@@ -0,0 +1,500 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlclkp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlclkp_2.sp ('sky130_fd_sc_hs__dlclkp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice ('sky130_fd_sc_hs__dlclkp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlclkp_2     sky130_fd_sc_hs__dlclkp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlclkp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlclkp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              17        17
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pex.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pex.spice
index 12da180..f38b37a 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_2.pex.spice
-* Created: Thu Aug 27 20:40:37 2020
+* Created: Tue Sep  1 20:01:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pxi.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pxi.spice
index 7b40484..a98e883 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_2.pxi.spice
-* Created: Thu Aug 27 20:40:37 2020
+* Created: Tue Sep  1 20:01:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLCLKP_2%A_83_244# N_A_83_244#_M1013_d N_A_83_244#_M1004_d
 + N_A_83_244#_c_139_n N_A_83_244#_M1020_g N_A_83_244#_c_140_n

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice
index 54fae72..73a8b1d 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_2.spice
-* Created: Thu Aug 27 20:40:37 2020
+* Created: Tue Sep  1 20:01:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.lvs.report b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.lvs.report
new file mode 100644
index 0000000..5cd69b2
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlclkp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlclkp_4.sp ('sky130_fd_sc_hs__dlclkp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice ('sky130_fd_sc_hs__dlclkp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlclkp_4     sky130_fd_sc_hs__dlclkp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlclkp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlclkp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              17        17
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pex.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pex.spice
index 4d82649..64ec9c0 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_4.pex.spice
-* Created: Thu Aug 27 20:40:44 2020
+* Created: Tue Sep  1 20:01:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pxi.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pxi.spice
index 4662b2f..28116ea 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_4.pxi.spice
-* Created: Thu Aug 27 20:40:44 2020
+* Created: Tue Sep  1 20:01:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLCLKP_4%A_84_48# N_A_84_48#_M1018_d N_A_84_48#_M1009_d
 + N_A_84_48#_c_147_n N_A_84_48#_M1021_g N_A_84_48#_c_148_n N_A_84_48#_M1011_g

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice
index 1ffe622..bbe13ba 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlclkp_4.spice
-* Created: Thu Aug 27 20:40:44 2020
+* Created: Tue Sep  1 20:01:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.lvs.report b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.lvs.report
new file mode 100644
index 0000000..65d5e91
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.lvs.report

@@ -0,0 +1,497 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrbn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrbn_1.sp ('sky130_fd_sc_hs__dlrbn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice ('sky130_fd_sc_hs__dlrbn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrbn_1      sky130_fd_sc_hs__dlrbn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrbn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              20        20
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        19        19
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         19         19            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pex.spice b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pex.spice
index f359a6a..867fca6 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbn_1.pex.spice
-* Created: Thu Aug 27 20:40:52 2020
+* Created: Tue Sep  1 20:01:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pxi.spice b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pxi.spice
index 5531f90..436c543 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbn_1.pxi.spice
-* Created: Thu Aug 27 20:40:52 2020
+* Created: Tue Sep  1 20:01:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRBN_1%D N_D_c_155_n N_D_M1009_g N_D_c_160_n N_D_M1019_g
 + D N_D_c_158_n PM_SKY130_FD_SC_HS__DLRBN_1%D

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice
index 5bfa958..5affb2a 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbn_1.spice
-* Created: Thu Aug 27 20:40:52 2020
+* Created: Tue Sep  1 20:01:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.lvs.report b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.lvs.report
new file mode 100644
index 0000000..3bf0f22
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrbn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrbn_2.sp ('sky130_fd_sc_hs__dlrbn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice ('sky130_fd_sc_hs__dlrbn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrbn_2      sky130_fd_sc_hs__dlrbn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrbn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              20        20
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        19        19
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         19         19            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pex.spice b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pex.spice
index 0457c71..7d1154d 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbn_2.pex.spice
-* Created: Thu Aug 27 20:41:00 2020
+* Created: Tue Sep  1 20:01:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pxi.spice b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pxi.spice
index 87b16fa..0b6adf7 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbn_2.pxi.spice
-* Created: Thu Aug 27 20:41:00 2020
+* Created: Tue Sep  1 20:01:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRBN_2%D N_D_c_176_n N_D_M1015_g N_D_c_181_n N_D_M1022_g
 + D N_D_c_179_n PM_SKY130_FD_SC_HS__DLRBN_2%D

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice
index 475e646..ddf49c0 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbn_2.spice
-* Created: Thu Aug 27 20:41:00 2020
+* Created: Tue Sep  1 20:01:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.lvs.report b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.lvs.report
new file mode 100644
index 0000000..2b9af11
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.lvs.report

@@ -0,0 +1,497 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrbp_1.sp ('sky130_fd_sc_hs__dlrbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice ('sky130_fd_sc_hs__dlrbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrbp_1      sky130_fd_sc_hs__dlrbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              20        20
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        19        19
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         19         19            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pex.spice b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pex.spice
index 2bc6084..8a19f5d 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbp_1.pex.spice
-* Created: Thu Aug 27 20:41:10 2020
+* Created: Tue Sep  1 20:01:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pxi.spice b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pxi.spice
index 76c5249..c77cd19 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbp_1.pxi.spice
-* Created: Thu Aug 27 20:41:10 2020
+* Created: Tue Sep  1 20:01:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRBP_1%D N_D_M1006_g N_D_c_159_n N_D_M1005_g D
 + PM_SKY130_FD_SC_HS__DLRBP_1%D

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice
index 6941589..0bc1194 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbp_1.spice
-* Created: Thu Aug 27 20:41:10 2020
+* Created: Tue Sep  1 20:01:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.lvs.report b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.lvs.report
new file mode 100644
index 0000000..caef061
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrbp_2.sp ('sky130_fd_sc_hs__dlrbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice ('sky130_fd_sc_hs__dlrbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:01:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrbp_2      sky130_fd_sc_hs__dlrbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              20        20
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        19        19
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         19         19            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pex.spice b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pex.spice
index 011b49c..2163202 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbp_2.pex.spice
-* Created: Thu Aug 27 20:41:18 2020
+* Created: Tue Sep  1 20:01:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pxi.spice b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pxi.spice
index 7553562..ed14252 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbp_2.pxi.spice
-* Created: Thu Aug 27 20:41:18 2020
+* Created: Tue Sep  1 20:01:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRBP_2%D N_D_M1016_g N_D_c_173_n N_D_M1009_g D
 + PM_SKY130_FD_SC_HS__DLRBP_2%D

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice
index faafa8e..9df3e90 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrbp_2.spice
-* Created: Thu Aug 27 20:41:18 2020
+* Created: Tue Sep  1 20:01:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.lvs.report b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.lvs.report
new file mode 100644
index 0000000..5461e63
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.lvs.report

@@ -0,0 +1,493 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrtn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrtn_1.sp ('sky130_fd_sc_hs__dlrtn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice ('sky130_fd_sc_hs__dlrtn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrtn_1      sky130_fd_sc_hs__dlrtn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrtn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               13         13            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pex.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pex.spice
index dca760c..9aceca7 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_1.pex.spice
-* Created: Thu Aug 27 20:41:25 2020
+* Created: Tue Sep  1 20:02:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pxi.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pxi.spice
index 16c2844..b7cf33c 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_1.pxi.spice
-* Created: Thu Aug 27 20:41:25 2020
+* Created: Tue Sep  1 20:02:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRTN_1%D N_D_M1011_g N_D_c_126_n N_D_M1000_g D
 + PM_SKY130_FD_SC_HS__DLRTN_1%D

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice
index 9f010a1..dcd3314 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_1.spice
-* Created: Thu Aug 27 20:41:25 2020
+* Created: Tue Sep  1 20:02:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.lvs.report b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.lvs.report
new file mode 100644
index 0000000..b65d115
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.lvs.report

@@ -0,0 +1,500 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrtn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrtn_2.sp ('sky130_fd_sc_hs__dlrtn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice ('sky130_fd_sc_hs__dlrtn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrtn_2      sky130_fd_sc_hs__dlrtn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrtn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrtn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               13         13            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pex.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pex.spice
index ced3f1b..5b861e8 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_2.pex.spice
-* Created: Thu Aug 27 20:41:32 2020
+* Created: Tue Sep  1 20:02:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pxi.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pxi.spice
index d761d44..fffca9e 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_2.pxi.spice
-* Created: Thu Aug 27 20:41:32 2020
+* Created: Tue Sep  1 20:02:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRTN_2%D N_D_M1018_g N_D_c_142_n N_D_M1004_g D
 + PM_SKY130_FD_SC_HS__DLRTN_2%D

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice
index 25ad64f..e39d74d 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_2.spice
-* Created: Thu Aug 27 20:41:32 2020
+* Created: Tue Sep  1 20:02:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.lvs.report b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.lvs.report
new file mode 100644
index 0000000..d135c20
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.lvs.report

@@ -0,0 +1,508 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrtn_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrtn_4.sp ('sky130_fd_sc_hs__dlrtn_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice ('sky130_fd_sc_hs__dlrtn_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrtn_4      sky130_fd_sc_hs__dlrtn_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrtn_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrtn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         15        15         MN (4 pins)
+                    15        15         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               13         13            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pex.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pex.spice
index 5212f14..dd3aeac 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_4.pex.spice
-* Created: Thu Aug 27 20:41:40 2020
+* Created: Tue Sep  1 20:02:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pxi.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pxi.spice
index f2dbb33..56439d5 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_4.pxi.spice
-* Created: Thu Aug 27 20:41:40 2020
+* Created: Tue Sep  1 20:02:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRTN_4%D N_D_M1026_g N_D_c_169_n N_D_M1006_g D
 + PM_SKY130_FD_SC_HS__DLRTN_4%D

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice
index a0a0714..e6ebbc0 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtn_4.spice
-* Created: Thu Aug 27 20:41:40 2020
+* Created: Tue Sep  1 20:02:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.lvs.report b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.lvs.report
new file mode 100644
index 0000000..f209827
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.lvs.report

@@ -0,0 +1,493 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrtp_1.sp ('sky130_fd_sc_hs__dlrtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice ('sky130_fd_sc_hs__dlrtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrtp_1      sky130_fd_sc_hs__dlrtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               13         13            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pex.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pex.spice
index 7d7e607..7521a83 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_1.pex.spice
-* Created: Thu Aug 27 20:41:47 2020
+* Created: Tue Sep  1 20:02:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pxi.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pxi.spice
index 732c9b5..3e8cd87 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_1.pxi.spice
-* Created: Thu Aug 27 20:41:47 2020
+* Created: Tue Sep  1 20:02:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRTP_1%D N_D_c_137_n N_D_c_138_n N_D_M1012_g N_D_M1017_g
 + D N_D_c_135_n N_D_c_136_n PM_SKY130_FD_SC_HS__DLRTP_1%D

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice
index e0665ec..40ddd94 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_1.spice
-* Created: Thu Aug 27 20:41:47 2020
+* Created: Tue Sep  1 20:02:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.lvs.report b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.lvs.report
new file mode 100644
index 0000000..d0cbb83
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.lvs.report

@@ -0,0 +1,500 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrtp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrtp_2.sp ('sky130_fd_sc_hs__dlrtp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice ('sky130_fd_sc_hs__dlrtp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrtp_2      sky130_fd_sc_hs__dlrtp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrtp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               13         13            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pex.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pex.spice
index b8a3c2e..4228228 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_2.pex.spice
-* Created: Thu Aug 27 20:41:56 2020
+* Created: Tue Sep  1 20:02:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pxi.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pxi.spice
index e693a20..005a6d4 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_2.pxi.spice
-* Created: Thu Aug 27 20:41:56 2020
+* Created: Tue Sep  1 20:02:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRTP_2%D N_D_c_139_n N_D_M1006_g N_D_M1009_g D
 + N_D_c_141_n PM_SKY130_FD_SC_HS__DLRTP_2%D

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice
index fb76eb9..46df8f0 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_2.spice
-* Created: Thu Aug 27 20:41:56 2020
+* Created: Tue Sep  1 20:02:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.lvs.report b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.lvs.report
new file mode 100644
index 0000000..2b8a5c9
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.lvs.report

@@ -0,0 +1,508 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlrtp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlrtp_4.sp ('sky130_fd_sc_hs__dlrtp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice ('sky130_fd_sc_hs__dlrtp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlrtp_4      sky130_fd_sc_hs__dlrtp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlrtp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         15        15         MN (4 pins)
+                    15        15         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          4         4         MN (4 pins)
+                     6         6         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        15        15
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               13         13            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         15         15            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pex.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pex.spice
index 856a673..4e4cbd4 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_4.pex.spice
-* Created: Thu Aug 27 20:42:03 2020
+* Created: Tue Sep  1 20:02:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pxi.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pxi.spice
index ec5e550..3b303a7 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_4.pxi.spice
-* Created: Thu Aug 27 20:42:03 2020
+* Created: Tue Sep  1 20:02:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLRTP_4%D N_D_M1019_g N_D_c_179_n N_D_M1009_g D
 + N_D_c_180_n PM_SKY130_FD_SC_HS__DLRTP_4%D

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice
index 2ef7577..e9142f1 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlrtp_4.spice
-* Created: Thu Aug 27 20:42:03 2020
+* Created: Tue Sep  1 20:02:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.lvs.report b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.lvs.report
new file mode 100644
index 0000000..28e2b28
--- /dev/null
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.lvs.report

@@ -0,0 +1,495 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxbn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxbn_1.sp ('sky130_fd_sc_hs__dlxbn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice ('sky130_fd_sc_hs__dlxbn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxbn_1      sky130_fd_sc_hs__dlxbn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxbn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pex.spice b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pex.spice
index 2f50dbf..85bc694 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pex.spice
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbn_1.pex.spice
-* Created: Thu Aug 27 20:42:14 2020
+* Created: Tue Sep  1 20:02:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pxi.spice b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pxi.spice
index 7af79ac..341677b 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pxi.spice
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbn_1.pxi.spice
-* Created: Thu Aug 27 20:42:14 2020
+* Created: Tue Sep  1 20:02:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXBN_1%D N_D_M1018_g N_D_c_139_n N_D_c_144_n N_D_M1015_g
 + D N_D_c_141_n N_D_c_142_n PM_SKY130_FD_SC_HS__DLXBN_1%D

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice
index 3e57e81..5a1724e 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbn_1.spice
-* Created: Thu Aug 27 20:42:14 2020
+* Created: Tue Sep  1 20:02:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.lvs.report b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.lvs.report
new file mode 100644
index 0000000..26a1b6a
--- /dev/null
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxbn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxbn_2.sp ('sky130_fd_sc_hs__dlxbn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice ('sky130_fd_sc_hs__dlxbn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxbn_2      sky130_fd_sc_hs__dlxbn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxbn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pex.spice b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pex.spice
index 2249b52..1e440df 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pex.spice
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbn_2.pex.spice
-* Created: Thu Aug 27 20:42:21 2020
+* Created: Tue Sep  1 20:02:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pxi.spice b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pxi.spice
index 4228880..4495b47 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pxi.spice
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbn_2.pxi.spice
-* Created: Thu Aug 27 20:42:21 2020
+* Created: Tue Sep  1 20:02:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXBN_2%D N_D_M1021_g N_D_c_167_n N_D_c_168_n N_D_M1003_g
 + D N_D_c_166_n PM_SKY130_FD_SC_HS__DLXBN_2%D

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice
index 2e0139a..3a68ea9 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbn_2.spice
-* Created: Thu Aug 27 20:42:21 2020
+* Created: Tue Sep  1 20:02:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.lvs.report b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.lvs.report
new file mode 100644
index 0000000..db30798
--- /dev/null
+++ b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.lvs.report

@@ -0,0 +1,495 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxbp_1.sp ('sky130_fd_sc_hs__dlxbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice ('sky130_fd_sc_hs__dlxbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxbp_1      sky130_fd_sc_hs__dlxbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pex.spice b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pex.spice
index b7d5a47..76be049 100644
--- a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pex.spice
+++ b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbp_1.pex.spice
-* Created: Thu Aug 27 20:42:28 2020
+* Created: Tue Sep  1 20:02:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pxi.spice b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pxi.spice
index 6adbe3b..16d5ceb 100644
--- a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pxi.spice
+++ b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbp_1.pxi.spice
-* Created: Thu Aug 27 20:42:28 2020
+* Created: Tue Sep  1 20:02:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXBP_1%D N_D_c_143_n N_D_M1006_g N_D_c_148_n N_D_M1018_g
 + D N_D_c_145_n N_D_c_146_n PM_SKY130_FD_SC_HS__DLXBP_1%D

diff --git a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice
index bdc70db..f2cf213 100644
--- a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice
+++ b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxbp_1.spice
-* Created: Thu Aug 27 20:42:28 2020
+* Created: Tue Sep  1 20:02:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.lvs.report b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.lvs.report
new file mode 100644
index 0000000..01077fc
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.lvs.report

@@ -0,0 +1,491 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxtn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxtn_1.sp ('sky130_fd_sc_hs__dlxtn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice ('sky130_fd_sc_hs__dlxtn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:02:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxtn_1      sky130_fd_sc_hs__dlxtn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxtn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              16        16
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        14        14
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         14         14            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pex.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pex.spice
index 7708131..2c1c9a4 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_1.pex.spice
-* Created: Thu Aug 27 20:42:36 2020
+* Created: Tue Sep  1 20:02:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pxi.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pxi.spice
index 6ef27ae..4b4d9ce 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_1.pxi.spice
-* Created: Thu Aug 27 20:42:36 2020
+* Created: Tue Sep  1 20:02:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXTN_1%D N_D_c_127_n N_D_M1005_g N_D_c_128_n N_D_c_132_n
 + N_D_M1001_g D N_D_c_130_n PM_SKY130_FD_SC_HS__DLXTN_1%D

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice
index b78128f..9f1fc30 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_1.spice
-* Created: Thu Aug 27 20:42:36 2020
+* Created: Tue Sep  1 20:02:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.lvs.report b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.lvs.report
new file mode 100644
index 0000000..9999eb1
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxtn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxtn_2.sp ('sky130_fd_sc_hs__dlxtn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice ('sky130_fd_sc_hs__dlxtn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxtn_2      sky130_fd_sc_hs__dlxtn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxtn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxtn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              16        16
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        14        14
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         14         14            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pex.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pex.spice
index 36abd97..cbf46a3 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_2.pex.spice
-* Created: Thu Aug 27 20:42:43 2020
+* Created: Tue Sep  1 20:03:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pxi.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pxi.spice
index c874cf3..7aecd3b 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_2.pxi.spice
-* Created: Thu Aug 27 20:42:43 2020
+* Created: Tue Sep  1 20:03:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXTN_2%D N_D_M1017_g N_D_c_136_n N_D_c_140_n N_D_M1008_g
 + D N_D_c_137_n N_D_c_138_n PM_SKY130_FD_SC_HS__DLXTN_2%D

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice
index e1a3784..84acd47 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_2.spice
-* Created: Thu Aug 27 20:42:43 2020
+* Created: Tue Sep  1 20:03:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.lvs.report b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.lvs.report
new file mode 100644
index 0000000..cce9845
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxtn_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxtn_4.sp ('sky130_fd_sc_hs__dlxtn_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice ('sky130_fd_sc_hs__dlxtn_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxtn_4      sky130_fd_sc_hs__dlxtn_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxtn_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxtn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              16        16
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        14        14
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         14         14            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pex.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pex.spice
index cc6d3b4..963ab7b 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_4.pex.spice
-* Created: Thu Aug 27 20:42:51 2020
+* Created: Tue Sep  1 20:03:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pxi.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pxi.spice
index e002c63..84d0b51 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_4.pxi.spice
-* Created: Thu Aug 27 20:42:51 2020
+* Created: Tue Sep  1 20:03:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXTN_4%D N_D_M1011_g N_D_c_157_n N_D_c_161_n N_D_M1004_g
 + D N_D_c_158_n N_D_c_159_n PM_SKY130_FD_SC_HS__DLXTN_4%D

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice
index 2ae8699..3a9400c 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtn_4.spice
-* Created: Thu Aug 27 20:42:51 2020
+* Created: Tue Sep  1 20:03:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.lvs.report b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.lvs.report
new file mode 100644
index 0000000..fc194de
--- /dev/null
+++ b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.lvs.report

@@ -0,0 +1,491 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlxtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlxtp_1.sp ('sky130_fd_sc_hs__dlxtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice ('sky130_fd_sc_hs__dlxtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlxtp_1      sky130_fd_sc_hs__dlxtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlxtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              16        16
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        14        14
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         14         14            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D GATE VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pex.spice b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pex.spice
index f494251..72593e3 100644
--- a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pex.spice
+++ b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtp_1.pex.spice
-* Created: Thu Aug 27 20:42:59 2020
+* Created: Tue Sep  1 20:03:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pxi.spice b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pxi.spice
index 7e6463f..1aed4fe 100644
--- a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pxi.spice
+++ b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtp_1.pxi.spice
-* Created: Thu Aug 27 20:42:59 2020
+* Created: Tue Sep  1 20:03:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLXTP_1%D N_D_c_150_n N_D_M1013_g N_D_M1008_g N_D_c_147_n
 + D D N_D_c_149_n PM_SKY130_FD_SC_HS__DLXTP_1%D

diff --git a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice
index f3b3be8..670fdb9 100644
--- a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice
+++ b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlxtp_1.spice
-* Created: Thu Aug 27 20:42:59 2020
+* Created: Tue Sep  1 20:03:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.lvs.report b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.lvs.report
new file mode 100644
index 0000000..c3bb1cc
--- /dev/null
+++ b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlygate4sd1_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlygate4sd1_1.sp ('sky130_fd_sc_hs__dlygate4sd1_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice ('sky130_fd_sc_hs__dlygate4sd1_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlygate4sd1_1 sky130_fd_sc_hs__dlygate4sd1_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlygate4sd1_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlygate4sd1_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pex.spice b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pex.spice
index 2c040a5..6d74150 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pex.spice
+++ b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd1_1.pex.spice
-* Created: Thu Aug 27 20:43:07 2020
+* Created: Tue Sep  1 20:03:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pxi.spice b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pxi.spice
index a7379d4..99f5928 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pxi.spice
+++ b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd1_1.pxi.spice
-* Created: Thu Aug 27 20:43:07 2020
+* Created: Tue Sep  1 20:03:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLYGATE4SD1_1%A N_A_M1004_g N_A_c_66_n N_A_c_70_n
 + N_A_M1006_g A A N_A_c_68_n PM_SKY130_FD_SC_HS__DLYGATE4SD1_1%A

diff --git a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice
index cc49114..e22cb1f 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice
+++ b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd1_1.spice
-* Created: Thu Aug 27 20:43:07 2020
+* Created: Tue Sep  1 20:03:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.lvs.report b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.lvs.report
new file mode 100644
index 0000000..e5cec96
--- /dev/null
+++ b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlygate4sd2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlygate4sd2_1.sp ('sky130_fd_sc_hs__dlygate4sd2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice ('sky130_fd_sc_hs__dlygate4sd2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlygate4sd2_1 sky130_fd_sc_hs__dlygate4sd2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlygate4sd2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlygate4sd2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pex.spice b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pex.spice
index 647ccd0..acd6bf5 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pex.spice
+++ b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd2_1.pex.spice
-* Created: Thu Aug 27 20:43:17 2020
+* Created: Tue Sep  1 20:03:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pxi.spice b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pxi.spice
index 00e32c9..ae98b8c 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pxi.spice
+++ b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd2_1.pxi.spice
-* Created: Thu Aug 27 20:43:17 2020
+* Created: Tue Sep  1 20:03:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLYGATE4SD2_1%A N_A_M1002_g N_A_c_65_n N_A_c_69_n
 + N_A_M1005_g A A N_A_c_67_n PM_SKY130_FD_SC_HS__DLYGATE4SD2_1%A

diff --git a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice
index 81e8706..0ce8b41 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice
+++ b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd2_1.spice
-* Created: Thu Aug 27 20:43:17 2020
+* Created: Tue Sep  1 20:03:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.lvs.report b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.lvs.report
new file mode 100644
index 0000000..d0648e6
--- /dev/null
+++ b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.lvs.report

@@ -0,0 +1,477 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlygate4sd3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlygate4sd3_1.sp ('sky130_fd_sc_hs__dlygate4sd3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice ('sky130_fd_sc_hs__dlygate4sd3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlygate4sd3_1 sky130_fd_sc_hs__dlygate4sd3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlygate4sd3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlygate4sd3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pex.spice b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pex.spice
index a877a58..8f0f80f 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pex.spice
+++ b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd3_1.pex.spice
-* Created: Thu Aug 27 20:43:24 2020
+* Created: Tue Sep  1 20:03:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pxi.spice b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pxi.spice
index ce9ffa0..b750131 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pxi.spice
+++ b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd3_1.pxi.spice
-* Created: Thu Aug 27 20:43:24 2020
+* Created: Tue Sep  1 20:03:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLYGATE4SD3_1%A N_A_M1004_g N_A_c_64_n N_A_c_68_n
 + N_A_M1007_g A A N_A_c_66_n PM_SKY130_FD_SC_HS__DLYGATE4SD3_1%A

diff --git a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice
index e021c81..ca83743 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice
+++ b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlygate4sd3_1.spice
-* Created: Thu Aug 27 20:43:24 2020
+* Created: Tue Sep  1 20:03:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.lvs.report b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.lvs.report
new file mode 100644
index 0000000..a608372
--- /dev/null
+++ b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlymetal6s2s_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlymetal6s2s_1.sp ('sky130_fd_sc_hs__dlymetal6s2s_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice ('sky130_fd_sc_hs__dlymetal6s2s_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlymetal6s2s_1 sky130_fd_sc_hs__dlymetal6s2s_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlymetal6s2s_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlymetal6s2s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                ------    ------
+ Total Inst:        12        12
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         12         12            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pex.spice b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pex.spice
index 7805ced..04fa877 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pex.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s2s_1.pex.spice
-* Created: Thu Aug 27 20:43:32 2020
+* Created: Tue Sep  1 20:03:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pxi.spice b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pxi.spice
index 9530c36..0d225ff 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pxi.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s2s_1.pxi.spice
-* Created: Thu Aug 27 20:43:32 2020
+* Created: Tue Sep  1 20:03:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLYMETAL6S2S_1%A N_A_M1006_g N_A_c_88_n N_A_M1004_g A
 + N_A_c_89_n PM_SKY130_FD_SC_HS__DLYMETAL6S2S_1%A

diff --git a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice
index 2da110b..c34c4f8 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s2s_1.spice
-* Created: Thu Aug 27 20:43:32 2020
+* Created: Tue Sep  1 20:03:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.lvs.report b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.lvs.report
new file mode 100644
index 0000000..221b95b
--- /dev/null
+++ b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlymetal6s4s_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlymetal6s4s_1.sp ('sky130_fd_sc_hs__dlymetal6s4s_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice ('sky130_fd_sc_hs__dlymetal6s4s_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlymetal6s4s_1 sky130_fd_sc_hs__dlymetal6s4s_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlymetal6s4s_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlymetal6s4s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                ------    ------
+ Total Inst:        12        12
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         12         12            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pex.spice b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pex.spice
index 48f1137..85a34f7 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pex.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s4s_1.pex.spice
-* Created: Thu Aug 27 20:43:39 2020
+* Created: Tue Sep  1 20:03:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pxi.spice b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pxi.spice
index e3fce51..bcb80b8 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pxi.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s4s_1.pxi.spice
-* Created: Thu Aug 27 20:43:39 2020
+* Created: Tue Sep  1 20:03:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLYMETAL6S4S_1%A N_A_M1006_g N_A_c_89_n N_A_M1004_g A
 + N_A_c_90_n PM_SKY130_FD_SC_HS__DLYMETAL6S4S_1%A

diff --git a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice
index de062ec..a0ae6a2 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s4s_1.spice
-* Created: Thu Aug 27 20:43:39 2020
+* Created: Tue Sep  1 20:03:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.lvs.report b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.lvs.report
new file mode 100644
index 0000000..5efbc62
--- /dev/null
+++ b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__dlymetal6s6s_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__dlymetal6s6s_1.sp ('sky130_fd_sc_hs__dlymetal6s6s_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice ('sky130_fd_sc_hs__dlymetal6s6s_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__dlymetal6s6s_1 sky130_fd_sc_hs__dlymetal6s6s_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__dlymetal6s6s_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__dlymetal6s6s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                ------    ------
+ Total Inst:        12        12
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         12         12            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pex.spice b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pex.spice
index c0d2d43..a964c1b 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pex.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s6s_1.pex.spice
-* Created: Thu Aug 27 20:43:47 2020
+* Created: Tue Sep  1 20:03:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pxi.spice b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pxi.spice
index ae8473d..93d425b 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pxi.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s6s_1.pxi.spice
-* Created: Thu Aug 27 20:43:47 2020
+* Created: Tue Sep  1 20:03:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__DLYMETAL6S6S_1%A N_A_M1006_g N_A_c_88_n N_A_M1004_g A
 + N_A_c_89_n PM_SKY130_FD_SC_HS__DLYMETAL6S6S_1%A

diff --git a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice
index 78ae4da..38856c8 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__dlymetal6s6s_1.spice
-* Created: Thu Aug 27 20:43:47 2020
+* Created: Tue Sep  1 20:03:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.lvs.report b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.lvs.report
new file mode 100644
index 0000000..8abac25
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.lvs.report

@@ -0,0 +1,481 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ebufn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ebufn_1.sp ('sky130_fd_sc_hs__ebufn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice ('sky130_fd_sc_hs__ebufn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:03:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ebufn_1      sky130_fd_sc_hs__ebufn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ebufn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__ebufn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pex.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pex.spice
index a8cdfeb..6933b43 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_1.pex.spice
-* Created: Thu Aug 27 20:43:54 2020
+* Created: Tue Sep  1 20:03:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pxi.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pxi.spice
index d0deec6..e6e4279 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_1.pxi.spice
-* Created: Thu Aug 27 20:43:54 2020
+* Created: Tue Sep  1 20:03:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__EBUFN_1%TE_B N_TE_B_c_68_n N_TE_B_M1002_g N_TE_B_M1007_g
 + N_TE_B_c_70_n N_TE_B_c_71_n N_TE_B_c_76_n N_TE_B_M1006_g N_TE_B_c_77_n

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice
index 510f768..ad9e5a2 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_1.spice
-* Created: Thu Aug 27 20:43:54 2020
+* Created: Tue Sep  1 20:03:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.lvs.report b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.lvs.report
new file mode 100644
index 0000000..00d51bd
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ebufn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ebufn_2.sp ('sky130_fd_sc_hs__ebufn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice ('sky130_fd_sc_hs__ebufn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ebufn_2      sky130_fd_sc_hs__ebufn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ebufn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__ebufn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pex.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pex.spice
index ad1e5ab..b9ff020 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_2.pex.spice
-* Created: Thu Aug 27 20:44:03 2020
+* Created: Tue Sep  1 20:04:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pxi.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pxi.spice
index 9c38438..d537c4a 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_2.pxi.spice
-* Created: Thu Aug 27 20:44:03 2020
+* Created: Tue Sep  1 20:04:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__EBUFN_2%A_84_48# N_A_84_48#_M1001_d N_A_84_48#_M1002_d
 + N_A_84_48#_M1009_g N_A_84_48#_c_86_n N_A_84_48#_M1004_g N_A_84_48#_M1010_g

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice
index b2015a6..8a2e067 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_2.spice
-* Created: Thu Aug 27 20:44:03 2020
+* Created: Tue Sep  1 20:04:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.lvs.report b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.lvs.report
new file mode 100644
index 0000000..4edac55
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ebufn_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ebufn_4.sp ('sky130_fd_sc_hs__ebufn_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice ('sky130_fd_sc_hs__ebufn_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ebufn_4      sky130_fd_sc_hs__ebufn_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ebufn_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__ebufn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A TE_B VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pex.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pex.spice
index 833c295..7c992ce 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_4.pex.spice
-* Created: Thu Aug 27 20:44:10 2020
+* Created: Tue Sep  1 20:04:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pxi.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pxi.spice
index f8a2e84..6c47abb 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_4.pxi.spice
-* Created: Thu Aug 27 20:44:10 2020
+* Created: Tue Sep  1 20:04:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__EBUFN_4%A N_A_c_124_n N_A_M1012_g N_A_M1003_g A
 + PM_SKY130_FD_SC_HS__EBUFN_4%A

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice
index d8c205c..82fe7d8 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_4.spice
-* Created: Thu Aug 27 20:44:10 2020
+* Created: Tue Sep  1 20:04:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.lvs.report b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.lvs.report
new file mode 100644
index 0000000..3506d35
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.lvs.report

@@ -0,0 +1,516 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ebufn_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ebufn_8.sp ('sky130_fd_sc_hs__ebufn_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice ('sky130_fd_sc_hs__ebufn_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ebufn_8      sky130_fd_sc_hs__ebufn_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ebufn_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__ebufn_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:         19        19         MN (4 pins)
+                    19        19         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   36 layout mos transistors were reduced to 6.
+     30 mos transistors were deleted by parallel reduction.
+   36 source mos transistors were reduced to 6.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pex.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pex.spice
index 61e17a0..757a284 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_8.pex.spice
-* Created: Thu Aug 27 20:44:20 2020
+* Created: Tue Sep  1 20:04:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pxi.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pxi.spice
index 9210018..85b5f73 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_8.pxi.spice
-* Created: Thu Aug 27 20:44:20 2020
+* Created: Tue Sep  1 20:04:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__EBUFN_8%A_84_48# N_A_84_48#_M1008_d N_A_84_48#_M1000_d
 + N_A_84_48#_M1005_g N_A_84_48#_c_218_n N_A_84_48#_M1006_g N_A_84_48#_M1009_g

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice
index 6b6d87a..92b61f0 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ebufn_8.spice
-* Created: Thu Aug 27 20:44:20 2020
+* Created: Tue Sep  1 20:04:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.lvs.report b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.lvs.report
new file mode 100644
index 0000000..458d076
--- /dev/null
+++ b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.lvs.report

@@ -0,0 +1,509 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__edfxbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__edfxbp_1.sp ('sky130_fd_sc_hs__edfxbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice ('sky130_fd_sc_hs__edfxbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__edfxbp_1     sky130_fd_sc_hs__edfxbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__edfxbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__edfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              27        27
+
+ Instances:         18        18         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        37        36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        26        26
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         26         26            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pex.spice b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pex.spice
index 48375ef..3326243 100644
--- a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pex.spice
+++ b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__edfxbp_1.pex.spice
-* Created: Thu Aug 27 20:44:28 2020
+* Created: Tue Sep  1 20:04:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pxi.spice b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pxi.spice
index 6a4f8eb..cef8bba 100644
--- a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pxi.spice
+++ b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__edfxbp_1.pxi.spice
-* Created: Thu Aug 27 20:44:28 2020
+* Created: Tue Sep  1 20:04:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__EDFXBP_1%D N_D_c_285_n N_D_c_290_n N_D_c_291_n N_D_M1000_g
 + N_D_M1031_g D D N_D_c_287_n N_D_c_288_n N_D_c_293_n

diff --git a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice
index 203e432..b1dd158 100644
--- a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice
+++ b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__edfxbp_1.spice
-* Created: Thu Aug 27 20:44:28 2020
+* Created: Tue Sep  1 20:04:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.lvs.report b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.lvs.report
new file mode 100644
index 0000000..3e60843
--- /dev/null
+++ b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.lvs.report

@@ -0,0 +1,507 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__edfxtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__edfxtp_1.sp ('sky130_fd_sc_hs__edfxtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice ('sky130_fd_sc_hs__edfxtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__edfxtp_1     sky130_fd_sc_hs__edfxtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__edfxtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__edfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              26        26
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              16        16
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pex.spice b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pex.spice
index db09710..3ecde5b 100644
--- a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pex.spice
+++ b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__edfxtp_1.pex.spice
-* Created: Thu Aug 27 20:44:35 2020
+* Created: Tue Sep  1 20:04:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pxi.spice b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pxi.spice
index d20d4da..6b69268 100644
--- a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pxi.spice
+++ b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__edfxtp_1.pxi.spice
-* Created: Thu Aug 27 20:44:35 2020
+* Created: Tue Sep  1 20:04:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__EDFXTP_1%D N_D_c_269_n N_D_c_270_n N_D_M1020_g N_D_M1013_g
 + D D N_D_c_266_n N_D_c_267_n N_D_c_268_n N_D_c_273_n

diff --git a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice
index 434e612..94106b2 100644
--- a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice
+++ b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__edfxtp_1.spice
-* Created: Thu Aug 27 20:44:35 2020
+* Created: Tue Sep  1 20:04:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_1.lvs.report b/cells/einvn/sky130_fd_sc_hs__einvn_1.lvs.report
new file mode 100644
index 0000000..ffe7e39
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvn_1.sp ('sky130_fd_sc_hs__einvn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_1.spice ('sky130_fd_sc_hs__einvn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvn_1      sky130_fd_sc_hs__einvn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_1.pex.spice b/cells/einvn/sky130_fd_sc_hs__einvn_1.pex.spice
index f6b72fd..363cffb 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_1.pex.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_1.pex.spice
-* Created: Thu Aug 27 20:44:43 2020
+* Created: Tue Sep  1 20:04:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_1.pxi.spice b/cells/einvn/sky130_fd_sc_hs__einvn_1.pxi.spice
index f342291..84d90f9 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_1.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_1.pxi.spice
-* Created: Thu Aug 27 20:44:43 2020
+* Created: Tue Sep  1 20:04:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVN_1%A_22_46# N_A_22_46#_M1005_s N_A_22_46#_M1002_s
 + N_A_22_46#_c_42_n N_A_22_46#_c_43_n N_A_22_46#_M1001_g N_A_22_46#_c_44_n

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_1.spice b/cells/einvn/sky130_fd_sc_hs__einvn_1.spice
index 4a19fe0..9644f5e 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_1.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_1.spice
-* Created: Thu Aug 27 20:44:43 2020
+* Created: Tue Sep  1 20:04:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_2.lvs.report b/cells/einvn/sky130_fd_sc_hs__einvn_2.lvs.report
new file mode 100644
index 0000000..c4653d2
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_2.lvs.report

@@ -0,0 +1,488 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvn_2.sp ('sky130_fd_sc_hs__einvn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_2.spice ('sky130_fd_sc_hs__einvn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvn_2      sky130_fd_sc_hs__einvn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_2.pex.spice b/cells/einvn/sky130_fd_sc_hs__einvn_2.pex.spice
index 1f2f435..9963918 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_2.pex.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_2.pex.spice
-* Created: Thu Aug 27 20:44:50 2020
+* Created: Tue Sep  1 20:04:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_2.pxi.spice b/cells/einvn/sky130_fd_sc_hs__einvn_2.pxi.spice
index 516d285..c87597b 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_2.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_2.pxi.spice
-* Created: Thu Aug 27 20:44:50 2020
+* Created: Tue Sep  1 20:04:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVN_2%A_115_464# N_A_115_464#_M1009_d
 + N_A_115_464#_M1007_d N_A_115_464#_c_68_n N_A_115_464#_M1000_g

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_2.spice b/cells/einvn/sky130_fd_sc_hs__einvn_2.spice
index b6fb52a..016f902 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_2.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_2.spice
-* Created: Thu Aug 27 20:44:50 2020
+* Created: Tue Sep  1 20:04:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_4.lvs.report b/cells/einvn/sky130_fd_sc_hs__einvn_4.lvs.report
new file mode 100644
index 0000000..d8915ed
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_4.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvn_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvn_4.sp ('sky130_fd_sc_hs__einvn_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_4.spice ('sky130_fd_sc_hs__einvn_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvn_4      sky130_fd_sc_hs__einvn_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvn_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_4.pex.spice b/cells/einvn/sky130_fd_sc_hs__einvn_4.pex.spice
index 1f22b72..da84817 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_4.pex.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_4.pex.spice
-* Created: Thu Aug 27 20:44:58 2020
+* Created: Tue Sep  1 20:04:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_4.pxi.spice b/cells/einvn/sky130_fd_sc_hs__einvn_4.pxi.spice
index caaf322..50bc597 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_4.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_4.pxi.spice
-* Created: Thu Aug 27 20:44:58 2020
+* Created: Tue Sep  1 20:04:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVN_4%A_114_74# N_A_114_74#_M1014_d N_A_114_74#_M1000_d
 + N_A_114_74#_c_98_n N_A_114_74#_c_99_n N_A_114_74#_c_100_n N_A_114_74#_M1005_g

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_4.spice b/cells/einvn/sky130_fd_sc_hs__einvn_4.spice
index 200c815..34768ff 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_4.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_4.spice
-* Created: Thu Aug 27 20:44:58 2020
+* Created: Tue Sep  1 20:04:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_8.lvs.report b/cells/einvn/sky130_fd_sc_hs__einvn_8.lvs.report
new file mode 100644
index 0000000..c7663c9
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_8.lvs.report

@@ -0,0 +1,512 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvn_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvn_8.sp ('sky130_fd_sc_hs__einvn_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvn/sky130_fd_sc_hs__einvn_8.spice ('sky130_fd_sc_hs__einvn_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvn_8      sky130_fd_sc_hs__einvn_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvn_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvn_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   32 layout mos transistors were reduced to 4.
+     28 mos transistors were deleted by parallel reduction.
+   32 source mos transistors were reduced to 4.
+     28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_8.pex.spice b/cells/einvn/sky130_fd_sc_hs__einvn_8.pex.spice
index 3d5a813..bbba321 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_8.pex.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_8.pex.spice
-* Created: Thu Aug 27 20:45:06 2020
+* Created: Tue Sep  1 20:04:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_8.pxi.spice b/cells/einvn/sky130_fd_sc_hs__einvn_8.pxi.spice
index 42e64e5..ab51d3a 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_8.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_8.pxi.spice
-* Created: Thu Aug 27 20:45:06 2020
+* Created: Tue Sep  1 20:04:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVN_8%A_126_74# N_A_126_74#_M1001_d N_A_126_74#_M1014_d
 + N_A_126_74#_c_173_n N_A_126_74#_c_174_n N_A_126_74#_c_175_n

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_8.spice b/cells/einvn/sky130_fd_sc_hs__einvn_8.spice
index 4254457..9cb2869 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_8.spice
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvn_8.spice
-* Created: Thu Aug 27 20:45:06 2020
+* Created: Tue Sep  1 20:04:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_1.lvs.report b/cells/einvp/sky130_fd_sc_hs__einvp_1.lvs.report
new file mode 100644
index 0000000..36d65e5
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_1.lvs.report

@@ -0,0 +1,479 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvp_1.sp ('sky130_fd_sc_hs__einvp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_1.spice ('sky130_fd_sc_hs__einvp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:04:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvp_1      sky130_fd_sc_hs__einvp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_1.pex.spice b/cells/einvp/sky130_fd_sc_hs__einvp_1.pex.spice
index f6fed8d..bf62c75 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_1.pex.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_1.pex.spice
-* Created: Thu Aug 27 20:45:14 2020
+* Created: Tue Sep  1 20:04:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_1.pxi.spice b/cells/einvp/sky130_fd_sc_hs__einvp_1.pxi.spice
index 9c401a1..4110cb0 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_1.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_1.pxi.spice
-* Created: Thu Aug 27 20:45:14 2020
+* Created: Tue Sep  1 20:04:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVP_1%TE N_TE_c_51_n N_TE_M1000_g N_TE_M1003_g
 + N_TE_c_46_n N_TE_c_47_n N_TE_M1001_g TE TE N_TE_c_50_n

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_1.spice b/cells/einvp/sky130_fd_sc_hs__einvp_1.spice
index 398797d..d5bc45e 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_1.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_1.spice
-* Created: Thu Aug 27 20:45:14 2020
+* Created: Tue Sep  1 20:04:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_2.lvs.report b/cells/einvp/sky130_fd_sc_hs__einvp_2.lvs.report
new file mode 100644
index 0000000..b2a3999
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_2.lvs.report

@@ -0,0 +1,488 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvp_2.sp ('sky130_fd_sc_hs__einvp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_2.spice ('sky130_fd_sc_hs__einvp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvp_2      sky130_fd_sc_hs__einvp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_2.pex.spice b/cells/einvp/sky130_fd_sc_hs__einvp_2.pex.spice
index 4a16d16..ca57c6d 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_2.pex.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_2.pex.spice
-* Created: Thu Aug 27 20:45:24 2020
+* Created: Tue Sep  1 20:05:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_2.pxi.spice b/cells/einvp/sky130_fd_sc_hs__einvp_2.pxi.spice
index c4d3a0e..e365c3d 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_2.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_2.pxi.spice
-* Created: Thu Aug 27 20:45:24 2020
+* Created: Tue Sep  1 20:05:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVP_2%A N_A_c_75_n N_A_M1003_g N_A_c_71_n N_A_M1001_g
 + N_A_c_76_n N_A_M1005_g N_A_c_72_n N_A_M1009_g A N_A_c_74_n

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_2.spice b/cells/einvp/sky130_fd_sc_hs__einvp_2.spice
index 0d20d58..ca79f7b 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_2.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_2.spice
-* Created: Thu Aug 27 20:45:24 2020
+* Created: Tue Sep  1 20:05:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_4.lvs.report b/cells/einvp/sky130_fd_sc_hs__einvp_4.lvs.report
new file mode 100644
index 0000000..b4a3682
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_4.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvp_4.sp ('sky130_fd_sc_hs__einvp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_4.spice ('sky130_fd_sc_hs__einvp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvp_4      sky130_fd_sc_hs__einvp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_4.pex.spice b/cells/einvp/sky130_fd_sc_hs__einvp_4.pex.spice
index 10d7839..9d5dd1c 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_4.pex.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_4.pex.spice
-* Created: Thu Aug 27 20:45:31 2020
+* Created: Tue Sep  1 20:05:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_4.pxi.spice b/cells/einvp/sky130_fd_sc_hs__einvp_4.pxi.spice
index ac790bd..384cd3b 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_4.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_4.pxi.spice
-* Created: Thu Aug 27 20:45:31 2020
+* Created: Tue Sep  1 20:05:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVP_4%A N_A_M1002_g N_A_c_120_n N_A_M1003_g N_A_M1004_g
 + N_A_c_121_n N_A_M1006_g N_A_c_122_n N_A_M1007_g N_A_M1013_g N_A_c_114_n

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_4.spice b/cells/einvp/sky130_fd_sc_hs__einvp_4.spice
index 5df0125..2930d61 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_4.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_4.spice
-* Created: Thu Aug 27 20:45:31 2020
+* Created: Tue Sep  1 20:05:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_8.lvs.report b/cells/einvp/sky130_fd_sc_hs__einvp_8.lvs.report
new file mode 100644
index 0000000..0c591da
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_8.lvs.report

@@ -0,0 +1,512 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__einvp_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__einvp_8.sp ('sky130_fd_sc_hs__einvp_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/einvp/sky130_fd_sc_hs__einvp_8.spice ('sky130_fd_sc_hs__einvp_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__einvp_8      sky130_fd_sc_hs__einvp_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__einvp_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__einvp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   32 layout mos transistors were reduced to 4.
+     28 mos transistors were deleted by parallel reduction.
+   32 source mos transistors were reduced to 4.
+     28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_8.pex.spice b/cells/einvp/sky130_fd_sc_hs__einvp_8.pex.spice
index d4a0eae..941311a 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_8.pex.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_8.pex.spice
-* Created: Thu Aug 27 20:45:39 2020
+* Created: Tue Sep  1 20:05:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_8.pxi.spice b/cells/einvp/sky130_fd_sc_hs__einvp_8.pxi.spice
index a680b40..b5e36c4 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_8.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_8.pxi.spice
-* Created: Thu Aug 27 20:45:39 2020
+* Created: Tue Sep  1 20:05:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__EINVP_8%A N_A_c_177_n N_A_M1009_g N_A_c_187_n N_A_M1001_g
 + N_A_c_178_n N_A_M1011_g N_A_c_188_n N_A_M1003_g N_A_c_189_n N_A_M1005_g

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_8.spice b/cells/einvp/sky130_fd_sc_hs__einvp_8.spice
index ac23207..f7e48ce 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_8.spice
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__einvp_8.spice
-* Created: Thu Aug 27 20:45:39 2020
+* Created: Tue Sep  1 20:05:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fa/sky130_fd_sc_hs__fa_1.lvs.report b/cells/fa/sky130_fd_sc_hs__fa_1.lvs.report
new file mode 100644
index 0000000..86614fc
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_hs__fa_1.lvs.report

@@ -0,0 +1,513 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fa_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fa_1.sp ('sky130_fd_sc_hs__fa_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_1.spice ('sky130_fd_sc_hs__fa_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fa_1         sky130_fd_sc_hs__fa_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fa_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__fa_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              21        21
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:        12        12
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_2_1
+                        1          1            0            0    SPMN_3_1
+                        1          1            0            0    SPMP_2_1
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:         12         12            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A CIN B SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fa/sky130_fd_sc_hs__fa_1.pex.spice b/cells/fa/sky130_fd_sc_hs__fa_1.pex.spice
index 0db7485..8058b69 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_1.pex.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_1.pex.spice
-* Created: Thu Aug 27 20:45:46 2020
+* Created: Tue Sep  1 20:05:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fa/sky130_fd_sc_hs__fa_1.pxi.spice b/cells/fa/sky130_fd_sc_hs__fa_1.pxi.spice
index a7647a9..ebccadd 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_1.pxi.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_1.pxi.spice
-* Created: Thu Aug 27 20:45:46 2020
+* Created: Tue Sep  1 20:05:20 2020
 * 
 x_PM_SKY130_FD_SC_HS__FA_1%A_69_260# N_A_69_260#_M1003_d N_A_69_260#_M1013_d
 + N_A_69_260#_M1027_g N_A_69_260#_c_158_n N_A_69_260#_M1006_g

diff --git a/cells/fa/sky130_fd_sc_hs__fa_1.spice b/cells/fa/sky130_fd_sc_hs__fa_1.spice
index e9a45ab..469db63 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_1.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_1.spice
-* Created: Thu Aug 27 20:45:46 2020
+* Created: Tue Sep  1 20:05:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fa/sky130_fd_sc_hs__fa_2.lvs.report b/cells/fa/sky130_fd_sc_hs__fa_2.lvs.report
new file mode 100644
index 0000000..c36b738
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_hs__fa_2.lvs.report

@@ -0,0 +1,522 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fa_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fa_2.sp ('sky130_fd_sc_hs__fa_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_2.spice ('sky130_fd_sc_hs__fa_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fa_2         sky130_fd_sc_hs__fa_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fa_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__fa_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              21        21
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:        12        12
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_2_1
+                        1          1            0            0    SPMN_3_1
+                        1          1            0            0    SPMP_2_1
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:         12         12            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A CIN B VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fa/sky130_fd_sc_hs__fa_2.pex.spice b/cells/fa/sky130_fd_sc_hs__fa_2.pex.spice
index 872d429..c6c0edb 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_2.pex.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_2.pex.spice
-* Created: Thu Aug 27 20:45:54 2020
+* Created: Tue Sep  1 20:05:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fa/sky130_fd_sc_hs__fa_2.pxi.spice b/cells/fa/sky130_fd_sc_hs__fa_2.pxi.spice
index 9c54e0c..0d169f6 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_2.pxi.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_2.pxi.spice
-* Created: Thu Aug 27 20:45:54 2020
+* Created: Tue Sep  1 20:05:26 2020
 * 
 x_PM_SKY130_FD_SC_HS__FA_2%A N_A_M1017_g N_A_c_172_n N_A_M1019_g N_A_c_173_n
 + N_A_M1023_g N_A_c_174_n N_A_M1000_g N_A_c_175_n N_A_M1003_g N_A_c_176_n

diff --git a/cells/fa/sky130_fd_sc_hs__fa_2.spice b/cells/fa/sky130_fd_sc_hs__fa_2.spice
index 2cb3c0a..6076a25 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_2.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_2.spice
-* Created: Thu Aug 27 20:45:54 2020
+* Created: Tue Sep  1 20:05:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fa/sky130_fd_sc_hs__fa_4.lvs.report b/cells/fa/sky130_fd_sc_hs__fa_4.lvs.report
new file mode 100644
index 0000000..d8e9da1
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_hs__fa_4.lvs.report

@@ -0,0 +1,530 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fa_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fa_4.sp ('sky130_fd_sc_hs__fa_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fa/sky130_fd_sc_hs__fa_4.spice ('sky130_fd_sc_hs__fa_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fa_4         sky130_fd_sc_hs__fa_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fa_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__fa_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              21        21
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                     1         1         SPMP_3_1 (6 pins)
+                ------    ------
+ Total Inst:        12        12
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMN3
+                        1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_2_1
+                        1          1            0            0    SPMN_3_1
+                        1          1            0            0    SPMP_2_1
+                        1          1            0            0    SPMP_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:         12         12            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B CIN A VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fa/sky130_fd_sc_hs__fa_4.pex.spice b/cells/fa/sky130_fd_sc_hs__fa_4.pex.spice
index 3d1225f..03ff432 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_4.pex.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_4.pex.spice
-* Created: Thu Aug 27 20:46:01 2020
+* Created: Tue Sep  1 20:05:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fa/sky130_fd_sc_hs__fa_4.pxi.spice b/cells/fa/sky130_fd_sc_hs__fa_4.pxi.spice
index dd2debb..b19b1ce 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_4.pxi.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_4.pxi.spice
-* Created: Thu Aug 27 20:46:01 2020
+* Created: Tue Sep  1 20:05:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__FA_4%B N_B_c_204_n N_B_M1023_g N_B_M1025_g N_B_M1019_g
 + N_B_c_195_n N_B_M1002_g N_B_M1027_g N_B_c_197_n N_B_M1021_g N_B_c_198_n

diff --git a/cells/fa/sky130_fd_sc_hs__fa_4.spice b/cells/fa/sky130_fd_sc_hs__fa_4.spice
index fc71899..65b40e3 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_4.spice
+++ b/cells/fa/sky130_fd_sc_hs__fa_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fa_4.spice
-* Created: Thu Aug 27 20:46:01 2020
+* Created: Tue Sep  1 20:05:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fah/sky130_fd_sc_hs__fah_1.lvs.report b/cells/fah/sky130_fd_sc_hs__fah_1.lvs.report
new file mode 100644
index 0000000..ff08705
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_hs__fah_1.lvs.report

@@ -0,0 +1,501 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fah_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fah_1.sp ('sky130_fd_sc_hs__fah_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_1.spice ('sky130_fd_sc_hs__fah_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fah_1        sky130_fd_sc_hs__fah_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fah_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__fah_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          16         16            0            0    MN(NLOWVT)
+                       16         16            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB CI B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fah/sky130_fd_sc_hs__fah_1.pex.spice b/cells/fah/sky130_fd_sc_hs__fah_1.pex.spice
index a506be1..2e7e738 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_1.pex.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_1.pex.spice
-* Created: Thu Aug 27 20:46:10 2020
+* Created: Tue Sep  1 20:05:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fah/sky130_fd_sc_hs__fah_1.pxi.spice b/cells/fah/sky130_fd_sc_hs__fah_1.pxi.spice
index e2ac446..63acdb7 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_1.pxi.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_1.pxi.spice
-* Created: Thu Aug 27 20:46:10 2020
+* Created: Tue Sep  1 20:05:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__FAH_1%CI N_CI_c_284_n N_CI_M1010_g N_CI_c_285_n
 + N_CI_M1022_g CI N_CI_c_286_n PM_SKY130_FD_SC_HS__FAH_1%CI

diff --git a/cells/fah/sky130_fd_sc_hs__fah_1.spice b/cells/fah/sky130_fd_sc_hs__fah_1.spice
index de2f3c9..4efd959 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_1.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_1.spice
-* Created: Thu Aug 27 20:46:10 2020
+* Created: Tue Sep  1 20:05:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fah/sky130_fd_sc_hs__fah_2.lvs.report b/cells/fah/sky130_fd_sc_hs__fah_2.lvs.report
new file mode 100644
index 0000000..4cdfc73
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_hs__fah_2.lvs.report

@@ -0,0 +1,510 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fah_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fah_2.sp ('sky130_fd_sc_hs__fah_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_2.spice ('sky130_fd_sc_hs__fah_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fah_2        sky130_fd_sc_hs__fah_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fah_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__fah_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         18        18         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        37        36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          16         16            0            0    MN(NLOWVT)
+                       16         16            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B CI VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fah/sky130_fd_sc_hs__fah_2.pex.spice b/cells/fah/sky130_fd_sc_hs__fah_2.pex.spice
index fc9959f..90b0ce6 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_2.pex.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_2.pex.spice
-* Created: Thu Aug 27 20:46:17 2020
+* Created: Tue Sep  1 20:05:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fah/sky130_fd_sc_hs__fah_2.pxi.spice b/cells/fah/sky130_fd_sc_hs__fah_2.pxi.spice
index d415513..7f9595f 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_2.pxi.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_2.pxi.spice
-* Created: Thu Aug 27 20:46:17 2020
+* Created: Tue Sep  1 20:05:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__FAH_2%A_81_260# N_A_81_260#_M1017_s N_A_81_260#_M1015_s
 + N_A_81_260#_c_258_n N_A_81_260#_M1002_g N_A_81_260#_M1034_g

diff --git a/cells/fah/sky130_fd_sc_hs__fah_2.spice b/cells/fah/sky130_fd_sc_hs__fah_2.spice
index 8fd535f..7516e27 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_2.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_2.spice
-* Created: Thu Aug 27 20:46:17 2020
+* Created: Tue Sep  1 20:05:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fah/sky130_fd_sc_hs__fah_4.lvs.report b/cells/fah/sky130_fd_sc_hs__fah_4.lvs.report
new file mode 100644
index 0000000..903a28a
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_hs__fah_4.lvs.report

@@ -0,0 +1,518 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 99 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 101 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 103 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 105 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fah_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fah_4.sp ('sky130_fd_sc_hs__fah_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fah/sky130_fd_sc_hs__fah_4.spice ('sky130_fd_sc_hs__fah_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fah_4        sky130_fd_sc_hs__fah_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fah_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__fah_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         22        22         MN (4 pins)
+                    22        22         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        45        44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          16         16            0            0    MN(NLOWVT)
+                       16         16            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 4.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B CI VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fah/sky130_fd_sc_hs__fah_4.pex.spice b/cells/fah/sky130_fd_sc_hs__fah_4.pex.spice
index 9673146..fd92df0 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_4.pex.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_4.pex.spice
-* Created: Thu Aug 27 20:46:28 2020
+* Created: Tue Sep  1 20:05:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fah/sky130_fd_sc_hs__fah_4.pxi.spice b/cells/fah/sky130_fd_sc_hs__fah_4.pxi.spice
index 5e034bb..9df7f47 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_4.pxi.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_4.pxi.spice
-* Created: Thu Aug 27 20:46:28 2020
+* Created: Tue Sep  1 20:05:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__FAH_4%A N_A_M1038_g N_A_c_309_n N_A_M1011_g N_A_M1039_g
 + N_A_c_310_n N_A_M1012_g A N_A_c_307_n N_A_c_308_n PM_SKY130_FD_SC_HS__FAH_4%A

diff --git a/cells/fah/sky130_fd_sc_hs__fah_4.spice b/cells/fah/sky130_fd_sc_hs__fah_4.spice
index c0d42b0..2c22df8 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_4.spice
+++ b/cells/fah/sky130_fd_sc_hs__fah_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fah_4.spice
-* Created: Thu Aug 27 20:46:28 2020
+* Created: Tue Sep  1 20:05:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.lvs.report b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.lvs.report
new file mode 100644
index 0000000..67296e6
--- /dev/null
+++ b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.lvs.report

@@ -0,0 +1,501 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fahcin_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fahcin_1.sp ('sky130_fd_sc_hs__fahcin_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice ('sky130_fd_sc_hs__fahcin_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:05:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fahcin_1     sky130_fd_sc_hs__fahcin_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fahcin_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__fahcin_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          16         16            0            0    MN(NLOWVT)
+                       16         16            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B CIN VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pex.spice b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pex.spice
index 2b88834..ac63069 100644
--- a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pex.spice
+++ b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fahcin_1.pex.spice
-* Created: Thu Aug 27 20:46:36 2020
+* Created: Tue Sep  1 20:05:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pxi.spice b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pxi.spice
index 7a028d7..93b31fe 100644
--- a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pxi.spice
+++ b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fahcin_1.pxi.spice
-* Created: Thu Aug 27 20:46:36 2020
+* Created: Tue Sep  1 20:05:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__FAHCIN_1%A N_A_M1017_g N_A_c_238_n N_A_M1005_g A
 + N_A_c_239_n PM_SKY130_FD_SC_HS__FAHCIN_1%A

diff --git a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice
index 2f397b8..de184b5 100644
--- a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice
+++ b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fahcin_1.spice
-* Created: Thu Aug 27 20:46:36 2020
+* Created: Tue Sep  1 20:05:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.lvs.report b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.lvs.report
new file mode 100644
index 0000000..15fa459
--- /dev/null
+++ b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.lvs.report

@@ -0,0 +1,501 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fahcon_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fahcon_1.sp ('sky130_fd_sc_hs__fahcon_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice ('sky130_fd_sc_hs__fahcon_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__fahcon_1     sky130_fd_sc_hs__fahcon_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__fahcon_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__fahcon_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              19        19
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          16         16            0            0    MN(NLOWVT)
+                       16         16            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B CI VPWR COUT_N SUM VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pex.spice b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pex.spice
index 5962046..ccbdc00 100644
--- a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pex.spice
+++ b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fahcon_1.pex.spice
-* Created: Thu Aug 27 20:46:43 2020
+* Created: Tue Sep  1 20:06:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pxi.spice b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pxi.spice
index 6636eea..974c9b0 100644
--- a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pxi.spice
+++ b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fahcon_1.pxi.spice
-* Created: Thu Aug 27 20:46:43 2020
+* Created: Tue Sep  1 20:06:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__FAHCON_1%A N_A_c_227_n N_A_M1013_g N_A_c_228_n N_A_M1030_g
 + A PM_SKY130_FD_SC_HS__FAHCON_1%A

diff --git a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice
index dba5d28..740cb98 100644
--- a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice
+++ b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__fahcon_1.spice
-* Created: Thu Aug 27 20:46:43 2020
+* Created: Tue Sep  1 20:06:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/fill/sky130_fd_sc_hs__fill_1.lvs.report b/cells/fill/sky130_fd_sc_hs__fill_1.lvs.report
new file mode 100644
index 0000000..b1d4815
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hs__fill_1.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_1.sp ('sky130_fd_sc_hs__fill_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill/sky130_fd_sc_hs__fill_1.spice ('sky130_fd_sc_hs__fill_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fill/sky130_fd_sc_hs__fill_2.lvs.report b/cells/fill/sky130_fd_sc_hs__fill_2.lvs.report
new file mode 100644
index 0000000..4ff656c
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hs__fill_2.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_2.sp ('sky130_fd_sc_hs__fill_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill/sky130_fd_sc_hs__fill_2.spice ('sky130_fd_sc_hs__fill_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fill/sky130_fd_sc_hs__fill_4.lvs.report b/cells/fill/sky130_fd_sc_hs__fill_4.lvs.report
new file mode 100644
index 0000000..f56ce8a
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hs__fill_4.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_4.sp ('sky130_fd_sc_hs__fill_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill/sky130_fd_sc_hs__fill_4.spice ('sky130_fd_sc_hs__fill_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fill/sky130_fd_sc_hs__fill_8.lvs.report b/cells/fill/sky130_fd_sc_hs__fill_8.lvs.report
new file mode 100644
index 0000000..d9307e0
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_hs__fill_8.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_8.sp ('sky130_fd_sc_hs__fill_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill/sky130_fd_sc_hs__fill_8.spice ('sky130_fd_sc_hs__fill_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.lvs.report b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.lvs.report
new file mode 100644
index 0000000..bcba335
--- /dev/null
+++ b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_diode_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_diode_2.sp ('sky130_fd_sc_hs__fill_diode_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.spice ('sky130_fd_sc_hs__fill_diode_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.lvs.report b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.lvs.report
new file mode 100644
index 0000000..b22d1ad
--- /dev/null
+++ b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_diode_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_diode_4.sp ('sky130_fd_sc_hs__fill_diode_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.spice ('sky130_fd_sc_hs__fill_diode_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.lvs.report b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.lvs.report
new file mode 100644
index 0000000..053fed8
--- /dev/null
+++ b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__fill_diode_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__fill_diode_8.sp ('sky130_fd_sc_hs__fill_diode_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.spice ('sky130_fd_sc_hs__fill_diode_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:23 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ha/sky130_fd_sc_hs__ha_1.lvs.report b/cells/ha/sky130_fd_sc_hs__ha_1.lvs.report
new file mode 100644
index 0000000..c59f4b3
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_hs__ha_1.lvs.report

@@ -0,0 +1,489 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ha_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ha_1.sp ('sky130_fd_sc_hs__ha_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_1.spice ('sky130_fd_sc_hs__ha_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ha_1         sky130_fd_sc_hs__ha_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ha_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__ha_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        10        10
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         10         10            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ha/sky130_fd_sc_hs__ha_1.pex.spice b/cells/ha/sky130_fd_sc_hs__ha_1.pex.spice
index c72641c..e03fe02 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_1.pex.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_1.pex.spice
-* Created: Thu Aug 27 20:47:15 2020
+* Created: Tue Sep  1 20:06:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ha/sky130_fd_sc_hs__ha_1.pxi.spice b/cells/ha/sky130_fd_sc_hs__ha_1.pxi.spice
index 073b166..f84bf4c 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_1.pxi.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_1.pxi.spice
-* Created: Thu Aug 27 20:47:15 2020
+* Created: Tue Sep  1 20:06:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__HA_1%A_83_260# N_A_83_260#_M1009_s N_A_83_260#_M1007_d
 + N_A_83_260#_M1012_g N_A_83_260#_c_89_n N_A_83_260#_M1006_g N_A_83_260#_c_90_n

diff --git a/cells/ha/sky130_fd_sc_hs__ha_1.spice b/cells/ha/sky130_fd_sc_hs__ha_1.spice
index 4b200b8..3b21315 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_1.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_1.spice
-* Created: Thu Aug 27 20:47:15 2020
+* Created: Tue Sep  1 20:06:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/ha/sky130_fd_sc_hs__ha_2.lvs.report b/cells/ha/sky130_fd_sc_hs__ha_2.lvs.report
new file mode 100644
index 0000000..78e338a
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_hs__ha_2.lvs.report

@@ -0,0 +1,498 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ha_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ha_2.sp ('sky130_fd_sc_hs__ha_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_2.spice ('sky130_fd_sc_hs__ha_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ha_2         sky130_fd_sc_hs__ha_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ha_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__ha_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        10        10
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         10         10            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ha/sky130_fd_sc_hs__ha_2.pex.spice b/cells/ha/sky130_fd_sc_hs__ha_2.pex.spice
index 24492f1..755595e 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_2.pex.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_2.pex.spice
-* Created: Thu Aug 27 20:47:23 2020
+* Created: Tue Sep  1 20:06:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ha/sky130_fd_sc_hs__ha_2.pxi.spice b/cells/ha/sky130_fd_sc_hs__ha_2.pxi.spice
index cbe97ec..4006590 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_2.pxi.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_2.pxi.spice
-* Created: Thu Aug 27 20:47:23 2020
+* Created: Tue Sep  1 20:06:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__HA_2%B N_B_M1015_g N_B_M1002_g N_B_c_103_n N_B_M1007_g
 + N_B_c_104_n N_B_M1005_g N_B_c_105_n N_B_c_112_n N_B_c_106_n N_B_c_107_n

diff --git a/cells/ha/sky130_fd_sc_hs__ha_2.spice b/cells/ha/sky130_fd_sc_hs__ha_2.spice
index d43e8d7..4498e6c 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_2.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_2.spice
-* Created: Thu Aug 27 20:47:23 2020
+* Created: Tue Sep  1 20:06:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/ha/sky130_fd_sc_hs__ha_4.lvs.report b/cells/ha/sky130_fd_sc_hs__ha_4.lvs.report
new file mode 100644
index 0000000..5e42e46
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_hs__ha_4.lvs.report

@@ -0,0 +1,516 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__ha_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__ha_4.sp ('sky130_fd_sc_hs__ha_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/ha/sky130_fd_sc_hs__ha_4.spice ('sky130_fd_sc_hs__ha_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__ha_4         sky130_fd_sc_hs__ha_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__ha_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__ha_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:         18        18         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        37        36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        10        10
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         10         10            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   36 layout mos transistors were reduced to 14.
+     22 mos transistors were deleted by parallel reduction.
+   36 source mos transistors were reduced to 14.
+     22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/ha/sky130_fd_sc_hs__ha_4.pex.spice b/cells/ha/sky130_fd_sc_hs__ha_4.pex.spice
index b2a9698..aeeba8a 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_4.pex.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_4.pex.spice
-* Created: Thu Aug 27 20:47:33 2020
+* Created: Tue Sep  1 20:06:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/ha/sky130_fd_sc_hs__ha_4.pxi.spice b/cells/ha/sky130_fd_sc_hs__ha_4.pxi.spice
index 686fe99..84464c4 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_4.pxi.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_4.pxi.spice
-* Created: Thu Aug 27 20:47:33 2020
+* Created: Tue Sep  1 20:06:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__HA_4%A_435_99# N_A_435_99#_M1002_d N_A_435_99#_M1000_s
 + N_A_435_99#_M1003_d N_A_435_99#_c_195_n N_A_435_99#_M1023_g

diff --git a/cells/ha/sky130_fd_sc_hs__ha_4.spice b/cells/ha/sky130_fd_sc_hs__ha_4.spice
index abc38ac..15060f8 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_4.spice
+++ b/cells/ha/sky130_fd_sc_hs__ha_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__ha_4.spice
-* Created: Thu Aug 27 20:47:33 2020
+* Created: Tue Sep  1 20:06:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/inv/sky130_fd_sc_hs__inv_1.lvs.report b/cells/inv/sky130_fd_sc_hs__inv_1.lvs.report
new file mode 100644
index 0000000..ebf6f18
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hs__inv_1.lvs.report

@@ -0,0 +1,471 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__inv_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__inv_1.sp ('sky130_fd_sc_hs__inv_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_1.spice ('sky130_fd_sc_hs__inv_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__inv_1        sky130_fd_sc_hs__inv_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__inv_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__inv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         3         2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/inv/sky130_fd_sc_hs__inv_1.pex.spice b/cells/inv/sky130_fd_sc_hs__inv_1.pex.spice
index 5a97d2b..26765e0 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_1.pex.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_1.pex.spice
-* Created: Thu Aug 27 20:47:49 2020
+* Created: Tue Sep  1 20:06:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/inv/sky130_fd_sc_hs__inv_1.pxi.spice b/cells/inv/sky130_fd_sc_hs__inv_1.pxi.spice
index c441ced..fe6edd1 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_1.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_1.pxi.spice
-* Created: Thu Aug 27 20:47:49 2020
+* Created: Tue Sep  1 20:06:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__INV_1%A N_A_c_25_n N_A_M1000_g N_A_M1001_g N_A_c_22_n
 + N_A_c_23_n A N_A_c_24_n PM_SKY130_FD_SC_HS__INV_1%A

diff --git a/cells/inv/sky130_fd_sc_hs__inv_1.spice b/cells/inv/sky130_fd_sc_hs__inv_1.spice
index e03bf10..46bbcf1 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_1.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_1.spice
-* Created: Thu Aug 27 20:47:49 2020
+* Created: Tue Sep  1 20:06:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/inv/sky130_fd_sc_hs__inv_16.lvs.report b/cells/inv/sky130_fd_sc_hs__inv_16.lvs.report
new file mode 100644
index 0000000..c65f77b
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hs__inv_16.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__inv_16.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__inv_16.sp ('sky130_fd_sc_hs__inv_16')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_16.spice ('sky130_fd_sc_hs__inv_16')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__inv_16       sky130_fd_sc_hs__inv_16
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__inv_16
+SOURCE CELL NAME:         sky130_fd_sc_hs__inv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   32 layout mos transistors were reduced to 2.
+     30 mos transistors were deleted by parallel reduction.
+   32 source mos transistors were reduced to 2.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/inv/sky130_fd_sc_hs__inv_16.pex.spice b/cells/inv/sky130_fd_sc_hs__inv_16.pex.spice
index 780c795..bad4761 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_16.pex.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_16.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_16.pex.spice
-* Created: Thu Aug 27 20:47:41 2020
+* Created: Tue Sep  1 20:06:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/inv/sky130_fd_sc_hs__inv_16.pxi.spice b/cells/inv/sky130_fd_sc_hs__inv_16.pxi.spice
index 3aad421..3e07c3d 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_16.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_16.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_16.pxi.spice
-* Created: Thu Aug 27 20:47:41 2020
+* Created: Tue Sep  1 20:06:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__INV_16%A N_A_c_161_n N_A_M1000_g N_A_M1002_g N_A_c_162_n
 + N_A_M1001_g N_A_M1004_g N_A_c_163_n N_A_M1003_g N_A_M1005_g N_A_c_164_n

diff --git a/cells/inv/sky130_fd_sc_hs__inv_16.spice b/cells/inv/sky130_fd_sc_hs__inv_16.spice
index 9813b3f..bbf83f3 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_16.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_16.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_16.spice
-* Created: Thu Aug 27 20:47:41 2020
+* Created: Tue Sep  1 20:06:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/inv/sky130_fd_sc_hs__inv_2.lvs.report b/cells/inv/sky130_fd_sc_hs__inv_2.lvs.report
new file mode 100644
index 0000000..843675c
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hs__inv_2.lvs.report

@@ -0,0 +1,478 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__inv_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__inv_2.sp ('sky130_fd_sc_hs__inv_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_2.spice ('sky130_fd_sc_hs__inv_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:06:56 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__inv_2        sky130_fd_sc_hs__inv_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__inv_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__inv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         5         4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/inv/sky130_fd_sc_hs__inv_2.pex.spice b/cells/inv/sky130_fd_sc_hs__inv_2.pex.spice
index 8049377..b05f830 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_2.pex.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_2.pex.spice
-* Created: Thu Aug 27 20:47:56 2020
+* Created: Tue Sep  1 20:06:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/inv/sky130_fd_sc_hs__inv_2.pxi.spice b/cells/inv/sky130_fd_sc_hs__inv_2.pxi.spice
index 9c11ceb..569fe38 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_2.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_2.pxi.spice
-* Created: Thu Aug 27 20:47:56 2020
+* Created: Tue Sep  1 20:06:59 2020
 * 
 x_PM_SKY130_FD_SC_HS__INV_2%A N_A_c_29_n N_A_M1000_g N_A_M1002_g N_A_c_31_n
 + N_A_c_32_n N_A_M1003_g N_A_c_38_n N_A_M1001_g N_A_c_34_n A N_A_c_35_n

diff --git a/cells/inv/sky130_fd_sc_hs__inv_2.spice b/cells/inv/sky130_fd_sc_hs__inv_2.spice
index c267cd3..f126725 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_2.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_2.spice
-* Created: Thu Aug 27 20:47:56 2020
+* Created: Tue Sep  1 20:06:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/inv/sky130_fd_sc_hs__inv_4.lvs.report b/cells/inv/sky130_fd_sc_hs__inv_4.lvs.report
new file mode 100644
index 0000000..8957ee1
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hs__inv_4.lvs.report

@@ -0,0 +1,482 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__inv_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__inv_4.sp ('sky130_fd_sc_hs__inv_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_4.spice ('sky130_fd_sc_hs__inv_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:02 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__inv_4        sky130_fd_sc_hs__inv_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__inv_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__inv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/inv/sky130_fd_sc_hs__inv_4.pex.spice b/cells/inv/sky130_fd_sc_hs__inv_4.pex.spice
index cdd2943..2db91d6 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_4.pex.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_4.pex.spice
-* Created: Thu Aug 27 20:48:03 2020
+* Created: Tue Sep  1 20:07:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/inv/sky130_fd_sc_hs__inv_4.pxi.spice b/cells/inv/sky130_fd_sc_hs__inv_4.pxi.spice
index e22f623..56989c8 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_4.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_4.pxi.spice
-* Created: Thu Aug 27 20:48:03 2020
+* Created: Tue Sep  1 20:07:05 2020
 * 
 x_PM_SKY130_FD_SC_HS__INV_4%A N_A_M1000_g N_A_c_49_n N_A_M1001_g N_A_c_50_n
 + N_A_M1002_g N_A_M1005_g N_A_c_51_n N_A_M1003_g N_A_M1006_g N_A_c_52_n

diff --git a/cells/inv/sky130_fd_sc_hs__inv_4.spice b/cells/inv/sky130_fd_sc_hs__inv_4.spice
index 6ade8f4..dc8872f 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_4.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_4.spice
-* Created: Thu Aug 27 20:48:03 2020
+* Created: Tue Sep  1 20:07:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/inv/sky130_fd_sc_hs__inv_8.lvs.report b/cells/inv/sky130_fd_sc_hs__inv_8.lvs.report
new file mode 100644
index 0000000..5c990e7
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_hs__inv_8.lvs.report

@@ -0,0 +1,490 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__inv_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__inv_8.sp ('sky130_fd_sc_hs__inv_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/inv/sky130_fd_sc_hs__inv_8.spice ('sky130_fd_sc_hs__inv_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:08 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__inv_8        sky130_fd_sc_hs__inv_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__inv_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__inv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              6         6
+
+ Nets:               6         6
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                ------    ------
+ Total Inst:         2         2
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               6          6            0            0
+
+   Nets:                6          6            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:          2          2            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 2.
+     14 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 2.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/inv/sky130_fd_sc_hs__inv_8.pex.spice b/cells/inv/sky130_fd_sc_hs__inv_8.pex.spice
index d46cf93..7a3bc32 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_8.pex.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_8.pex.spice
-* Created: Thu Aug 27 20:48:11 2020
+* Created: Tue Sep  1 20:07:11 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/inv/sky130_fd_sc_hs__inv_8.pxi.spice b/cells/inv/sky130_fd_sc_hs__inv_8.pxi.spice
index cbd961e..429b012 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_8.pxi.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_8.pxi.spice
-* Created: Thu Aug 27 20:48:11 2020
+* Created: Tue Sep  1 20:07:11 2020
 * 
 x_PM_SKY130_FD_SC_HS__INV_8%A N_A_c_77_n N_A_M1002_g N_A_c_68_n N_A_M1000_g
 + N_A_c_69_n N_A_M1001_g N_A_c_78_n N_A_M1003_g N_A_M1004_g N_A_c_79_n

diff --git a/cells/inv/sky130_fd_sc_hs__inv_8.spice b/cells/inv/sky130_fd_sc_hs__inv_8.spice
index 8c6fd55..58c1b49 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_8.spice
+++ b/cells/inv/sky130_fd_sc_hs__inv_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__inv_8.spice
-* Created: Thu Aug 27 20:48:11 2020
+* Created: Tue Sep  1 20:07:11 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_1.lvs.report b/cells/maj3/sky130_fd_sc_hs__maj3_1.lvs.report
new file mode 100644
index 0000000..a8065d4
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_1.lvs.report

@@ -0,0 +1,487 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__maj3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__maj3_1.sp ('sky130_fd_sc_hs__maj3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_1.spice ('sky130_fd_sc_hs__maj3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:14 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__maj3_1       sky130_fd_sc_hs__maj3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__maj3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__maj3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B C A X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_1.pex.spice b/cells/maj3/sky130_fd_sc_hs__maj3_1.pex.spice
index 160e4df..54b2375 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_1.pex.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_1.pex.spice
-* Created: Thu Aug 27 20:48:20 2020
+* Created: Tue Sep  1 20:07:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_1.pxi.spice b/cells/maj3/sky130_fd_sc_hs__maj3_1.pxi.spice
index e211a27..8f632dd 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_1.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_1.pxi.spice
-* Created: Thu Aug 27 20:48:20 2020
+* Created: Tue Sep  1 20:07:17 2020
 * 
 x_PM_SKY130_FD_SC_HS__MAJ3_1%A_84_74# N_A_84_74#_M1004_d N_A_84_74#_M1010_d
 + N_A_84_74#_M1002_d N_A_84_74#_M1001_d N_A_84_74#_c_69_n N_A_84_74#_M1003_g

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_1.spice b/cells/maj3/sky130_fd_sc_hs__maj3_1.spice
index 690d575..6ccfead 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_1.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_1.spice
-* Created: Thu Aug 27 20:48:20 2020
+* Created: Tue Sep  1 20:07:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_2.lvs.report b/cells/maj3/sky130_fd_sc_hs__maj3_2.lvs.report
new file mode 100644
index 0000000..3d45adf
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_2.lvs.report

@@ -0,0 +1,494 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__maj3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__maj3_2.sp ('sky130_fd_sc_hs__maj3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_2.spice ('sky130_fd_sc_hs__maj3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__maj3_2       sky130_fd_sc_hs__maj3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__maj3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__maj3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B C A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_2.pex.spice b/cells/maj3/sky130_fd_sc_hs__maj3_2.pex.spice
index 4dc70ee..2705fd7 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_2.pex.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_2.pex.spice
-* Created: Thu Aug 27 20:48:27 2020
+* Created: Tue Sep  1 20:07:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_2.pxi.spice b/cells/maj3/sky130_fd_sc_hs__maj3_2.pxi.spice
index 873b4e7..5cd847e 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_2.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_2.pxi.spice
-* Created: Thu Aug 27 20:48:27 2020
+* Created: Tue Sep  1 20:07:23 2020
 * 
 x_PM_SKY130_FD_SC_HS__MAJ3_2%A_87_264# N_A_87_264#_M1007_d N_A_87_264#_M1010_d
 + N_A_87_264#_M1012_d N_A_87_264#_M1002_d N_A_87_264#_M1008_g N_A_87_264#_c_85_n

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_2.spice b/cells/maj3/sky130_fd_sc_hs__maj3_2.spice
index 3c7be63..31653b9 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_2.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_2.spice
-* Created: Thu Aug 27 20:48:27 2020
+* Created: Tue Sep  1 20:07:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_4.lvs.report b/cells/maj3/sky130_fd_sc_hs__maj3_4.lvs.report
new file mode 100644
index 0000000..f9c1fcd
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_4.lvs.report

@@ -0,0 +1,510 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__maj3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__maj3_4.sp ('sky130_fd_sc_hs__maj3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/maj3/sky130_fd_sc_hs__maj3_4.spice ('sky130_fd_sc_hs__maj3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__maj3_4       sky130_fd_sc_hs__maj3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__maj3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__maj3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     3         3         SMN2 (4 pins)
+                     3         3         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        3          3            0            0    SMN2
+                        3          3            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   32 layout mos transistors were reduced to 14.
+     18 mos transistors were deleted by parallel reduction.
+   32 source mos transistors were reduced to 14.
+     18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_4.pex.spice b/cells/maj3/sky130_fd_sc_hs__maj3_4.pex.spice
index 8c3c340..344542f 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_4.pex.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_4.pex.spice
-* Created: Thu Aug 27 20:48:38 2020
+* Created: Tue Sep  1 20:07:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_4.pxi.spice b/cells/maj3/sky130_fd_sc_hs__maj3_4.pxi.spice
index 7ee7d1c..93bdd06 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_4.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_4.pxi.spice
-* Created: Thu Aug 27 20:48:38 2020
+* Created: Tue Sep  1 20:07:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__MAJ3_4%B N_B_c_152_n N_B_M1011_g N_B_c_144_n N_B_M1017_g
 + N_B_c_153_n N_B_M1016_g N_B_c_145_n N_B_M1025_g N_B_c_154_n N_B_M1012_g

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_4.spice b/cells/maj3/sky130_fd_sc_hs__maj3_4.spice
index 6e48bd6..d8abb91 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_4.spice
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__maj3_4.spice
-* Created: Thu Aug 27 20:48:38 2020
+* Created: Tue Sep  1 20:07:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_1.lvs.report b/cells/mux2/sky130_fd_sc_hs__mux2_1.lvs.report
new file mode 100644
index 0000000..e1d5a2b
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_1.lvs.report

@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux2_1.sp ('sky130_fd_sc_hs__mux2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_1.spice ('sky130_fd_sc_hs__mux2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux2_1       sky130_fd_sc_hs__mux2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB S A1 A0 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_1.pex.spice b/cells/mux2/sky130_fd_sc_hs__mux2_1.pex.spice
index a7eadaa..4c7bde3 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_1.pex.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_1.pex.spice
-* Created: Thu Aug 27 20:48:45 2020
+* Created: Tue Sep  1 20:07:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_1.pxi.spice b/cells/mux2/sky130_fd_sc_hs__mux2_1.pxi.spice
index 08d889a..760c6d9 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_1.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_1.pxi.spice
-* Created: Thu Aug 27 20:48:45 2020
+* Created: Tue Sep  1 20:07:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX2_1%S N_S_M1003_g N_S_c_78_n N_S_M1005_g N_S_c_79_n
 + N_S_M1000_g N_S_M1006_g N_S_c_74_n N_S_c_75_n N_S_c_76_n S N_S_c_77_n

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_1.spice b/cells/mux2/sky130_fd_sc_hs__mux2_1.spice
index bf387f2..64a489a 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_1.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_1.spice
-* Created: Thu Aug 27 20:48:45 2020
+* Created: Tue Sep  1 20:07:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_2.lvs.report b/cells/mux2/sky130_fd_sc_hs__mux2_2.lvs.report
new file mode 100644
index 0000000..a94cb86
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_2.lvs.report

@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux2_2.sp ('sky130_fd_sc_hs__mux2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_2.spice ('sky130_fd_sc_hs__mux2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux2_2       sky130_fd_sc_hs__mux2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A0 A1 S VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_2.pex.spice b/cells/mux2/sky130_fd_sc_hs__mux2_2.pex.spice
index d9ed425..e18f9c0 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_2.pex.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_2.pex.spice
-* Created: Thu Aug 27 20:48:53 2020
+* Created: Tue Sep  1 20:07:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_2.pxi.spice b/cells/mux2/sky130_fd_sc_hs__mux2_2.pxi.spice
index 7fb7544..53b5978 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_2.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_2.pxi.spice
-* Created: Thu Aug 27 20:48:53 2020
+* Created: Tue Sep  1 20:07:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX2_2%A0 N_A0_c_93_n N_A0_M1008_g N_A0_c_94_n
 + N_A0_M1003_g A0 PM_SKY130_FD_SC_HS__MUX2_2%A0

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_2.spice b/cells/mux2/sky130_fd_sc_hs__mux2_2.spice
index 0169f65..4d5a152 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_2.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_2.spice
-* Created: Thu Aug 27 20:48:53 2020
+* Created: Tue Sep  1 20:07:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_4.lvs.report b/cells/mux2/sky130_fd_sc_hs__mux2_4.lvs.report
new file mode 100644
index 0000000..c93f8dc
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_4.lvs.report

@@ -0,0 +1,504 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux2_4.sp ('sky130_fd_sc_hs__mux2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2/sky130_fd_sc_hs__mux2_4.spice ('sky130_fd_sc_hs__mux2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux2_4       sky130_fd_sc_hs__mux2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB S A0 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_4.pex.spice b/cells/mux2/sky130_fd_sc_hs__mux2_4.pex.spice
index 1815381..b9c40aa 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_4.pex.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_4.pex.spice
-* Created: Thu Aug 27 20:49:00 2020
+* Created: Tue Sep  1 20:07:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_4.pxi.spice b/cells/mux2/sky130_fd_sc_hs__mux2_4.pxi.spice
index 9cf90f1..13c6700 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_4.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_4.pxi.spice
-* Created: Thu Aug 27 20:49:00 2020
+* Created: Tue Sep  1 20:07:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX2_4%S N_S_c_158_n N_S_M1016_g N_S_M1003_g N_S_M1001_g
 + N_S_c_167_n N_S_M1002_g N_S_M1024_g N_S_c_168_n N_S_M1007_g N_S_c_169_n

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_4.spice b/cells/mux2/sky130_fd_sc_hs__mux2_4.spice
index 050c72b..29b3add 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_4.spice
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2_4.spice
-* Created: Thu Aug 27 20:49:00 2020
+* Created: Tue Sep  1 20:07:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.lvs.report b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.lvs.report
new file mode 100644
index 0000000..15f601a
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.lvs.report

@@ -0,0 +1,483 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux2i_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux2i_1.sp ('sky130_fd_sc_hs__mux2i_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice ('sky130_fd_sc_hs__mux2i_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux2i_1      sky130_fd_sc_hs__mux2i_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux2i_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux2i_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB S A0 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pex.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pex.spice
index 7f99442..57b3653 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_1.pex.spice
-* Created: Thu Aug 27 20:49:08 2020
+* Created: Tue Sep  1 20:07:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pxi.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pxi.spice
index 6ef81d8..837e184 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_1.pxi.spice
-* Created: Thu Aug 27 20:49:08 2020
+* Created: Tue Sep  1 20:07:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX2I_1%S N_S_M1008_g N_S_c_76_n N_S_M1002_g N_S_c_69_n
 + N_S_c_70_n N_S_c_78_n N_S_M1006_g N_S_c_71_n N_S_M1009_g N_S_c_72_n N_S_c_79_n

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice
index 02ce3b2..f5c5881 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_1.spice
-* Created: Thu Aug 27 20:49:08 2020
+* Created: Tue Sep  1 20:07:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.lvs.report b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.lvs.report
new file mode 100644
index 0000000..801eed7
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.lvs.report

@@ -0,0 +1,496 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux2i_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux2i_2.sp ('sky130_fd_sc_hs__mux2i_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice ('sky130_fd_sc_hs__mux2i_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:07:56 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux2i_2      sky130_fd_sc_hs__mux2i_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux2i_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux2i_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A0 A1 S Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pex.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pex.spice
index 08a2f0e..faf68a0 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_2.pex.spice
-* Created: Thu Aug 27 20:49:16 2020
+* Created: Tue Sep  1 20:07:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pxi.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pxi.spice
index cfb4662..8483848 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_2.pxi.spice
-* Created: Thu Aug 27 20:49:16 2020
+* Created: Tue Sep  1 20:07:59 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX2I_2%A0 N_A0_c_90_n N_A0_M1008_g N_A0_c_94_n
 + N_A0_M1000_g N_A0_c_95_n N_A0_M1005_g N_A0_c_91_n N_A0_M1016_g A0 A0

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice
index d285f23..1724481 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_2.spice
-* Created: Thu Aug 27 20:49:16 2020
+* Created: Tue Sep  1 20:07:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.lvs.report b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.lvs.report
new file mode 100644
index 0000000..c3477ce
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.lvs.report

@@ -0,0 +1,513 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux2i_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux2i_4.sp ('sky130_fd_sc_hs__mux2i_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice ('sky130_fd_sc_hs__mux2i_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:02 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux2i_4      sky130_fd_sc_hs__mux2i_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux2i_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux2i_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              13        13
+
+ Instances:         17        17         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        36        35
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   34 layout mos transistors were reduced to 9.
+     25 mos transistors were deleted by parallel reduction.
+   34 source mos transistors were reduced to 9.
+     25 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A0 S Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pex.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pex.spice
index 2c48a64..3d531d1 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_4.pex.spice
-* Created: Thu Aug 27 20:49:24 2020
+* Created: Tue Sep  1 20:08:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pxi.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pxi.spice
index 57c3518..a28ed33 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_4.pxi.spice
-* Created: Thu Aug 27 20:49:24 2020
+* Created: Tue Sep  1 20:08:05 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX2I_4%A1 N_A1_M1000_g N_A1_c_133_n N_A1_M1015_g
 + N_A1_M1001_g N_A1_c_134_n N_A1_M1016_g N_A1_M1017_g N_A1_c_135_n N_A1_M1018_g

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice
index 6f604fd..29c7d32 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux2i_4.spice
-* Created: Thu Aug 27 20:49:24 2020
+* Created: Tue Sep  1 20:08:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_1.lvs.report b/cells/mux4/sky130_fd_sc_hs__mux4_1.lvs.report
new file mode 100644
index 0000000..79ca21d
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_1.lvs.report

@@ -0,0 +1,499 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux4_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux4_1.sp ('sky130_fd_sc_hs__mux4_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_1.spice ('sky130_fd_sc_hs__mux4_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux4_1       sky130_fd_sc_hs__mux4_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux4_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              24        24
+
+ Instances:         13        13         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        27        26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              16        16
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A0 A1 A2 S0 A3 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_1.pex.spice b/cells/mux4/sky130_fd_sc_hs__mux4_1.pex.spice
index a22abf9..1f2517f 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_1.pex.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_1.pex.spice
-* Created: Thu Aug 27 20:49:32 2020
+* Created: Tue Sep  1 20:08:11 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_1.pxi.spice b/cells/mux4/sky130_fd_sc_hs__mux4_1.pxi.spice
index e1098ce..57024f4 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_1.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_1.pxi.spice
-* Created: Thu Aug 27 20:49:32 2020
+* Created: Tue Sep  1 20:08:11 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX4_1%A0 N_A0_c_181_n N_A0_M1001_g N_A0_M1008_g A0
 + N_A0_c_183_n PM_SKY130_FD_SC_HS__MUX4_1%A0

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_1.spice b/cells/mux4/sky130_fd_sc_hs__mux4_1.spice
index 8e1050a..be8007e 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_1.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_1.spice
-* Created: Thu Aug 27 20:49:32 2020
+* Created: Tue Sep  1 20:08:11 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_2.lvs.report b/cells/mux4/sky130_fd_sc_hs__mux4_2.lvs.report
new file mode 100644
index 0000000..1c2954b
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_2.lvs.report

@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux4_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux4_2.sp ('sky130_fd_sc_hs__mux4_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_2.spice ('sky130_fd_sc_hs__mux4_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux4_2       sky130_fd_sc_hs__mux4_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux4_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              24        24
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              16        16
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB S0 A1 A0 A3 A2 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_2.pex.spice b/cells/mux4/sky130_fd_sc_hs__mux4_2.pex.spice
index 4057ebb..581d107 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_2.pex.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_2.pex.spice
-* Created: Thu Aug 27 20:49:43 2020
+* Created: Tue Sep  1 20:08:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_2.pxi.spice b/cells/mux4/sky130_fd_sc_hs__mux4_2.pxi.spice
index 802dd54..7f3a144 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_2.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_2.pxi.spice
-* Created: Thu Aug 27 20:49:43 2020
+* Created: Tue Sep  1 20:08:17 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX4_2%S0 N_S0_M1001_g N_S0_c_165_n N_S0_c_183_n
 + N_S0_M1007_g N_S0_M1010_g N_S0_c_167_n N_S0_M1020_g N_S0_M1016_g N_S0_c_168_n

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_2.spice b/cells/mux4/sky130_fd_sc_hs__mux4_2.spice
index e8354e1..4513d31 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_2.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_2.spice
-* Created: Thu Aug 27 20:49:43 2020
+* Created: Tue Sep  1 20:08:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_4.lvs.report b/cells/mux4/sky130_fd_sc_hs__mux4_4.lvs.report
new file mode 100644
index 0000000..2ff7ae6
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_4.lvs.report

@@ -0,0 +1,530 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 75 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 77 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 79 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 81 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 83 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 85 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 87 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 89 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 91 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 93 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 95 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 97 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 99 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 101 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 103 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 105 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 107 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 109 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 111 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 113 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 115 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 117 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 119 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 121 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__mux4_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__mux4_4.sp ('sky130_fd_sc_hs__mux4_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/mux4/sky130_fd_sc_hs__mux4_4.spice ('sky130_fd_sc_hs__mux4_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__mux4_4       sky130_fd_sc_hs__mux4_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__mux4_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__mux4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              24        24
+
+ Instances:         26        26         MN (4 pins)
+                    26        26         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        53        52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              16        16
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               16         16            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   48 layout mos transistors were reduced to 22.
+     26 mos transistors were deleted by parallel reduction.
+   48 source mos transistors were reduced to 22.
+     26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A0 S0 A2 A3 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_4.pex.spice b/cells/mux4/sky130_fd_sc_hs__mux4_4.pex.spice
index 95d6bd7..222c4ba 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_4.pex.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_4.pex.spice
-* Created: Thu Aug 27 20:49:50 2020
+* Created: Tue Sep  1 20:08:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_4.pxi.spice b/cells/mux4/sky130_fd_sc_hs__mux4_4.pxi.spice
index d8c42b8..64220d3 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_4.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_4.pxi.spice
-* Created: Thu Aug 27 20:49:50 2020
+* Created: Tue Sep  1 20:08:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__MUX4_4%A1 N_A1_M1034_g N_A1_c_318_n N_A1_M1015_g
 + N_A1_M1037_g N_A1_c_319_n N_A1_M1016_g A1 A1 N_A1_c_317_n

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_4.spice b/cells/mux4/sky130_fd_sc_hs__mux4_4.spice
index cd1cf5a..bed2ad7 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_4.spice
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__mux4_4.spice
-* Created: Thu Aug 27 20:49:50 2020
+* Created: Tue Sep  1 20:08:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_1.lvs.report b/cells/nand2/sky130_fd_sc_hs__nand2_1.lvs.report
new file mode 100644
index 0000000..2855029
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2_1.sp ('sky130_fd_sc_hs__nand2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2/sky130_fd_sc_hs__nand2_1.spice ('sky130_fd_sc_hs__nand2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:27 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2_1      sky130_fd_sc_hs__nand2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         5         4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_1.pex.spice b/cells/nand2/sky130_fd_sc_hs__nand2_1.pex.spice
index 86a1e73..14e9650 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_1.pex.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_1.pex.spice
-* Created: Thu Aug 27 20:49:58 2020
+* Created: Tue Sep  1 20:08:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_1.pxi.spice b/cells/nand2/sky130_fd_sc_hs__nand2_1.pxi.spice
index ce6bb70..b284c6e 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_1.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_1.pxi.spice
-* Created: Thu Aug 27 20:49:58 2020
+* Created: Tue Sep  1 20:08:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2_1%B N_B_c_25_n N_B_M1000_g N_B_c_26_n N_B_M1003_g B
 + PM_SKY130_FD_SC_HS__NAND2_1%B

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_1.spice b/cells/nand2/sky130_fd_sc_hs__nand2_1.spice
index cd7391b..daa8332 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_1.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_1.spice
-* Created: Thu Aug 27 20:49:58 2020
+* Created: Tue Sep  1 20:08:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_2.lvs.report b/cells/nand2/sky130_fd_sc_hs__nand2_2.lvs.report
new file mode 100644
index 0000000..f9aec0c
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2_2.sp ('sky130_fd_sc_hs__nand2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2/sky130_fd_sc_hs__nand2_2.spice ('sky130_fd_sc_hs__nand2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:33 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2_2      sky130_fd_sc_hs__nand2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_2.pex.spice b/cells/nand2/sky130_fd_sc_hs__nand2_2.pex.spice
index c1b3924..99a9566 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_2.pex.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_2.pex.spice
-* Created: Thu Aug 27 20:50:05 2020
+* Created: Tue Sep  1 20:08:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_2.pxi.spice b/cells/nand2/sky130_fd_sc_hs__nand2_2.pxi.spice
index 8d5cc6a..df0d26f 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_2.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_2.pxi.spice
-* Created: Thu Aug 27 20:50:05 2020
+* Created: Tue Sep  1 20:08:36 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2_2%B N_B_M1004_g N_B_c_49_n N_B_M1001_g N_B_c_50_n
 + N_B_M1003_g N_B_M1005_g B B N_B_c_48_n PM_SKY130_FD_SC_HS__NAND2_2%B

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_2.spice b/cells/nand2/sky130_fd_sc_hs__nand2_2.spice
index 63372cd..638f192 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_2.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_2.spice
-* Created: Thu Aug 27 20:50:05 2020
+* Created: Tue Sep  1 20:08:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_4.lvs.report b/cells/nand2/sky130_fd_sc_hs__nand2_4.lvs.report
new file mode 100644
index 0000000..b6e1be1
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2_4.sp ('sky130_fd_sc_hs__nand2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2/sky130_fd_sc_hs__nand2_4.spice ('sky130_fd_sc_hs__nand2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:39 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2_4      sky130_fd_sc_hs__nand2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          8         8         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_4.pex.spice b/cells/nand2/sky130_fd_sc_hs__nand2_4.pex.spice
index 7842ccb..de7e160 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_4.pex.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_4.pex.spice
-* Created: Thu Aug 27 20:50:13 2020
+* Created: Tue Sep  1 20:08:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_4.pxi.spice b/cells/nand2/sky130_fd_sc_hs__nand2_4.pxi.spice
index 061555b..35a38e6 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_4.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_4.pxi.spice
-* Created: Thu Aug 27 20:50:13 2020
+* Created: Tue Sep  1 20:08:42 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2_4%B N_B_M1006_g N_B_c_73_n N_B_M1001_g N_B_M1009_g
 + N_B_M1010_g N_B_c_74_n N_B_M1005_g N_B_M1011_g B B B N_B_c_72_n N_B_c_77_n

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_4.spice b/cells/nand2/sky130_fd_sc_hs__nand2_4.spice
index 779beb8..2e84ea9 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_4.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_4.spice
-* Created: Thu Aug 27 20:50:13 2020
+* Created: Tue Sep  1 20:08:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_8.lvs.report b/cells/nand2/sky130_fd_sc_hs__nand2_8.lvs.report
new file mode 100644
index 0000000..6b4d0c4
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_8.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2_8.sp ('sky130_fd_sc_hs__nand2_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2/sky130_fd_sc_hs__nand2_8.spice ('sky130_fd_sc_hs__nand2_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:45 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2_8      sky130_fd_sc_hs__nand2_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:         16        16         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 4.
+     20 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 4.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_8.pex.spice b/cells/nand2/sky130_fd_sc_hs__nand2_8.pex.spice
index 227c2c1..0fcd35f 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_8.pex.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_8.pex.spice
-* Created: Thu Aug 27 20:50:20 2020
+* Created: Tue Sep  1 20:08:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_8.pxi.spice b/cells/nand2/sky130_fd_sc_hs__nand2_8.pxi.spice
index 392993a..fdd2bfc 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_8.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_8.pxi.spice
-* Created: Thu Aug 27 20:50:20 2020
+* Created: Tue Sep  1 20:08:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2_8%B N_B_c_108_n N_B_M1000_g N_B_c_109_n N_B_c_110_n
 + N_B_c_111_n N_B_M1001_g N_B_c_112_n N_B_c_113_n N_B_M1003_g N_B_c_114_n

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_8.spice b/cells/nand2/sky130_fd_sc_hs__nand2_8.spice
index 5fd1cb9..93f9b78 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_8.spice
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2_8.spice
-* Created: Thu Aug 27 20:50:20 2020
+* Created: Tue Sep  1 20:08:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.lvs.report b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.lvs.report
new file mode 100644
index 0000000..b403ff3
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2b_1.sp ('sky130_fd_sc_hs__nand2b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2b/sky130_fd_sc_hs__nand2b_1.spice ('sky130_fd_sc_hs__nand2b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:51 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2b_1     sky130_fd_sc_hs__nand2b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pex.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pex.spice
index 962f17d..4dcd043 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_1.pex.spice
-* Created: Thu Aug 27 20:50:29 2020
+* Created: Tue Sep  1 20:08:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pxi.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pxi.spice
index 905921a..e873005 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_1.pxi.spice
-* Created: Thu Aug 27 20:50:29 2020
+* Created: Tue Sep  1 20:08:54 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2B_1%A_N N_A_N_M1004_g N_A_N_c_45_n N_A_N_M1005_g A_N
 + A_N N_A_N_c_44_n PM_SKY130_FD_SC_HS__NAND2B_1%A_N

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.spice
index 98c277f..86e8d87 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_1.spice
-* Created: Thu Aug 27 20:50:29 2020
+* Created: Tue Sep  1 20:08:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.lvs.report b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.lvs.report
new file mode 100644
index 0000000..a3769eb
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2b_2.sp ('sky130_fd_sc_hs__nand2b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2b/sky130_fd_sc_hs__nand2b_2.spice ('sky130_fd_sc_hs__nand2b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:08:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2b_2     sky130_fd_sc_hs__nand2b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pex.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pex.spice
index 343b2ee..4759b2d 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_2.pex.spice
-* Created: Thu Aug 27 20:50:36 2020
+* Created: Tue Sep  1 20:09:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pxi.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pxi.spice
index 4181f1c..a7be1d0 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_2.pxi.spice
-* Created: Thu Aug 27 20:50:36 2020
+* Created: Tue Sep  1 20:09:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2B_2%A_N N_A_N_M1008_g N_A_N_c_72_n N_A_N_M1003_g A_N
 + N_A_N_c_73_n PM_SKY130_FD_SC_HS__NAND2B_2%A_N

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.spice
index 2dde3a5..4dade1b 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_2.spice
-* Created: Thu Aug 27 20:50:36 2020
+* Created: Tue Sep  1 20:09:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.lvs.report b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.lvs.report
new file mode 100644
index 0000000..77bf3ec
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand2b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand2b_4.sp ('sky130_fd_sc_hs__nand2b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand2b/sky130_fd_sc_hs__nand2b_4.spice ('sky130_fd_sc_hs__nand2b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand2b_4     sky130_fd_sc_hs__nand2b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand2b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          9         9         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        16        15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pex.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pex.spice
index 46cf90f..c171ca9 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_4.pex.spice
-* Created: Thu Aug 27 20:50:47 2020
+* Created: Tue Sep  1 20:09:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pxi.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pxi.spice
index 3c78679..4b2779a 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_4.pxi.spice
-* Created: Thu Aug 27 20:50:47 2020
+* Created: Tue Sep  1 20:09:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND2B_4%A_N N_A_N_M1012_g N_A_N_c_91_n N_A_N_M1005_g
 + N_A_N_c_86_n N_A_N_c_93_n N_A_N_M1008_g N_A_N_c_87_n N_A_N_c_88_n A_N A_N

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.spice b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.spice
index f1bab51..0f44103 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.spice
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand2b_4.spice
-* Created: Thu Aug 27 20:50:47 2020
+* Created: Tue Sep  1 20:09:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_1.lvs.report b/cells/nand3/sky130_fd_sc_hs__nand3_1.lvs.report
new file mode 100644
index 0000000..cfe7c38
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand3_1.sp ('sky130_fd_sc_hs__nand3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand3/sky130_fd_sc_hs__nand3_1.spice ('sky130_fd_sc_hs__nand3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand3_1      sky130_fd_sc_hs__nand3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_1.pex.spice b/cells/nand3/sky130_fd_sc_hs__nand3_1.pex.spice
index 3f7ce9a..fe78402 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_1.pex.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_1.pex.spice
-* Created: Thu Aug 27 20:50:54 2020
+* Created: Tue Sep  1 20:09:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_1.pxi.spice b/cells/nand3/sky130_fd_sc_hs__nand3_1.pxi.spice
index 7b8196e..daa9f82 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_1.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_1.pxi.spice
-* Created: Thu Aug 27 20:50:54 2020
+* Created: Tue Sep  1 20:09:12 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND3_1%C N_C_c_36_n N_C_c_37_n N_C_M1001_g N_C_c_38_n
 + N_C_M1005_g C C PM_SKY130_FD_SC_HS__NAND3_1%C

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_1.spice b/cells/nand3/sky130_fd_sc_hs__nand3_1.spice
index 0baeea2..a8162db 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_1.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_1.spice
-* Created: Thu Aug 27 20:50:54 2020
+* Created: Tue Sep  1 20:09:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_2.lvs.report b/cells/nand3/sky130_fd_sc_hs__nand3_2.lvs.report
new file mode 100644
index 0000000..89c25c5
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand3_2.sp ('sky130_fd_sc_hs__nand3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand3/sky130_fd_sc_hs__nand3_2.spice ('sky130_fd_sc_hs__nand3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:16 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand3_2      sky130_fd_sc_hs__nand3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_2.pex.spice b/cells/nand3/sky130_fd_sc_hs__nand3_2.pex.spice
index 884ac08..8363ab6 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_2.pex.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_2.pex.spice
-* Created: Thu Aug 27 20:51:02 2020
+* Created: Tue Sep  1 20:09:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_2.pxi.spice b/cells/nand3/sky130_fd_sc_hs__nand3_2.pxi.spice
index 8b3b997..7bbf9c3 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_2.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_2.pxi.spice
-* Created: Thu Aug 27 20:51:02 2020
+* Created: Tue Sep  1 20:09:18 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND3_2%C N_C_c_58_n N_C_M1000_g N_C_c_62_n N_C_M1004_g
 + N_C_c_59_n N_C_M1010_g N_C_c_63_n N_C_M1006_g C N_C_c_60_n N_C_c_61_n

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_2.spice b/cells/nand3/sky130_fd_sc_hs__nand3_2.spice
index 733fad9..ca95029 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_2.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_2.spice
-* Created: Thu Aug 27 20:51:02 2020
+* Created: Tue Sep  1 20:09:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_4.lvs.report b/cells/nand3/sky130_fd_sc_hs__nand3_4.lvs.report
new file mode 100644
index 0000000..d2508d0
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand3_4.sp ('sky130_fd_sc_hs__nand3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand3/sky130_fd_sc_hs__nand3_4.spice ('sky130_fd_sc_hs__nand3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand3_4      sky130_fd_sc_hs__nand3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:         12        12         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   18 layout mos transistors were reduced to 6.
+     12 mos transistors were deleted by parallel reduction.
+   18 source mos transistors were reduced to 6.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_4.pex.spice b/cells/nand3/sky130_fd_sc_hs__nand3_4.pex.spice
index a2ac0d6..209fe59 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_4.pex.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_4.pex.spice
-* Created: Thu Aug 27 20:51:09 2020
+* Created: Tue Sep  1 20:09:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_4.pxi.spice b/cells/nand3/sky130_fd_sc_hs__nand3_4.pxi.spice
index 9669076..d55f616 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_4.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_4.pxi.spice
-* Created: Thu Aug 27 20:51:09 2020
+* Created: Tue Sep  1 20:09:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND3_4%A N_A_c_87_n N_A_M1004_g N_A_c_92_n N_A_M1006_g
 + N_A_c_88_n N_A_M1009_g N_A_c_89_n N_A_M1010_g N_A_c_93_n N_A_M1014_g

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_4.spice b/cells/nand3/sky130_fd_sc_hs__nand3_4.spice
index 939f540..73c64ea 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_4.spice
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3_4.spice
-* Created: Thu Aug 27 20:51:09 2020
+* Created: Tue Sep  1 20:09:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.lvs.report b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.lvs.report
new file mode 100644
index 0000000..9e185c1
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand3b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand3b_1.sp ('sky130_fd_sc_hs__nand3b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand3b/sky130_fd_sc_hs__nand3b_1.spice ('sky130_fd_sc_hs__nand3b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:28 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand3b_1     sky130_fd_sc_hs__nand3b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand3b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pex.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pex.spice
index 9e998f4..bc54b48 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_1.pex.spice
-* Created: Thu Aug 27 20:51:17 2020
+* Created: Tue Sep  1 20:09:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pxi.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pxi.spice
index 2175c74..2dec911 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_1.pxi.spice
-* Created: Thu Aug 27 20:51:17 2020
+* Created: Tue Sep  1 20:09:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND3B_1%A_N N_A_N_M1003_g N_A_N_c_48_n N_A_N_M1005_g A_N
 + N_A_N_c_49_n PM_SKY130_FD_SC_HS__NAND3B_1%A_N

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.spice
index 034d4b3..5a9a872 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_1.spice
-* Created: Thu Aug 27 20:51:17 2020
+* Created: Tue Sep  1 20:09:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.lvs.report b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.lvs.report
new file mode 100644
index 0000000..f4ca7d1
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand3b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand3b_2.sp ('sky130_fd_sc_hs__nand3b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand3b/sky130_fd_sc_hs__nand3b_2.spice ('sky130_fd_sc_hs__nand3b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:34 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand3b_2     sky130_fd_sc_hs__nand3b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand3b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pex.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pex.spice
index b507a73..5219eba 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_2.pex.spice
-* Created: Thu Aug 27 20:51:24 2020
+* Created: Tue Sep  1 20:09:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pxi.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pxi.spice
index 38e4ca0..95f85ce 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_2.pxi.spice
-* Created: Thu Aug 27 20:51:24 2020
+* Created: Tue Sep  1 20:09:37 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND3B_2%A_N N_A_N_M1001_g N_A_N_c_74_n N_A_N_M1003_g A_N
 + N_A_N_c_72_n N_A_N_c_73_n PM_SKY130_FD_SC_HS__NAND3B_2%A_N

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.spice
index 9dc90ea..bbf924a 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_2.spice
-* Created: Thu Aug 27 20:51:24 2020
+* Created: Tue Sep  1 20:09:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.lvs.report b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.lvs.report
new file mode 100644
index 0000000..5f98154
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand3b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand3b_4.sp ('sky130_fd_sc_hs__nand3b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand3b/sky130_fd_sc_hs__nand3b_4.spice ('sky130_fd_sc_hs__nand3b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:40 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand3b_4     sky130_fd_sc_hs__nand3b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand3b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         13        13         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        22        21
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 7.
+     13 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 7.
+     13 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pex.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pex.spice
index 805110f..9372ad1 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_4.pex.spice
-* Created: Thu Aug 27 20:51:33 2020
+* Created: Tue Sep  1 20:09:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pxi.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pxi.spice
index fb4e216..e011be8 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_4.pxi.spice
-* Created: Thu Aug 27 20:51:33 2020
+* Created: Tue Sep  1 20:09:43 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND3B_4%A_N N_A_N_M1000_g N_A_N_c_105_n N_A_N_M1003_g
 + N_A_N_c_102_n N_A_N_c_107_n N_A_N_M1006_g A_N N_A_N_c_103_n N_A_N_c_104_n

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.spice b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.spice
index a8ddccd..8c09310 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.spice
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand3b_4.spice
-* Created: Thu Aug 27 20:51:33 2020
+* Created: Tue Sep  1 20:09:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_1.lvs.report b/cells/nand4/sky130_fd_sc_hs__nand4_1.lvs.report
new file mode 100644
index 0000000..3078009
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4_1.sp ('sky130_fd_sc_hs__nand4_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4/sky130_fd_sc_hs__nand4_1.spice ('sky130_fd_sc_hs__nand4_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:46 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4_1      sky130_fd_sc_hs__nand4_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          4         4         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_1.pex.spice b/cells/nand4/sky130_fd_sc_hs__nand4_1.pex.spice
index dc4507c..fdfc6f5 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_1.pex.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_1.pex.spice
-* Created: Thu Aug 27 20:51:41 2020
+* Created: Tue Sep  1 20:09:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_1.pxi.spice b/cells/nand4/sky130_fd_sc_hs__nand4_1.pxi.spice
index 0e16616..8142a1b 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_1.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_1.pxi.spice
-* Created: Thu Aug 27 20:51:41 2020
+* Created: Tue Sep  1 20:09:49 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4_1%D N_D_c_43_n N_D_M1004_g N_D_c_44_n N_D_M1000_g D
 + PM_SKY130_FD_SC_HS__NAND4_1%D

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_1.spice b/cells/nand4/sky130_fd_sc_hs__nand4_1.spice
index b52c7e2..933bdf1 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_1.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_1.spice
-* Created: Thu Aug 27 20:51:41 2020
+* Created: Tue Sep  1 20:09:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_2.lvs.report b/cells/nand4/sky130_fd_sc_hs__nand4_2.lvs.report
new file mode 100644
index 0000000..beb9a1c
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4_2.sp ('sky130_fd_sc_hs__nand4_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4/sky130_fd_sc_hs__nand4_2.spice ('sky130_fd_sc_hs__nand4_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:52 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4_2      sky130_fd_sc_hs__nand4_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          4         4         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_2.pex.spice b/cells/nand4/sky130_fd_sc_hs__nand4_2.pex.spice
index a607339..64e3569 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_2.pex.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_2.pex.spice
-* Created: Thu Aug 27 20:51:51 2020
+* Created: Tue Sep  1 20:09:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_2.pxi.spice b/cells/nand4/sky130_fd_sc_hs__nand4_2.pxi.spice
index 08f97fe..4dc6cda 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_2.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_2.pxi.spice
-* Created: Thu Aug 27 20:51:51 2020
+* Created: Tue Sep  1 20:09:55 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4_2%D N_D_M1005_g N_D_c_84_n N_D_M1007_g N_D_c_85_n
 + N_D_M1010_g N_D_M1012_g D D N_D_c_82_n N_D_c_83_n

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_2.spice b/cells/nand4/sky130_fd_sc_hs__nand4_2.spice
index 8a1046a..8884e63 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_2.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_2.spice
-* Created: Thu Aug 27 20:51:51 2020
+* Created: Tue Sep  1 20:09:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_4.lvs.report b/cells/nand4/sky130_fd_sc_hs__nand4_4.lvs.report
new file mode 100644
index 0000000..ea8a3e1
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4_4.sp ('sky130_fd_sc_hs__nand4_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4/sky130_fd_sc_hs__nand4_4.spice ('sky130_fd_sc_hs__nand4_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:09:58 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4_4      sky130_fd_sc_hs__nand4_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         16        16         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          4         4         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 8.
+     16 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 8.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_4.pex.spice b/cells/nand4/sky130_fd_sc_hs__nand4_4.pex.spice
index fba4803..6797642 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_4.pex.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_4.pex.spice
-* Created: Thu Aug 27 20:51:59 2020
+* Created: Tue Sep  1 20:10:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_4.pxi.spice b/cells/nand4/sky130_fd_sc_hs__nand4_4.pxi.spice
index bddcdbd..eca8024 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_4.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_4.pxi.spice
-* Created: Thu Aug 27 20:51:59 2020
+* Created: Tue Sep  1 20:10:01 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4_4%D N_D_M1008_g N_D_M1010_g N_D_c_109_n N_D_M1014_g
 + N_D_c_118_n N_D_M1016_g N_D_M1020_g N_D_c_119_n N_D_M1017_g N_D_c_112_n

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_4.spice b/cells/nand4/sky130_fd_sc_hs__nand4_4.spice
index 248f623..d8d134e 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_4.spice
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4_4.spice
-* Created: Thu Aug 27 20:51:59 2020
+* Created: Tue Sep  1 20:10:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.lvs.report b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.lvs.report
new file mode 100644
index 0000000..8f88147
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4b_1.sp ('sky130_fd_sc_hs__nand4b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4b/sky130_fd_sc_hs__nand4b_1.spice ('sky130_fd_sc_hs__nand4b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:04 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4b_1     sky130_fd_sc_hs__nand4b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N D C B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pex.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pex.spice
index b7c330b..0962494 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_1.pex.spice
-* Created: Thu Aug 27 20:52:06 2020
+* Created: Tue Sep  1 20:10:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pxi.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pxi.spice
index c49e98e..bbd88d0 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_1.pxi.spice
-* Created: Thu Aug 27 20:52:06 2020
+* Created: Tue Sep  1 20:10:07 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4B_1%A_N N_A_N_c_52_n N_A_N_M1007_g N_A_N_c_53_n
 + N_A_N_M1006_g A_N PM_SKY130_FD_SC_HS__NAND4B_1%A_N

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.spice
index 351ad66..aa763d0 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_1.spice
-* Created: Thu Aug 27 20:52:06 2020
+* Created: Tue Sep  1 20:10:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.lvs.report b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.lvs.report
new file mode 100644
index 0000000..dbe9a05
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4b_2.sp ('sky130_fd_sc_hs__nand4b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4b/sky130_fd_sc_hs__nand4b_2.spice ('sky130_fd_sc_hs__nand4b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4b_2     sky130_fd_sc_hs__nand4b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pex.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pex.spice
index 56ed3ad..dd7e62a 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_2.pex.spice
-* Created: Thu Aug 27 20:52:14 2020
+* Created: Tue Sep  1 20:10:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pxi.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pxi.spice
index c979b95..218b14e 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_2.pxi.spice
-* Created: Thu Aug 27 20:52:14 2020
+* Created: Tue Sep  1 20:10:13 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4B_2%A_N N_A_N_M1015_g N_A_N_c_94_n N_A_N_c_98_n
 + N_A_N_M1003_g A_N A_N N_A_N_c_95_n N_A_N_c_96_n

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.spice
index 0610eb3..6831a4b 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_2.spice
-* Created: Thu Aug 27 20:52:14 2020
+* Created: Tue Sep  1 20:10:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.lvs.report b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.lvs.report
new file mode 100644
index 0000000..57ae9bf
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4b_4.sp ('sky130_fd_sc_hs__nand4b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4b/sky130_fd_sc_hs__nand4b_4.spice ('sky130_fd_sc_hs__nand4b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:16 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4b_4     sky130_fd_sc_hs__nand4b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         17        17         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        28        27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        5          5            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   26 layout mos transistors were reduced to 9.
+     17 mos transistors were deleted by parallel reduction.
+   26 source mos transistors were reduced to 9.
+     17 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pex.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pex.spice
index 332d712..88df032 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_4.pex.spice
-* Created: Thu Aug 27 20:52:21 2020
+* Created: Tue Sep  1 20:10:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pxi.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pxi.spice
index f1b1e3d..36ca864 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_4.pxi.spice
-* Created: Thu Aug 27 20:52:21 2020
+* Created: Tue Sep  1 20:10:19 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4B_4%A_N N_A_N_M1023_g N_A_N_c_121_n N_A_N_M1004_g
 + N_A_N_c_118_n N_A_N_c_119_n N_A_N_c_124_n N_A_N_M1006_g A_N A_N

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.spice b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.spice
index 9df3ade..d701257 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.spice
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4b_4.spice
-* Created: Thu Aug 27 20:52:21 2020
+* Created: Tue Sep  1 20:10:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.lvs.report b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.lvs.report
new file mode 100644
index 0000000..44faf37
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4bb_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4bb_1.sp ('sky130_fd_sc_hs__nand4bb_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.spice ('sky130_fd_sc_hs__nand4bb_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:22 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4bb_1    sky130_fd_sc_hs__nand4bb_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4bb_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pex.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pex.spice
index db1e36b..9950f91 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_1.pex.spice
-* Created: Thu Aug 27 20:52:29 2020
+* Created: Tue Sep  1 20:10:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pxi.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pxi.spice
index 361f31f..e353c9d 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_1.pxi.spice
-* Created: Thu Aug 27 20:52:29 2020
+* Created: Tue Sep  1 20:10:25 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4BB_1%A_N N_A_N_c_70_n N_A_N_c_71_n N_A_N_c_76_n
 + N_A_N_M1002_g N_A_N_M1005_g A_N N_A_N_c_73_n N_A_N_c_74_n

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.spice
index 10655f5..ac8e5bd 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_1.spice
-* Created: Thu Aug 27 20:52:29 2020
+* Created: Tue Sep  1 20:10:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.lvs.report b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.lvs.report
new file mode 100644
index 0000000..4b6d6ec
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4bb_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4bb_2.sp ('sky130_fd_sc_hs__nand4bb_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.spice ('sky130_fd_sc_hs__nand4bb_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:28 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4bb_2    sky130_fd_sc_hs__nand4bb_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4bb_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pex.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pex.spice
index fa06432..f1c3cfa 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_2.pex.spice
-* Created: Thu Aug 27 20:52:39 2020
+* Created: Tue Sep  1 20:10:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pxi.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pxi.spice
index 4bf43b0..30d3c8d 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_2.pxi.spice
-* Created: Thu Aug 27 20:52:39 2020
+* Created: Tue Sep  1 20:10:31 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4BB_2%A_N N_A_N_c_111_n N_A_N_M1008_g N_A_N_M1018_g
 + A_N N_A_N_c_113_n PM_SKY130_FD_SC_HS__NAND4BB_2%A_N

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.spice
index 03bca0d..3b0189e 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_2.spice
-* Created: Thu Aug 27 20:52:39 2020
+* Created: Tue Sep  1 20:10:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.lvs.report b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.lvs.report
new file mode 100644
index 0000000..855f91c
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nand4bb_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nand4bb_4.sp ('sky130_fd_sc_hs__nand4bb_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.spice ('sky130_fd_sc_hs__nand4bb_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:34 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nand4bb_4    sky130_fd_sc_hs__nand4bb_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nand4bb_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nand4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         18        18         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         1         SMN4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        6          6            0            0    MP(PSHORT)
+                        1          1            0            0    SMN4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   36 layout mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+   36 source mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pex.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pex.spice
index 75116cc..f664869 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_4.pex.spice
-* Created: Thu Aug 27 20:52:46 2020
+* Created: Tue Sep  1 20:10:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pxi.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pxi.spice
index 2ab243f..075b488 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_4.pxi.spice
-* Created: Thu Aug 27 20:52:46 2020
+* Created: Tue Sep  1 20:10:37 2020
 * 
 x_PM_SKY130_FD_SC_HS__NAND4BB_4%A_N N_A_N_M1019_g N_A_N_c_178_n N_A_N_c_182_n
 + N_A_N_M1025_g N_A_N_c_183_n N_A_N_M1026_g N_A_N_c_184_n A_N N_A_N_c_180_n

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.spice b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.spice
index 7b5c40e..39ef4a4 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.spice
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nand4bb_4.spice
-* Created: Thu Aug 27 20:52:46 2020
+* Created: Tue Sep  1 20:10:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_1.lvs.report b/cells/nor2/sky130_fd_sc_hs__nor2_1.lvs.report
new file mode 100644
index 0000000..a700637
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2_1.sp ('sky130_fd_sc_hs__nor2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2/sky130_fd_sc_hs__nor2_1.spice ('sky130_fd_sc_hs__nor2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:41 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2_1       sky130_fd_sc_hs__nor2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          2         2         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         5         4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_1.pex.spice b/cells/nor2/sky130_fd_sc_hs__nor2_1.pex.spice
index 8154daa..171b1cb 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_1.pex.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_1.pex.spice
-* Created: Thu Aug 27 20:52:57 2020
+* Created: Tue Sep  1 20:10:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_1.pxi.spice b/cells/nor2/sky130_fd_sc_hs__nor2_1.pxi.spice
index f4a3eea..865f865 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_1.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_1.pxi.spice
-* Created: Thu Aug 27 20:52:57 2020
+* Created: Tue Sep  1 20:10:44 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2_1%A N_A_c_27_n N_A_M1001_g N_A_M1003_g A N_A_c_29_n
 + PM_SKY130_FD_SC_HS__NOR2_1%A

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_1.spice b/cells/nor2/sky130_fd_sc_hs__nor2_1.spice
index 19ec38c..d8841fb 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_1.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_1.spice
-* Created: Thu Aug 27 20:52:57 2020
+* Created: Tue Sep  1 20:10:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_2.lvs.report b/cells/nor2/sky130_fd_sc_hs__nor2_2.lvs.report
new file mode 100644
index 0000000..a3eb5d9
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2_2.sp ('sky130_fd_sc_hs__nor2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2/sky130_fd_sc_hs__nor2_2.spice ('sky130_fd_sc_hs__nor2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:47 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2_2       sky130_fd_sc_hs__nor2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          2         2         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_2.pex.spice b/cells/nor2/sky130_fd_sc_hs__nor2_2.pex.spice
index 54d0d20..780960e 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_2.pex.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_2.pex.spice
-* Created: Thu Aug 27 20:53:05 2020
+* Created: Tue Sep  1 20:10:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_2.pxi.spice b/cells/nor2/sky130_fd_sc_hs__nor2_2.pxi.spice
index 88133d6..2d04fc6 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_2.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_2.pxi.spice
-* Created: Thu Aug 27 20:53:05 2020
+* Created: Tue Sep  1 20:10:50 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2_2%B N_B_M1004_g N_B_M1003_g N_B_c_40_n N_B_c_45_n
 + N_B_M1005_g N_B_c_41_n N_B_c_42_n N_B_c_47_n B PM_SKY130_FD_SC_HS__NOR2_2%B

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_2.spice b/cells/nor2/sky130_fd_sc_hs__nor2_2.spice
index d61c2d2..e0864ea 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_2.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_2.spice
-* Created: Thu Aug 27 20:53:05 2020
+* Created: Tue Sep  1 20:10:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_4.lvs.report b/cells/nor2/sky130_fd_sc_hs__nor2_4.lvs.report
new file mode 100644
index 0000000..f0d9346
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2_4.sp ('sky130_fd_sc_hs__nor2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2/sky130_fd_sc_hs__nor2_4.spice ('sky130_fd_sc_hs__nor2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:53 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2_4       sky130_fd_sc_hs__nor2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          4         4         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_4.pex.spice b/cells/nor2/sky130_fd_sc_hs__nor2_4.pex.spice
index 53ea21e..70d38bd 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_4.pex.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_4.pex.spice
-* Created: Thu Aug 27 20:53:12 2020
+* Created: Tue Sep  1 20:10:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_4.pxi.spice b/cells/nor2/sky130_fd_sc_hs__nor2_4.pxi.spice
index d0b8815..f7b85a3 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_4.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_4.pxi.spice
-* Created: Thu Aug 27 20:53:12 2020
+* Created: Tue Sep  1 20:10:56 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2_4%A N_A_c_54_n N_A_M1003_g N_A_c_50_n N_A_M1000_g
 + N_A_c_55_n N_A_M1005_g N_A_c_56_n N_A_M1006_g N_A_c_51_n N_A_M1001_g

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_4.spice b/cells/nor2/sky130_fd_sc_hs__nor2_4.spice
index 30f2069..f61bc67 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_4.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_4.spice
-* Created: Thu Aug 27 20:53:12 2020
+* Created: Tue Sep  1 20:10:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_8.lvs.report b/cells/nor2/sky130_fd_sc_hs__nor2_8.lvs.report
new file mode 100644
index 0000000..bbee717
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_8.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2_8.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2_8.sp ('sky130_fd_sc_hs__nor2_8')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2/sky130_fd_sc_hs__nor2_8.spice ('sky130_fd_sc_hs__nor2_8')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:10:59 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2_8       sky130_fd_sc_hs__nor2_8
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2_8
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          8         8         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               7         7
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                7          7            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 4.
+     20 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 4.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_8.pex.spice b/cells/nor2/sky130_fd_sc_hs__nor2_8.pex.spice
index 7d21a3b..90fd2cf 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_8.pex.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_8.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_8.pex.spice
-* Created: Thu Aug 27 20:53:20 2020
+* Created: Tue Sep  1 20:11:02 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_8.pxi.spice b/cells/nor2/sky130_fd_sc_hs__nor2_8.pxi.spice
index 1ce2380..e0f99cc 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_8.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_8.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_8.pxi.spice
-* Created: Thu Aug 27 20:53:20 2020
+* Created: Tue Sep  1 20:11:02 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2_8%A N_A_c_142_n N_A_M1009_g N_A_c_130_n N_A_c_131_n
 + N_A_c_145_n N_A_M1011_g N_A_c_132_n N_A_c_147_n N_A_M1012_g N_A_c_133_n

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_8.spice b/cells/nor2/sky130_fd_sc_hs__nor2_8.spice
index a1665c4..f2ffab6 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_8.spice
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_8.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2_8.spice
-* Created: Thu Aug 27 20:53:20 2020
+* Created: Tue Sep  1 20:11:02 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.lvs.report b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.lvs.report
new file mode 100644
index 0000000..e439172
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2b_1.sp ('sky130_fd_sc_hs__nor2b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2b/sky130_fd_sc_hs__nor2b_1.spice ('sky130_fd_sc_hs__nor2b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:05 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2b_1      sky130_fd_sc_hs__nor2b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pex.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pex.spice
index 59dfad0..7c392d0 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_1.pex.spice
-* Created: Thu Aug 27 20:53:27 2020
+* Created: Tue Sep  1 20:11:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pxi.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pxi.spice
index ddfb195..4660112 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_1.pxi.spice
-* Created: Thu Aug 27 20:53:27 2020
+* Created: Tue Sep  1 20:11:08 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2B_1%B_N N_B_N_c_40_n N_B_N_M1000_g N_B_N_c_41_n
 + N_B_N_M1003_g N_B_N_c_42_n B_N PM_SKY130_FD_SC_HS__NOR2B_1%B_N

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.spice
index 251443c..d38e825 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_1.spice
-* Created: Thu Aug 27 20:53:27 2020
+* Created: Tue Sep  1 20:11:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.lvs.report b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.lvs.report
new file mode 100644
index 0000000..feac622
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2b_2.sp ('sky130_fd_sc_hs__nor2b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2b/sky130_fd_sc_hs__nor2b_2.spice ('sky130_fd_sc_hs__nor2b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:11 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2b_2      sky130_fd_sc_hs__nor2b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pex.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pex.spice
index 6f6e4da..002bf62 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_2.pex.spice
-* Created: Thu Aug 27 20:53:35 2020
+* Created: Tue Sep  1 20:11:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pxi.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pxi.spice
index 7d56b79..a341e00 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_2.pxi.spice
-* Created: Thu Aug 27 20:53:35 2020
+* Created: Tue Sep  1 20:11:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2B_2%B_N N_B_N_c_63_n N_B_N_M1007_g N_B_N_M1005_g B_N
 + N_B_N_c_62_n PM_SKY130_FD_SC_HS__NOR2B_2%B_N

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.spice
index 7b01533..d491fd1 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_2.spice
-* Created: Thu Aug 27 20:53:35 2020
+* Created: Tue Sep  1 20:11:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.lvs.report b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.lvs.report
new file mode 100644
index 0000000..f13f672
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor2b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor2b_4.sp ('sky130_fd_sc_hs__nor2b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor2b/sky130_fd_sc_hs__nor2b_4.spice ('sky130_fd_sc_hs__nor2b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor2b_4      sky130_fd_sc_hs__nor2b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor2b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          5         5         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        16        15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B_N VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pex.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pex.spice
index 68e8eba..cd72c4a 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_4.pex.spice
-* Created: Thu Aug 27 20:53:43 2020
+* Created: Tue Sep  1 20:11:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pxi.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pxi.spice
index 4f75e13..fa1d4ed 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_4.pxi.spice
-* Created: Thu Aug 27 20:53:43 2020
+* Created: Tue Sep  1 20:11:20 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR2B_4%A N_A_c_80_n N_A_c_91_n N_A_M1006_g N_A_c_81_n
 + N_A_c_93_n N_A_M1007_g N_A_c_82_n N_A_c_95_n N_A_M1008_g N_A_c_83_n

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.spice b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.spice
index 30f8792..474c918 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.spice
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor2b_4.spice
-* Created: Thu Aug 27 20:53:43 2020
+* Created: Tue Sep  1 20:11:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_1.lvs.report b/cells/nor3/sky130_fd_sc_hs__nor3_1.lvs.report
new file mode 100644
index 0000000..8167fa7
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor3_1.sp ('sky130_fd_sc_hs__nor3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor3/sky130_fd_sc_hs__nor3_1.spice ('sky130_fd_sc_hs__nor3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:23 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor3_1       sky130_fd_sc_hs__nor3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_1.pex.spice b/cells/nor3/sky130_fd_sc_hs__nor3_1.pex.spice
index f301c10..8fba891 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_1.pex.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_1.pex.spice
-* Created: Thu Aug 27 20:53:51 2020
+* Created: Tue Sep  1 20:11:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_1.pxi.spice b/cells/nor3/sky130_fd_sc_hs__nor3_1.pxi.spice
index 54f94d4..114371a 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_1.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_1.pxi.spice
-* Created: Thu Aug 27 20:53:51 2020
+* Created: Tue Sep  1 20:11:26 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR3_1%A N_A_c_38_n N_A_M1004_g N_A_c_39_n N_A_M1001_g A A
 + PM_SKY130_FD_SC_HS__NOR3_1%A

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_1.spice b/cells/nor3/sky130_fd_sc_hs__nor3_1.spice
index 1b4f6f0..809165b 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_1.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_1.spice
-* Created: Thu Aug 27 20:53:51 2020
+* Created: Tue Sep  1 20:11:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_2.lvs.report b/cells/nor3/sky130_fd_sc_hs__nor3_2.lvs.report
new file mode 100644
index 0000000..2cc619d
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor3_2.sp ('sky130_fd_sc_hs__nor3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor3/sky130_fd_sc_hs__nor3_2.spice ('sky130_fd_sc_hs__nor3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:29 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor3_2       sky130_fd_sc_hs__nor3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        10         9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   6 layout mos transistors were reduced to 3.
+     3 mos transistors were deleted by parallel reduction.
+   6 source mos transistors were reduced to 3.
+     3 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_2.pex.spice b/cells/nor3/sky130_fd_sc_hs__nor3_2.pex.spice
index ede24d8..0548500 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_2.pex.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_2.pex.spice
-* Created: Thu Aug 27 20:54:02 2020
+* Created: Tue Sep  1 20:11:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_2.pxi.spice b/cells/nor3/sky130_fd_sc_hs__nor3_2.pxi.spice
index 1890c19..dd33199 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_2.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_2.pxi.spice
-* Created: Thu Aug 27 20:54:02 2020
+* Created: Tue Sep  1 20:11:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR3_2%C N_C_c_57_n N_C_M1006_g N_C_c_60_n N_C_M1000_g
 + N_C_c_61_n N_C_M1003_g C N_C_c_59_n PM_SKY130_FD_SC_HS__NOR3_2%C

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_2.spice b/cells/nor3/sky130_fd_sc_hs__nor3_2.spice
index 75fe4ce..992661c 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_2.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_2.spice
-* Created: Thu Aug 27 20:54:02 2020
+* Created: Tue Sep  1 20:11:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_4.lvs.report b/cells/nor3/sky130_fd_sc_hs__nor3_4.lvs.report
new file mode 100644
index 0000000..aca5a64
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor3_4.sp ('sky130_fd_sc_hs__nor3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor3/sky130_fd_sc_hs__nor3_4.spice ('sky130_fd_sc_hs__nor3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:35 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor3_4       sky130_fd_sc_hs__nor3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          6         6         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   18 layout mos transistors were reduced to 6.
+     12 mos transistors were deleted by parallel reduction.
+   18 source mos transistors were reduced to 6.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_4.pex.spice b/cells/nor3/sky130_fd_sc_hs__nor3_4.pex.spice
index 170208e..8e7bfcc 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_4.pex.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_4.pex.spice
-* Created: Thu Aug 27 20:54:09 2020
+* Created: Tue Sep  1 20:11:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_4.pxi.spice b/cells/nor3/sky130_fd_sc_hs__nor3_4.pxi.spice
index d3f6de5..2b946d2 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_4.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_4.pxi.spice
-* Created: Thu Aug 27 20:54:09 2020
+* Created: Tue Sep  1 20:11:38 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR3_4%A N_A_M1004_g N_A_c_115_n N_A_M1005_g N_A_M1016_g
 + N_A_c_116_n N_A_M1006_g N_A_c_117_n N_A_M1012_g N_A_c_118_n N_A_M1013_g

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_4.spice b/cells/nor3/sky130_fd_sc_hs__nor3_4.spice
index 34d3d18..f130393 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_4.spice
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3_4.spice
-* Created: Thu Aug 27 20:54:09 2020
+* Created: Tue Sep  1 20:11:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.lvs.report b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.lvs.report
new file mode 100644
index 0000000..e6a8200
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor3b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor3b_1.sp ('sky130_fd_sc_hs__nor3b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor3b/sky130_fd_sc_hs__nor3b_1.spice ('sky130_fd_sc_hs__nor3b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor3b_1      sky130_fd_sc_hs__nor3b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor3b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N A B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pex.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pex.spice
index 8df9164..a1123a9 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_1.pex.spice
-* Created: Thu Aug 27 20:54:17 2020
+* Created: Tue Sep  1 20:11:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pxi.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pxi.spice
index 0b3e8bd..286ebe7 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_1.pxi.spice
-* Created: Thu Aug 27 20:54:17 2020
+* Created: Tue Sep  1 20:11:44 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR3B_1%C_N N_C_N_c_48_n N_C_N_M1001_g N_C_N_c_49_n
 + N_C_N_M1005_g C_N PM_SKY130_FD_SC_HS__NOR3B_1%C_N

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.spice
index bb0d69c..1c0a6e8 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_1.spice
-* Created: Thu Aug 27 20:54:17 2020
+* Created: Tue Sep  1 20:11:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.lvs.report b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.lvs.report
new file mode 100644
index 0000000..f607b7e
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor3b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor3b_2.sp ('sky130_fd_sc_hs__nor3b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor3b/sky130_fd_sc_hs__nor3b_2.spice ('sky130_fd_sc_hs__nor3b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor3b_2      sky130_fd_sc_hs__nor3b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor3b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pex.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pex.spice
index 72baee9..f24a424 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_2.pex.spice
-* Created: Thu Aug 27 20:54:24 2020
+* Created: Tue Sep  1 20:11:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pxi.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pxi.spice
index 7112b9c..fde7b44 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_2.pxi.spice
-* Created: Thu Aug 27 20:54:24 2020
+* Created: Tue Sep  1 20:11:50 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR3B_2%C_N N_C_N_M1005_g N_C_N_c_81_n N_C_N_M1004_g C_N
 + PM_SKY130_FD_SC_HS__NOR3B_2%C_N

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.spice
index 65cddfd..cb0e76d 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_2.spice
-* Created: Thu Aug 27 20:54:24 2020
+* Created: Tue Sep  1 20:11:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.lvs.report b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.lvs.report
new file mode 100644
index 0000000..320bb28
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor3b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor3b_4.sp ('sky130_fd_sc_hs__nor3b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor3b/sky130_fd_sc_hs__nor3b_4.spice ('sky130_fd_sc_hs__nor3b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:11:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor3b_4      sky130_fd_sc_hs__nor3b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor3b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         13        13         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        28        27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   26 layout mos transistors were reduced to 7.
+     19 mos transistors were deleted by parallel reduction.
+   26 source mos transistors were reduced to 7.
+     19 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A C_N Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pex.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pex.spice
index 8198f0c..172a06d 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_4.pex.spice
-* Created: Thu Aug 27 20:54:32 2020
+* Created: Tue Sep  1 20:11:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pxi.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pxi.spice
index c427872..a5dd5bd 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_4.pxi.spice
-* Created: Thu Aug 27 20:54:32 2020
+* Created: Tue Sep  1 20:11:56 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR3B_4%B N_B_M1003_g N_B_c_118_n N_B_M1010_g N_B_M1008_g
 + N_B_c_119_n N_B_M1012_g N_B_c_120_n N_B_M1014_g N_B_M1024_g N_B_c_121_n

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.spice b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.spice
index c46e74a..c0dcb6a 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.spice
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor3b_4.spice
-* Created: Thu Aug 27 20:54:32 2020
+* Created: Tue Sep  1 20:11:56 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_1.lvs.report b/cells/nor4/sky130_fd_sc_hs__nor4_1.lvs.report
new file mode 100644
index 0000000..addcd22
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4_1.sp ('sky130_fd_sc_hs__nor4_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4/sky130_fd_sc_hs__nor4_1.spice ('sky130_fd_sc_hs__nor4_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4_1       sky130_fd_sc_hs__nor4_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_1.pex.spice b/cells/nor4/sky130_fd_sc_hs__nor4_1.pex.spice
index 4c6d5ef..c5ec6b7 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_1.pex.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_1.pex.spice
-* Created: Thu Aug 27 20:54:40 2020
+* Created: Tue Sep  1 20:12:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_1.pxi.spice b/cells/nor4/sky130_fd_sc_hs__nor4_1.pxi.spice
index aad660b..9450e40 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_1.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_1.pxi.spice
-* Created: Thu Aug 27 20:54:40 2020
+* Created: Tue Sep  1 20:12:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4_1%A N_A_c_48_n N_A_M1004_g N_A_M1001_g N_A_c_45_n
 + N_A_c_46_n A N_A_c_47_n PM_SKY130_FD_SC_HS__NOR4_1%A

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_1.spice b/cells/nor4/sky130_fd_sc_hs__nor4_1.spice
index 31efaaf..e5cb88d 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_1.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_1.spice
-* Created: Thu Aug 27 20:54:40 2020
+* Created: Tue Sep  1 20:12:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_2.lvs.report b/cells/nor4/sky130_fd_sc_hs__nor4_2.lvs.report
new file mode 100644
index 0000000..7d8cde5
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4_2.sp ('sky130_fd_sc_hs__nor4_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4/sky130_fd_sc_hs__nor4_2.spice ('sky130_fd_sc_hs__nor4_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4_2       sky130_fd_sc_hs__nor4_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C D B A Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_2.pex.spice b/cells/nor4/sky130_fd_sc_hs__nor4_2.pex.spice
index 172a7ec..d3cff9c 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_2.pex.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_2.pex.spice
-* Created: Thu Aug 27 20:54:48 2020
+* Created: Tue Sep  1 20:12:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_2.pxi.spice b/cells/nor4/sky130_fd_sc_hs__nor4_2.pxi.spice
index 9d72819..87b88e4 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_2.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_2.pxi.spice
-* Created: Thu Aug 27 20:54:48 2020
+* Created: Tue Sep  1 20:12:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4_2%C N_C_c_78_n N_C_c_87_n N_C_M1002_g N_C_c_79_n
 + N_C_M1008_g N_C_M1007_g N_C_c_81_n N_C_c_82_n C C N_C_c_83_n C N_C_c_85_n

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_2.spice b/cells/nor4/sky130_fd_sc_hs__nor4_2.spice
index 2c2b582..41d0626 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_2.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_2.spice
-* Created: Thu Aug 27 20:54:48 2020
+* Created: Tue Sep  1 20:12:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_4.lvs.report b/cells/nor4/sky130_fd_sc_hs__nor4_4.lvs.report
new file mode 100644
index 0000000..55ee0eb
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4_4.sp ('sky130_fd_sc_hs__nor4_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4/sky130_fd_sc_hs__nor4_4.spice ('sky130_fd_sc_hs__nor4_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:12 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4_4       sky130_fd_sc_hs__nor4_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 8.
+     16 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 8.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D C B A Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_4.pex.spice b/cells/nor4/sky130_fd_sc_hs__nor4_4.pex.spice
index 4996a7a..8821bfc 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_4.pex.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_4.pex.spice
-* Created: Thu Aug 27 20:54:56 2020
+* Created: Tue Sep  1 20:12:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_4.pxi.spice b/cells/nor4/sky130_fd_sc_hs__nor4_4.pxi.spice
index a69df71..397635f 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_4.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_4.pxi.spice
-* Created: Thu Aug 27 20:54:56 2020
+* Created: Tue Sep  1 20:12:15 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4_4%D N_D_M1003_g N_D_c_105_n N_D_M1008_g N_D_c_106_n
 + N_D_M1009_g N_D_c_107_n N_D_M1011_g N_D_M1021_g N_D_c_108_n N_D_M1013_g D D D

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_4.spice b/cells/nor4/sky130_fd_sc_hs__nor4_4.spice
index 378dde1..f8b313e 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_4.spice
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4_4.spice
-* Created: Thu Aug 27 20:54:56 2020
+* Created: Tue Sep  1 20:12:15 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.lvs.report b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.lvs.report
new file mode 100644
index 0000000..fae61c1
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4b_1.sp ('sky130_fd_sc_hs__nor4b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4b/sky130_fd_sc_hs__nor4b_1.spice ('sky130_fd_sc_hs__nor4b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4b_1      sky130_fd_sc_hs__nor4b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pex.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pex.spice
index 977087d..642a842 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_1.pex.spice
-* Created: Thu Aug 27 20:55:06 2020
+* Created: Tue Sep  1 20:12:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pxi.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pxi.spice
index 28b02a4..52bd51f 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_1.pxi.spice
-* Created: Thu Aug 27 20:55:06 2020
+* Created: Tue Sep  1 20:12:21 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4B_1%D_N N_D_N_c_58_n N_D_N_c_63_n N_D_N_M1002_g
 + N_D_N_M1008_g D_N N_D_N_c_61_n PM_SKY130_FD_SC_HS__NOR4B_1%D_N

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.spice
index 68b44ce..6cebb9f 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_1.spice
-* Created: Thu Aug 27 20:55:06 2020
+* Created: Tue Sep  1 20:12:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.lvs.report b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.lvs.report
new file mode 100644
index 0000000..69203b1
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4b_2.sp ('sky130_fd_sc_hs__nor4b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4b/sky130_fd_sc_hs__nor4b_2.spice ('sky130_fd_sc_hs__nor4b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4b_2      sky130_fd_sc_hs__nor4b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pex.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pex.spice
index 4bb01ac..32cc046 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_2.pex.spice
-* Created: Thu Aug 27 20:55:14 2020
+* Created: Tue Sep  1 20:12:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pxi.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pxi.spice
index 5cad437..7ccb827 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_2.pxi.spice
-* Created: Thu Aug 27 20:55:14 2020
+* Created: Tue Sep  1 20:12:27 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4B_2%D_N N_D_N_c_95_n N_D_N_M1008_g N_D_N_M1002_g D_N
 + PM_SKY130_FD_SC_HS__NOR4B_2%D_N

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.spice
index ba70e98..b3613ad 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_2.spice
-* Created: Thu Aug 27 20:55:14 2020
+* Created: Tue Sep  1 20:12:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.lvs.report b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.lvs.report
new file mode 100644
index 0000000..35c96d4
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4b_4.sp ('sky130_fd_sc_hs__nor4b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4b/sky130_fd_sc_hs__nor4b_4.spice ('sky130_fd_sc_hs__nor4b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4b_4      sky130_fd_sc_hs__nor4b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         17        17         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        36        35
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   34 layout mos transistors were reduced to 9.
+     25 mos transistors were deleted by parallel reduction.
+   34 source mos transistors were reduced to 9.
+     25 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pex.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pex.spice
index c8ffacd..e458f8e 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_4.pex.spice
-* Created: Thu Aug 27 20:55:22 2020
+* Created: Tue Sep  1 20:12:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pxi.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pxi.spice
index d84c352..6efde6b 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_4.pxi.spice
-* Created: Thu Aug 27 20:55:22 2020
+* Created: Tue Sep  1 20:12:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4B_4%D_N N_D_N_c_153_n N_D_N_M1028_g N_D_N_c_154_n
 + N_D_N_M1029_g N_D_N_c_150_n N_D_N_M1023_g D_N D_N N_D_N_c_151_n N_D_N_c_152_n

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.spice b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.spice
index 14580bc..2fd45e9 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.spice
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4b_4.spice
-* Created: Thu Aug 27 20:55:22 2020
+* Created: Tue Sep  1 20:12:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.lvs.report b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.lvs.report
new file mode 100644
index 0000000..fa07f6b
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4bb_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4bb_1.sp ('sky130_fd_sc_hs__nor4bb_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.spice ('sky130_fd_sc_hs__nor4bb_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:37 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4bb_1     sky130_fd_sc_hs__nor4bb_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4bb_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N A B D_N VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pex.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pex.spice
index 03b7a0b..fa8fc62 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_1.pex.spice
-* Created: Thu Aug 27 20:55:29 2020
+* Created: Tue Sep  1 20:12:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pxi.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pxi.spice
index 6e29e88..983f997 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_1.pxi.spice
-* Created: Thu Aug 27 20:55:29 2020
+* Created: Tue Sep  1 20:12:40 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4BB_1%C_N N_C_N_c_75_n N_C_N_M1009_g N_C_N_c_72_n
 + N_C_N_M1001_g C_N N_C_N_c_74_n PM_SKY130_FD_SC_HS__NOR4BB_1%C_N

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.spice
index cb2908d..d594a2e 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_1.spice
-* Created: Thu Aug 27 20:55:29 2020
+* Created: Tue Sep  1 20:12:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.lvs.report b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.lvs.report
new file mode 100644
index 0000000..b90e9a5
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4bb_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4bb_2.sp ('sky130_fd_sc_hs__nor4bb_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.spice ('sky130_fd_sc_hs__nor4bb_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4bb_2     sky130_fd_sc_hs__nor4bb_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4bb_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N D_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pex.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pex.spice
index 3ed825d..2668988 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_2.pex.spice
-* Created: Thu Aug 27 20:55:37 2020
+* Created: Tue Sep  1 20:12:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pxi.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pxi.spice
index c887bb3..ca8cc45 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_2.pxi.spice
-* Created: Thu Aug 27 20:55:37 2020
+* Created: Tue Sep  1 20:12:46 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4BB_2%C_N N_C_N_c_110_n N_C_N_M1005_g N_C_N_M1019_g C_N
 + C_N N_C_N_c_109_n PM_SKY130_FD_SC_HS__NOR4BB_2%C_N

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.spice
index 95fdbb7..40a95fc 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_2.spice
-* Created: Thu Aug 27 20:55:37 2020
+* Created: Tue Sep  1 20:12:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.lvs.report b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.lvs.report
new file mode 100644
index 0000000..2fa20fd
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__nor4bb_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__nor4bb_4.sp ('sky130_fd_sc_hs__nor4bb_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.spice ('sky130_fd_sc_hs__nor4bb_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__nor4bb_4     sky130_fd_sc_hs__nor4bb_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__nor4bb_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__nor4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         18        18         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   36 layout mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+   36 source mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A C_N D_N VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pex.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pex.spice
index a409455..26f4254 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_4.pex.spice
-* Created: Thu Aug 27 20:55:45 2020
+* Created: Tue Sep  1 20:12:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pxi.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pxi.spice
index aa189d2..caf18d6 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_4.pxi.spice
-* Created: Thu Aug 27 20:55:45 2020
+* Created: Tue Sep  1 20:12:52 2020
 * 
 x_PM_SKY130_FD_SC_HS__NOR4BB_4%B N_B_c_185_n N_B_M1010_g N_B_M1001_g N_B_M1020_g
 + N_B_c_195_n N_B_M1012_g N_B_c_196_n N_B_M1015_g N_B_M1028_g N_B_c_197_n

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.spice b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.spice
index f2f06ed..69b1729 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.spice
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__nor4bb_4.spice
-* Created: Thu Aug 27 20:55:45 2020
+* Created: Tue Sep  1 20:12:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.lvs.report b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.lvs.report
new file mode 100644
index 0000000..83831ef
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2111a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2111a_1.sp ('sky130_fd_sc_hs__o2111a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2111a/sky130_fd_sc_hs__o2111a_1.spice ('sky130_fd_sc_hs__o2111a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:12:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2111a_1     sky130_fd_sc_hs__o2111a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2111a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2111a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pex.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pex.spice
index bedff29..8c9deec 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_1.pex.spice
-* Created: Thu Aug 27 20:55:54 2020
+* Created: Tue Sep  1 20:12:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pxi.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pxi.spice
index f0f06f8..0fd65da 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_1.pxi.spice
-* Created: Thu Aug 27 20:55:54 2020
+* Created: Tue Sep  1 20:12:58 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2111A_1%A_82_48# N_A_82_48#_M1011_s N_A_82_48#_M1003_d
 + N_A_82_48#_M1005_d N_A_82_48#_c_69_n N_A_82_48#_M1006_g N_A_82_48#_c_70_n

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.spice
index 411fcd1..22db261 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_1.spice
-* Created: Thu Aug 27 20:55:54 2020
+* Created: Tue Sep  1 20:12:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.lvs.report b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.lvs.report
new file mode 100644
index 0000000..42f8a6e
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2111a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2111a_2.sp ('sky130_fd_sc_hs__o2111a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2111a/sky130_fd_sc_hs__o2111a_2.spice ('sky130_fd_sc_hs__o2111a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2111a_2     sky130_fd_sc_hs__o2111a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2111a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2111a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 D1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pex.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pex.spice
index 69d6c7d..447a9a6 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_2.pex.spice
-* Created: Thu Aug 27 20:56:01 2020
+* Created: Tue Sep  1 20:13:04 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pxi.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pxi.spice
index ee7fa50..9387584 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_2.pxi.spice
-* Created: Thu Aug 27 20:56:01 2020
+* Created: Tue Sep  1 20:13:04 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2111A_2%A1 N_A1_c_73_n N_A1_c_77_n N_A1_M1000_g
 + N_A1_M1010_g A1 A1 N_A1_c_75_n PM_SKY130_FD_SC_HS__O2111A_2%A1

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.spice
index 9548d35..2e668d1 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_2.spice
-* Created: Thu Aug 27 20:56:01 2020
+* Created: Tue Sep  1 20:13:04 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.lvs.report b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.lvs.report
new file mode 100644
index 0000000..3aa9bc4
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2111a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2111a_4.sp ('sky130_fd_sc_hs__o2111a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2111a/sky130_fd_sc_hs__o2111a_4.spice ('sky130_fd_sc_hs__o2111a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2111a_4     sky130_fd_sc_hs__o2111a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2111a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2111a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pex.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pex.spice
index 6f8bf5d..41d6ab2 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_4.pex.spice
-* Created: Thu Aug 27 20:56:12 2020
+* Created: Tue Sep  1 20:13:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pxi.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pxi.spice
index 1f582c1..ba45560 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_4.pxi.spice
-* Created: Thu Aug 27 20:56:12 2020
+* Created: Tue Sep  1 20:13:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2111A_4%D1 N_D1_M1019_g N_D1_c_150_n N_D1_M1004_g
 + N_D1_c_151_n N_D1_M1020_g N_D1_c_157_n N_D1_M1011_g N_D1_c_153_n D1

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.spice b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.spice
index b896135..b1c15f0 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.spice
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111a_4.spice
-* Created: Thu Aug 27 20:56:12 2020
+* Created: Tue Sep  1 20:13:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.lvs.report b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.lvs.report
new file mode 100644
index 0000000..f7ae943
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2111ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2111ai_1.sp ('sky130_fd_sc_hs__o2111ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.spice ('sky130_fd_sc_hs__o2111ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:14 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2111ai_1    sky130_fd_sc_hs__o2111ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2111ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2111ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pex.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pex.spice
index c1cf825..8f8f0c3 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_1.pex.spice
-* Created: Thu Aug 27 20:56:19 2020
+* Created: Tue Sep  1 20:13:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pxi.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pxi.spice
index e9ebe1e..ffda033 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_1.pxi.spice
-* Created: Thu Aug 27 20:56:19 2020
+* Created: Tue Sep  1 20:13:17 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2111AI_1%D1 N_D1_c_49_n N_D1_M1001_g N_D1_c_50_n
 + N_D1_M1006_g D1 PM_SKY130_FD_SC_HS__O2111AI_1%D1

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.spice
index f6c590d..20da948 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_1.spice
-* Created: Thu Aug 27 20:56:19 2020
+* Created: Tue Sep  1 20:13:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.lvs.report b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.lvs.report
new file mode 100644
index 0000000..7309f2c
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2111ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2111ai_2.sp ('sky130_fd_sc_hs__o2111ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.spice ('sky130_fd_sc_hs__o2111ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2111ai_2    sky130_fd_sc_hs__o2111ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2111ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2111ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pex.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pex.spice
index 23d7e7f..676ce42 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_2.pex.spice
-* Created: Thu Aug 27 20:56:27 2020
+* Created: Tue Sep  1 20:13:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pxi.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pxi.spice
index f02c71c..621d82d 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_2.pxi.spice
-* Created: Thu Aug 27 20:56:27 2020
+* Created: Tue Sep  1 20:13:23 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2111AI_2%D1 N_D1_c_105_n N_D1_M1018_g N_D1_c_100_n
 + N_D1_M1012_g N_D1_c_101_n N_D1_M1014_g N_D1_c_106_n N_D1_M1019_g N_D1_c_102_n

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.spice
index 2f47267..4ca25fb 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_2.spice
-* Created: Thu Aug 27 20:56:27 2020
+* Created: Tue Sep  1 20:13:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.lvs.report b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.lvs.report
new file mode 100644
index 0000000..29d441a
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2111ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2111ai_4.sp ('sky130_fd_sc_hs__o2111ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.spice ('sky130_fd_sc_hs__o2111ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2111ai_4    sky130_fd_sc_hs__o2111ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2111ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2111ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   34 layout mos transistors were reduced to 10.
+     24 mos transistors were deleted by parallel reduction.
+   34 source mos transistors were reduced to 10.
+     24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pex.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pex.spice
index 304eadb..2363082 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_4.pex.spice
-* Created: Thu Aug 27 20:56:35 2020
+* Created: Tue Sep  1 20:13:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pxi.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pxi.spice
index e852096..41e2238 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_4.pxi.spice
-* Created: Thu Aug 27 20:56:35 2020
+* Created: Tue Sep  1 20:13:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2111AI_4%D1 N_D1_c_140_n N_D1_M1011_g N_D1_c_141_n
 + N_D1_M1013_g N_D1_c_146_n N_D1_M1020_g N_D1_c_142_n N_D1_M1030_g N_D1_c_147_n

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.spice b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.spice
index ea784c2..525c61e 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.spice
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2111ai_4.spice
-* Created: Thu Aug 27 20:56:35 2020
+* Created: Tue Sep  1 20:13:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_1.lvs.report b/cells/o211a/sky130_fd_sc_hs__o211a_1.lvs.report
new file mode 100644
index 0000000..25d1a7f
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o211a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o211a_1.sp ('sky130_fd_sc_hs__o211a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o211a/sky130_fd_sc_hs__o211a_1.spice ('sky130_fd_sc_hs__o211a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o211a_1      sky130_fd_sc_hs__o211a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o211a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o211a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_1.pex.spice b/cells/o211a/sky130_fd_sc_hs__o211a_1.pex.spice
index 166202c..6e20ffc 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_1.pex.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_1.pex.spice
-* Created: Thu Aug 27 20:56:42 2020
+* Created: Tue Sep  1 20:13:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_1.pxi.spice b/cells/o211a/sky130_fd_sc_hs__o211a_1.pxi.spice
index eda3db7..4249b18 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_1.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_1.pxi.spice
-* Created: Thu Aug 27 20:56:42 2020
+* Created: Tue Sep  1 20:13:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__O211A_1%A_83_264# N_A_83_264#_M1000_d N_A_83_264#_M1001_d
 + N_A_83_264#_M1009_d N_A_83_264#_M1008_g N_A_83_264#_c_70_n N_A_83_264#_M1005_g

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_1.spice b/cells/o211a/sky130_fd_sc_hs__o211a_1.spice
index 73e57be..3dc8418 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_1.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_1.spice
-* Created: Thu Aug 27 20:56:42 2020
+* Created: Tue Sep  1 20:13:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_2.lvs.report b/cells/o211a/sky130_fd_sc_hs__o211a_2.lvs.report
new file mode 100644
index 0000000..930a295
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o211a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o211a_2.sp ('sky130_fd_sc_hs__o211a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o211a/sky130_fd_sc_hs__o211a_2.spice ('sky130_fd_sc_hs__o211a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o211a_2      sky130_fd_sc_hs__o211a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o211a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o211a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_2.pex.spice b/cells/o211a/sky130_fd_sc_hs__o211a_2.pex.spice
index 0ccdd49..2011fde 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_2.pex.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_2.pex.spice
-* Created: Thu Aug 27 20:56:50 2020
+* Created: Tue Sep  1 20:13:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_2.pxi.spice b/cells/o211a/sky130_fd_sc_hs__o211a_2.pxi.spice
index a398369..0f49e08 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_2.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_2.pxi.spice
-* Created: Thu Aug 27 20:56:50 2020
+* Created: Tue Sep  1 20:13:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__O211A_2%C1 N_C1_c_63_n N_C1_M1002_g N_C1_c_64_n
 + N_C1_M1011_g C1 PM_SKY130_FD_SC_HS__O211A_2%C1

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_2.spice b/cells/o211a/sky130_fd_sc_hs__o211a_2.spice
index a10d40d..fb1e53d 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_2.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_2.spice
-* Created: Thu Aug 27 20:56:50 2020
+* Created: Tue Sep  1 20:13:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_4.lvs.report b/cells/o211a/sky130_fd_sc_hs__o211a_4.lvs.report
new file mode 100644
index 0000000..0f90937
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o211a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o211a_4.sp ('sky130_fd_sc_hs__o211a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o211a/sky130_fd_sc_hs__o211a_4.spice ('sky130_fd_sc_hs__o211a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o211a_4      sky130_fd_sc_hs__o211a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o211a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o211a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_4.pex.spice b/cells/o211a/sky130_fd_sc_hs__o211a_4.pex.spice
index a40cdb5..88f835b 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_4.pex.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_4.pex.spice
-* Created: Thu Aug 27 20:56:59 2020
+* Created: Tue Sep  1 20:13:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_4.pxi.spice b/cells/o211a/sky130_fd_sc_hs__o211a_4.pxi.spice
index 3ff5b57..decad65 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_4.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_4.pxi.spice
-* Created: Thu Aug 27 20:56:59 2020
+* Created: Tue Sep  1 20:13:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__O211A_4%A_91_48# N_A_91_48#_M1015_s N_A_91_48#_M1002_d
 + N_A_91_48#_M1018_s N_A_91_48#_M1004_s N_A_91_48#_M1000_g N_A_91_48#_c_140_n

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_4.spice b/cells/o211a/sky130_fd_sc_hs__o211a_4.spice
index ad3bac5..ef201ac 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_4.spice
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211a_4.spice
-* Created: Thu Aug 27 20:56:59 2020
+* Created: Tue Sep  1 20:13:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.lvs.report b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.lvs.report
new file mode 100644
index 0000000..7d148be
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o211ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o211ai_1.sp ('sky130_fd_sc_hs__o211ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o211ai/sky130_fd_sc_hs__o211ai_1.spice ('sky130_fd_sc_hs__o211ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:51 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o211ai_1     sky130_fd_sc_hs__o211ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o211ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o211ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pex.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pex.spice
index 0ae5636..d20937d 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_1.pex.spice
-* Created: Thu Aug 27 20:57:06 2020
+* Created: Tue Sep  1 20:13:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pxi.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pxi.spice
index 0143e39..8a70293 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_1.pxi.spice
-* Created: Thu Aug 27 20:57:06 2020
+* Created: Tue Sep  1 20:13:54 2020
 * 
 x_PM_SKY130_FD_SC_HS__O211AI_1%A1 N_A1_c_46_n N_A1_M1005_g N_A1_M1006_g A1
 + N_A1_c_48_n PM_SKY130_FD_SC_HS__O211AI_1%A1

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.spice
index fe50cc8..03f18fd 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_1.spice
-* Created: Thu Aug 27 20:57:06 2020
+* Created: Tue Sep  1 20:13:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.lvs.report b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.lvs.report
new file mode 100644
index 0000000..acc04e0
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o211ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o211ai_2.sp ('sky130_fd_sc_hs__o211ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o211ai/sky130_fd_sc_hs__o211ai_2.spice ('sky130_fd_sc_hs__o211ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:13:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o211ai_2     sky130_fd_sc_hs__o211ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o211ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o211ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pex.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pex.spice
index 36cb80d..0a123f4 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_2.pex.spice
-* Created: Thu Aug 27 20:57:17 2020
+* Created: Tue Sep  1 20:14:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pxi.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pxi.spice
index 5cebf39..e11598b 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_2.pxi.spice
-* Created: Thu Aug 27 20:57:17 2020
+* Created: Tue Sep  1 20:14:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__O211AI_2%C1 N_C1_M1003_g N_C1_c_88_n N_C1_M1009_g
 + N_C1_M1004_g N_C1_c_89_n N_C1_M1010_g C1 N_C1_c_86_n N_C1_c_87_n

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.spice
index 0590522..0a34936 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_2.spice
-* Created: Thu Aug 27 20:57:17 2020
+* Created: Tue Sep  1 20:14:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.lvs.report b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.lvs.report
new file mode 100644
index 0000000..08628dc
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o211ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o211ai_4.sp ('sky130_fd_sc_hs__o211ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o211ai/sky130_fd_sc_hs__o211ai_4.spice ('sky130_fd_sc_hs__o211ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o211ai_4     sky130_fd_sc_hs__o211ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o211ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o211ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         16        16         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pex.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pex.spice
index 425fff7..ab5d4b1 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_4.pex.spice
-* Created: Thu Aug 27 20:57:25 2020
+* Created: Tue Sep  1 20:14:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pxi.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pxi.spice
index eea98bd..10f9123 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_4.pxi.spice
-* Created: Thu Aug 27 20:57:25 2020
+* Created: Tue Sep  1 20:14:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__O211AI_4%A1 N_A1_M1010_g N_A1_c_133_n N_A1_M1020_g
 + N_A1_c_134_n N_A1_M1021_g N_A1_M1014_g N_A1_c_135_n N_A1_M1024_g N_A1_M1019_g

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.spice b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.spice
index f2c848a..c252b4e 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.spice
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o211ai_4.spice
-* Created: Thu Aug 27 20:57:25 2020
+* Created: Tue Sep  1 20:14:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_1.lvs.report b/cells/o21a/sky130_fd_sc_hs__o21a_1.lvs.report
new file mode 100644
index 0000000..08fa18d
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21a_1.sp ('sky130_fd_sc_hs__o21a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21a/sky130_fd_sc_hs__o21a_1.spice ('sky130_fd_sc_hs__o21a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21a_1       sky130_fd_sc_hs__o21a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_1.pex.spice b/cells/o21a/sky130_fd_sc_hs__o21a_1.pex.spice
index 059e0aa..e21c487 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_1.pex.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_1.pex.spice
-* Created: Thu Aug 27 20:57:33 2020
+* Created: Tue Sep  1 20:14:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_1.pxi.spice b/cells/o21a/sky130_fd_sc_hs__o21a_1.pxi.spice
index 7aa1ad8..9d0a1de 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_1.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_1.pxi.spice
-* Created: Thu Aug 27 20:57:33 2020
+* Created: Tue Sep  1 20:14:12 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21A_1%A_83_244# N_A_83_244#_M1002_s N_A_83_244#_M1004_d
 + N_A_83_244#_c_50_n N_A_83_244#_M1006_g N_A_83_244#_c_51_n N_A_83_244#_M1005_g

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_1.spice b/cells/o21a/sky130_fd_sc_hs__o21a_1.spice
index 22661d8..c12011b 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_1.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_1.spice
-* Created: Thu Aug 27 20:57:33 2020
+* Created: Tue Sep  1 20:14:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_2.lvs.report b/cells/o21a/sky130_fd_sc_hs__o21a_2.lvs.report
new file mode 100644
index 0000000..2de9ac4
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21a_2.sp ('sky130_fd_sc_hs__o21a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21a/sky130_fd_sc_hs__o21a_2.spice ('sky130_fd_sc_hs__o21a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21a_2       sky130_fd_sc_hs__o21a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_2.pex.spice b/cells/o21a/sky130_fd_sc_hs__o21a_2.pex.spice
index 56bac7a..038557c 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_2.pex.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_2.pex.spice
-* Created: Thu Aug 27 20:57:40 2020
+* Created: Tue Sep  1 20:14:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_2.pxi.spice b/cells/o21a/sky130_fd_sc_hs__o21a_2.pxi.spice
index d21b644..2bbc98e 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_2.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_2.pxi.spice
-* Created: Thu Aug 27 20:57:40 2020
+* Created: Tue Sep  1 20:14:18 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21A_2%A1 N_A1_c_59_n N_A1_M1006_g N_A1_c_60_n
 + N_A1_M1001_g N_A1_c_61_n A1 A1 PM_SKY130_FD_SC_HS__O21A_2%A1

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_2.spice b/cells/o21a/sky130_fd_sc_hs__o21a_2.spice
index 31079e3..77eed8c 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_2.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_2.spice
-* Created: Thu Aug 27 20:57:40 2020
+* Created: Tue Sep  1 20:14:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_4.lvs.report b/cells/o21a/sky130_fd_sc_hs__o21a_4.lvs.report
new file mode 100644
index 0000000..3456540
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21a_4.sp ('sky130_fd_sc_hs__o21a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21a/sky130_fd_sc_hs__o21a_4.spice ('sky130_fd_sc_hs__o21a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21a_4       sky130_fd_sc_hs__o21a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_4.pex.spice b/cells/o21a/sky130_fd_sc_hs__o21a_4.pex.spice
index 515f40b..6bde859 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_4.pex.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_4.pex.spice
-* Created: Thu Aug 27 20:57:48 2020
+* Created: Tue Sep  1 20:14:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_4.pxi.spice b/cells/o21a/sky130_fd_sc_hs__o21a_4.pxi.spice
index fefe8c1..0b89358 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_4.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_4.pxi.spice
-* Created: Thu Aug 27 20:57:48 2020
+* Created: Tue Sep  1 20:14:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21A_4%A2 N_A2_M1005_g N_A2_c_104_n N_A2_M1015_g
 + N_A2_M1006_g N_A2_c_105_n N_A2_M1018_g A2 N_A2_c_102_n N_A2_c_103_n

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_4.spice b/cells/o21a/sky130_fd_sc_hs__o21a_4.spice
index e4f744d..d7bcd76 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_4.spice
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21a_4.spice
-* Created: Thu Aug 27 20:57:48 2020
+* Created: Tue Sep  1 20:14:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.lvs.report b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.lvs.report
new file mode 100644
index 0000000..8249f12
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21ai_1.sp ('sky130_fd_sc_hs__o21ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21ai/sky130_fd_sc_hs__o21ai_1.spice ('sky130_fd_sc_hs__o21ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:27 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21ai_1      sky130_fd_sc_hs__o21ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pex.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pex.spice
index 9435881..911b071 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_1.pex.spice
-* Created: Thu Aug 27 20:57:55 2020
+* Created: Tue Sep  1 20:14:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pxi.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pxi.spice
index 9674ea0..195bc40 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_1.pxi.spice
-* Created: Thu Aug 27 20:57:55 2020
+* Created: Tue Sep  1 20:14:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21AI_1%A1 N_A1_c_36_n N_A1_M1004_g N_A1_c_37_n
 + N_A1_M1005_g A1 N_A1_c_38_n PM_SKY130_FD_SC_HS__O21AI_1%A1

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.spice
index 3fb2017..1b760e6 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_1.spice
-* Created: Thu Aug 27 20:57:55 2020
+* Created: Tue Sep  1 20:14:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.lvs.report b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.lvs.report
new file mode 100644
index 0000000..665fa30
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21ai_2.sp ('sky130_fd_sc_hs__o21ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21ai/sky130_fd_sc_hs__o21ai_2.spice ('sky130_fd_sc_hs__o21ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:33 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21ai_2      sky130_fd_sc_hs__o21ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pex.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pex.spice
index 94e1602..61b5b5b 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_2.pex.spice
-* Created: Thu Aug 27 20:58:04 2020
+* Created: Tue Sep  1 20:14:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pxi.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pxi.spice
index c7f8688..95803f5 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_2.pxi.spice
-* Created: Thu Aug 27 20:58:04 2020
+* Created: Tue Sep  1 20:14:36 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21AI_2%A1 N_A1_M1009_g N_A1_c_63_n N_A1_M1002_g
 + N_A1_M1010_g N_A1_c_65_n N_A1_M1005_g N_A1_c_66_n N_A1_c_74_p N_A1_c_96_p A1

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.spice
index 453075e..36b7db6 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_2.spice
-* Created: Thu Aug 27 20:58:04 2020
+* Created: Tue Sep  1 20:14:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.lvs.report b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.lvs.report
new file mode 100644
index 0000000..3146d87
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21ai_4.sp ('sky130_fd_sc_hs__o21ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21ai/sky130_fd_sc_hs__o21ai_4.spice ('sky130_fd_sc_hs__o21ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:40 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21ai_4      sky130_fd_sc_hs__o21ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:         12        12         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   22 layout mos transistors were reduced to 6.
+     16 mos transistors were deleted by parallel reduction.
+   22 source mos transistors were reduced to 6.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 B1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pex.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pex.spice
index a0c32e5..2f18933 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_4.pex.spice
-* Created: Thu Aug 27 20:58:12 2020
+* Created: Tue Sep  1 20:14:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pxi.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pxi.spice
index bd472a7..0f6d2c6 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_4.pxi.spice
-* Created: Thu Aug 27 20:58:12 2020
+* Created: Tue Sep  1 20:14:43 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21AI_4%A1 N_A1_M1006_g N_A1_c_98_n N_A1_M1008_g
 + N_A1_M1018_g N_A1_c_99_n N_A1_M1009_g N_A1_M1019_g N_A1_c_100_n N_A1_M1010_g

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.spice b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.spice
index 5d3285b..08801a5 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.spice
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ai_4.spice
-* Created: Thu Aug 27 20:58:12 2020
+* Created: Tue Sep  1 20:14:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.lvs.report b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.lvs.report
new file mode 100644
index 0000000..7bfe296
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21ba_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21ba_1.sp ('sky130_fd_sc_hs__o21ba_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21ba/sky130_fd_sc_hs__o21ba_1.spice ('sky130_fd_sc_hs__o21ba_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:46 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21ba_1      sky130_fd_sc_hs__o21ba_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21ba_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21ba_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  1 sec

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pex.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pex.spice
index a66255f..e877967 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_1.pex.spice
-* Created: Thu Aug 27 20:58:23 2020
+* Created: Tue Sep  1 20:14:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pxi.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pxi.spice
index 0a2b99c..f692f3b 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_1.pxi.spice
-* Created: Thu Aug 27 20:58:23 2020
+* Created: Tue Sep  1 20:14:49 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21BA_1%A1 N_A1_c_73_n N_A1_M1008_g N_A1_c_78_n
 + N_A1_M1002_g A1 A1 N_A1_c_75_n N_A1_c_76_n PM_SKY130_FD_SC_HS__O21BA_1%A1

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.spice
index be7b2bd..0ec0e2b 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_1.spice
-* Created: Thu Aug 27 20:58:23 2020
+* Created: Tue Sep  1 20:14:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.lvs.report b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.lvs.report
new file mode 100644
index 0000000..c991bc8
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21ba_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21ba_2.sp ('sky130_fd_sc_hs__o21ba_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21ba/sky130_fd_sc_hs__o21ba_2.spice ('sky130_fd_sc_hs__o21ba_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:52 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21ba_2      sky130_fd_sc_hs__o21ba_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21ba_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21ba_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pex.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pex.spice
index f1019bb..981c7e8 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_2.pex.spice
-* Created: Thu Aug 27 20:58:31 2020
+* Created: Tue Sep  1 20:14:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pxi.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pxi.spice
index fc103bc..f9a6ba6 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_2.pxi.spice
-* Created: Thu Aug 27 20:58:31 2020
+* Created: Tue Sep  1 20:14:55 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21BA_2%B1_N N_B1_N_M1003_g N_B1_N_c_70_n N_B1_N_M1005_g
 + B1_N N_B1_N_c_71_n PM_SKY130_FD_SC_HS__O21BA_2%B1_N

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.spice
index 2bb98b1..ed62c8e 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_2.spice
-* Created: Thu Aug 27 20:58:31 2020
+* Created: Tue Sep  1 20:14:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.lvs.report b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.lvs.report
new file mode 100644
index 0000000..0501bf5
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21ba_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21ba_4.sp ('sky130_fd_sc_hs__o21ba_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21ba/sky130_fd_sc_hs__o21ba_4.spice ('sky130_fd_sc_hs__o21ba_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:14:58 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21ba_4      sky130_fd_sc_hs__o21ba_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21ba_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21ba_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          2         2         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pex.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pex.spice
index 0781a57..77b2e48 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_4.pex.spice
-* Created: Thu Aug 27 20:58:38 2020
+* Created: Tue Sep  1 20:15:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pxi.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pxi.spice
index 9f2bc65..abdc7db 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_4.pxi.spice
-* Created: Thu Aug 27 20:58:38 2020
+* Created: Tue Sep  1 20:15:01 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21BA_4%B1_N N_B1_N_c_115_n N_B1_N_M1016_g N_B1_N_c_116_n
 + N_B1_N_M1021_g B1_N PM_SKY130_FD_SC_HS__O21BA_4%B1_N

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.spice b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.spice
index 1951ded..98d74d7 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.spice
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21ba_4.spice
-* Created: Thu Aug 27 20:58:38 2020
+* Created: Tue Sep  1 20:15:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.lvs.report b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.lvs.report
new file mode 100644
index 0000000..2acd232
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21bai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21bai_1.sp ('sky130_fd_sc_hs__o21bai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21bai/sky130_fd_sc_hs__o21bai_1.spice ('sky130_fd_sc_hs__o21bai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:05 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21bai_1     sky130_fd_sc_hs__o21bai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21bai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21bai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pex.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pex.spice
index d2af53d..d3b4215 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_1.pex.spice
-* Created: Thu Aug 27 20:58:46 2020
+* Created: Tue Sep  1 20:15:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pxi.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pxi.spice
index 73e2980..b6c89d5 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_1.pxi.spice
-* Created: Thu Aug 27 20:58:46 2020
+* Created: Tue Sep  1 20:15:08 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21BAI_1%B1_N N_B1_N_M1001_g N_B1_N_c_60_n N_B1_N_M1000_g
 + B1_N N_B1_N_c_61_n PM_SKY130_FD_SC_HS__O21BAI_1%B1_N

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.spice
index 5848616..4f865f5 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_1.spice
-* Created: Thu Aug 27 20:58:46 2020
+* Created: Tue Sep  1 20:15:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.lvs.report b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.lvs.report
new file mode 100644
index 0000000..682d753
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21bai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21bai_2.sp ('sky130_fd_sc_hs__o21bai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21bai/sky130_fd_sc_hs__o21bai_2.spice ('sky130_fd_sc_hs__o21bai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:11 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21bai_2     sky130_fd_sc_hs__o21bai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21bai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21bai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pex.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pex.spice
index 3f58317..af0a201 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_2.pex.spice
-* Created: Thu Aug 27 20:58:54 2020
+* Created: Tue Sep  1 20:15:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pxi.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pxi.spice
index 7099c73..16f0b03 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_2.pxi.spice
-* Created: Thu Aug 27 20:58:54 2020
+* Created: Tue Sep  1 20:15:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21BAI_2%B1_N N_B1_N_M1012_g N_B1_N_c_79_n N_B1_N_M1003_g
 + B1_N N_B1_N_c_80_n PM_SKY130_FD_SC_HS__O21BAI_2%B1_N

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.spice
index 3bf5873..d3cbe36 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_2.spice
-* Created: Thu Aug 27 20:58:54 2020
+* Created: Tue Sep  1 20:15:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.lvs.report b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.lvs.report
new file mode 100644
index 0000000..b0952a5
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o21bai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o21bai_4.sp ('sky130_fd_sc_hs__o21bai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o21bai/sky130_fd_sc_hs__o21bai_4.spice ('sky130_fd_sc_hs__o21bai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o21bai_4     sky130_fd_sc_hs__o21bai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o21bai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o21bai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         13        13         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        26        25
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 7.
+     17 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 7.
+     17 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pex.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pex.spice
index d424dfa..ae0482c 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_4.pex.spice
-* Created: Thu Aug 27 20:59:01 2020
+* Created: Tue Sep  1 20:15:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pxi.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pxi.spice
index 931b01b..79c1f82 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_4.pxi.spice
-* Created: Thu Aug 27 20:59:01 2020
+* Created: Tue Sep  1 20:15:20 2020
 * 
 x_PM_SKY130_FD_SC_HS__O21BAI_4%A1 N_A1_M1006_g N_A1_c_135_n N_A1_M1008_g
 + N_A1_c_136_n N_A1_M1009_g N_A1_M1016_g N_A1_M1019_g N_A1_c_137_n N_A1_M1010_g

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.spice b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.spice
index 204f73f..a466639 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.spice
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o21bai_4.spice
-* Created: Thu Aug 27 20:59:01 2020
+* Created: Tue Sep  1 20:15:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_1.lvs.report b/cells/o221a/sky130_fd_sc_hs__o221a_1.lvs.report
new file mode 100644
index 0000000..e780fdc
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o221a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o221a_1.sp ('sky130_fd_sc_hs__o221a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o221a/sky130_fd_sc_hs__o221a_1.spice ('sky130_fd_sc_hs__o221a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:23 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o221a_1      sky130_fd_sc_hs__o221a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o221a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o221a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_1.pex.spice b/cells/o221a/sky130_fd_sc_hs__o221a_1.pex.spice
index 5ebbd1e..3c242f4 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_1.pex.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_1.pex.spice
-* Created: Thu Aug 27 20:59:10 2020
+* Created: Tue Sep  1 20:15:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_1.pxi.spice b/cells/o221a/sky130_fd_sc_hs__o221a_1.pxi.spice
index 5c72fca..49bf2ef 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_1.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_1.pxi.spice
-* Created: Thu Aug 27 20:59:10 2020
+* Created: Tue Sep  1 20:15:26 2020
 * 
 x_PM_SKY130_FD_SC_HS__O221A_1%A_83_264# N_A_83_264#_M1005_d N_A_83_264#_M1006_d
 + N_A_83_264#_M1011_d N_A_83_264#_c_73_n N_A_83_264#_M1009_g N_A_83_264#_M1003_g

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_1.spice b/cells/o221a/sky130_fd_sc_hs__o221a_1.spice
index 61a35be..9c982f0 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_1.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_1.spice
-* Created: Thu Aug 27 20:59:10 2020
+* Created: Tue Sep  1 20:15:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_2.lvs.report b/cells/o221a/sky130_fd_sc_hs__o221a_2.lvs.report
new file mode 100644
index 0000000..c22b604
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o221a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o221a_2.sp ('sky130_fd_sc_hs__o221a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o221a/sky130_fd_sc_hs__o221a_2.spice ('sky130_fd_sc_hs__o221a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:29 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o221a_2      sky130_fd_sc_hs__o221a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o221a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o221a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_2.pex.spice b/cells/o221a/sky130_fd_sc_hs__o221a_2.pex.spice
index bc13e5d..fecb9fd 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_2.pex.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_2.pex.spice
-* Created: Thu Aug 27 20:59:18 2020
+* Created: Tue Sep  1 20:15:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_2.pxi.spice b/cells/o221a/sky130_fd_sc_hs__o221a_2.pxi.spice
index dd33859..5da8194 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_2.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_2.pxi.spice
-* Created: Thu Aug 27 20:59:18 2020
+* Created: Tue Sep  1 20:15:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__O221A_2%C1 N_C1_c_84_n N_C1_M1013_g N_C1_c_81_n
 + N_C1_M1006_g C1 N_C1_c_83_n PM_SKY130_FD_SC_HS__O221A_2%C1

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_2.spice b/cells/o221a/sky130_fd_sc_hs__o221a_2.spice
index a719a3e..fa8e7b6 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_2.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_2.spice
-* Created: Thu Aug 27 20:59:18 2020
+* Created: Tue Sep  1 20:15:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_4.lvs.report b/cells/o221a/sky130_fd_sc_hs__o221a_4.lvs.report
new file mode 100644
index 0000000..705e4da
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o221a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o221a_4.sp ('sky130_fd_sc_hs__o221a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o221a/sky130_fd_sc_hs__o221a_4.spice ('sky130_fd_sc_hs__o221a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:35 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o221a_4      sky130_fd_sc_hs__o221a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o221a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o221a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B2 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_4.pex.spice b/cells/o221a/sky130_fd_sc_hs__o221a_4.pex.spice
index be5f137..9fb8bcf 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_4.pex.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_4.pex.spice
-* Created: Thu Aug 27 20:59:29 2020
+* Created: Tue Sep  1 20:15:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_4.pxi.spice b/cells/o221a/sky130_fd_sc_hs__o221a_4.pxi.spice
index 5dd6c13..a882aae 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_4.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_4.pxi.spice
-* Created: Thu Aug 27 20:59:29 2020
+* Created: Tue Sep  1 20:15:38 2020
 * 
 x_PM_SKY130_FD_SC_HS__O221A_4%C1 N_C1_M1016_g N_C1_c_146_n N_C1_M1024_g
 + N_C1_M1017_g N_C1_c_147_n N_C1_M1025_g C1 C1 N_C1_c_145_n

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_4.spice b/cells/o221a/sky130_fd_sc_hs__o221a_4.spice
index 67a277e..4a44503 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_4.spice
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221a_4.spice
-* Created: Thu Aug 27 20:59:29 2020
+* Created: Tue Sep  1 20:15:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.lvs.report b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.lvs.report
new file mode 100644
index 0000000..6635674
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o221ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o221ai_1.sp ('sky130_fd_sc_hs__o221ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o221ai/sky130_fd_sc_hs__o221ai_1.spice ('sky130_fd_sc_hs__o221ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o221ai_1     sky130_fd_sc_hs__o221ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o221ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o221ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 B2 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pex.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pex.spice
index fcfc7eb..265f66d 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_1.pex.spice
-* Created: Thu Aug 27 20:59:36 2020
+* Created: Tue Sep  1 20:15:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pxi.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pxi.spice
index ad3a192..7121848 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_1.pxi.spice
-* Created: Thu Aug 27 20:59:36 2020
+* Created: Tue Sep  1 20:15:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__O221AI_1%C1 N_C1_M1009_g N_C1_c_61_n N_C1_M1001_g C1
 + N_C1_c_59_n N_C1_c_60_n PM_SKY130_FD_SC_HS__O221AI_1%C1

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.spice
index 16dcb7b..300c1e3 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_1.spice
-* Created: Thu Aug 27 20:59:36 2020
+* Created: Tue Sep  1 20:15:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.lvs.report b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.lvs.report
new file mode 100644
index 0000000..713790f
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o221ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o221ai_2.sp ('sky130_fd_sc_hs__o221ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o221ai/sky130_fd_sc_hs__o221ai_2.spice ('sky130_fd_sc_hs__o221ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o221ai_2     sky130_fd_sc_hs__o221ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o221ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o221ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pex.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pex.spice
index f1d0eec..499f866 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_2.pex.spice
-* Created: Thu Aug 27 20:59:44 2020
+* Created: Tue Sep  1 20:15:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pxi.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pxi.spice
index 31fe051..a00c404 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_2.pxi.spice
-* Created: Thu Aug 27 20:59:44 2020
+* Created: Tue Sep  1 20:15:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__O221AI_2%C1 N_C1_M1015_g N_C1_c_96_n N_C1_M1018_g
 + N_C1_M1016_g N_C1_c_97_n N_C1_M1019_g C1 N_C1_c_94_n N_C1_c_95_n

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.spice
index fcba24f..6915779 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_2.spice
-* Created: Thu Aug 27 20:59:44 2020
+* Created: Tue Sep  1 20:15:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.lvs.report b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.lvs.report
new file mode 100644
index 0000000..0774841
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o221ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o221ai_4.sp ('sky130_fd_sc_hs__o221ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o221ai/sky130_fd_sc_hs__o221ai_4.spice ('sky130_fd_sc_hs__o221ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:15:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o221ai_4     sky130_fd_sc_hs__o221ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o221ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o221ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pex.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pex.spice
index a6d0c3a..74348a1 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_4.pex.spice
-* Created: Thu Aug 27 20:59:52 2020
+* Created: Tue Sep  1 20:15:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pxi.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pxi.spice
index 0f73350..472a8d5 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_4.pxi.spice
-* Created: Thu Aug 27 20:59:52 2020
+* Created: Tue Sep  1 20:15:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__O221AI_4%C1 N_C1_M1000_g N_C1_c_148_n N_C1_M1001_g
 + N_C1_M1005_g N_C1_c_149_n N_C1_M1014_g N_C1_M1006_g N_C1_c_150_n N_C1_M1028_g

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.spice b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.spice
index f2ca7a6..4635d00 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.spice
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o221ai_4.spice
-* Created: Thu Aug 27 20:59:52 2020
+* Created: Tue Sep  1 20:15:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_1.lvs.report b/cells/o22a/sky130_fd_sc_hs__o22a_1.lvs.report
new file mode 100644
index 0000000..41df59e
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o22a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o22a_1.sp ('sky130_fd_sc_hs__o22a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o22a/sky130_fd_sc_hs__o22a_1.spice ('sky130_fd_sc_hs__o22a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o22a_1       sky130_fd_sc_hs__o22a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o22a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o22a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_1.pex.spice b/cells/o22a/sky130_fd_sc_hs__o22a_1.pex.spice
index 835a1bf..d6b8b06 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_1.pex.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_1.pex.spice
-* Created: Thu Aug 27 21:00:00 2020
+* Created: Tue Sep  1 20:16:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_1.pxi.spice b/cells/o22a/sky130_fd_sc_hs__o22a_1.pxi.spice
index cf035ca..a532850 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_1.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_1.pxi.spice
-* Created: Thu Aug 27 21:00:00 2020
+* Created: Tue Sep  1 20:16:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__O22A_1%A_83_260# N_A_83_260#_M1001_d N_A_83_260#_M1002_d
 + N_A_83_260#_M1009_g N_A_83_260#_c_67_n N_A_83_260#_M1005_g N_A_83_260#_c_62_n

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_1.spice b/cells/o22a/sky130_fd_sc_hs__o22a_1.spice
index 22ea0d1..76ce494 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_1.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_1.spice
-* Created: Thu Aug 27 21:00:00 2020
+* Created: Tue Sep  1 20:16:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_2.lvs.report b/cells/o22a/sky130_fd_sc_hs__o22a_2.lvs.report
new file mode 100644
index 0000000..fdd5305
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o22a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o22a_2.sp ('sky130_fd_sc_hs__o22a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o22a/sky130_fd_sc_hs__o22a_2.spice ('sky130_fd_sc_hs__o22a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o22a_2       sky130_fd_sc_hs__o22a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o22a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o22a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_2.pex.spice b/cells/o22a/sky130_fd_sc_hs__o22a_2.pex.spice
index 7b00d5b..fead3de 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_2.pex.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_2.pex.spice
-* Created: Thu Aug 27 21:00:07 2020
+* Created: Tue Sep  1 20:16:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_2.pxi.spice b/cells/o22a/sky130_fd_sc_hs__o22a_2.pxi.spice
index 4e25ee2..da17766 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_2.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_2.pxi.spice
-* Created: Thu Aug 27 21:00:07 2020
+* Created: Tue Sep  1 20:16:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__O22A_2%A_82_48# N_A_82_48#_M1001_d N_A_82_48#_M1000_d
 + N_A_82_48#_M1002_g N_A_82_48#_c_76_n N_A_82_48#_M1004_g N_A_82_48#_M1006_g

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_2.spice b/cells/o22a/sky130_fd_sc_hs__o22a_2.spice
index 1c3b574..cc66421 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_2.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_2.spice
-* Created: Thu Aug 27 21:00:07 2020
+* Created: Tue Sep  1 20:16:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_4.lvs.report b/cells/o22a/sky130_fd_sc_hs__o22a_4.lvs.report
new file mode 100644
index 0000000..0a64c4a
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o22a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o22a_4.sp ('sky130_fd_sc_hs__o22a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o22a/sky130_fd_sc_hs__o22a_4.spice ('sky130_fd_sc_hs__o22a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:13 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o22a_4       sky130_fd_sc_hs__o22a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o22a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o22a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_4.pex.spice b/cells/o22a/sky130_fd_sc_hs__o22a_4.pex.spice
index a70f792..bb69d24 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_4.pex.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_4.pex.spice
-* Created: Thu Aug 27 21:00:16 2020
+* Created: Tue Sep  1 20:16:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_4.pxi.spice b/cells/o22a/sky130_fd_sc_hs__o22a_4.pxi.spice
index 8f173ee..734c7f3 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_4.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_4.pxi.spice
-* Created: Thu Aug 27 21:00:16 2020
+* Created: Tue Sep  1 20:16:16 2020
 * 
 x_PM_SKY130_FD_SC_HS__O22A_4%A2 N_A2_c_119_n N_A2_M1010_g N_A2_M1018_g
 + N_A2_c_116_n N_A2_M1019_g N_A2_c_120_n N_A2_M1011_g A2 N_A2_c_117_n

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_4.spice b/cells/o22a/sky130_fd_sc_hs__o22a_4.spice
index 0c4e264..03ae8df 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_4.spice
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22a_4.spice
-* Created: Thu Aug 27 21:00:16 2020
+* Created: Tue Sep  1 20:16:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.lvs.report b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.lvs.report
new file mode 100644
index 0000000..f32f781
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o22ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o22ai_1.sp ('sky130_fd_sc_hs__o22ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o22ai/sky130_fd_sc_hs__o22ai_1.spice ('sky130_fd_sc_hs__o22ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:19 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o22ai_1      sky130_fd_sc_hs__o22ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o22ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o22ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pex.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pex.spice
index e65c70b..bacaa26 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_1.pex.spice
-* Created: Thu Aug 27 21:00:24 2020
+* Created: Tue Sep  1 20:16:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pxi.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pxi.spice
index 7404834..ad1d718 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_1.pxi.spice
-* Created: Thu Aug 27 21:00:24 2020
+* Created: Tue Sep  1 20:16:22 2020
 * 
 x_PM_SKY130_FD_SC_HS__O22AI_1%B1 N_B1_c_44_n N_B1_M1007_g N_B1_c_45_n
 + N_B1_M1000_g B1 PM_SKY130_FD_SC_HS__O22AI_1%B1

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.spice
index dd91db5..cc94d9a 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_1.spice
-* Created: Thu Aug 27 21:00:24 2020
+* Created: Tue Sep  1 20:16:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.lvs.report b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.lvs.report
new file mode 100644
index 0000000..0a6f48d
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o22ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o22ai_2.sp ('sky130_fd_sc_hs__o22ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o22ai/sky130_fd_sc_hs__o22ai_2.spice ('sky130_fd_sc_hs__o22ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:25 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o22ai_2      sky130_fd_sc_hs__o22ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o22ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o22ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pex.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pex.spice
index c8d5127..b64fbaf 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_2.pex.spice
-* Created: Thu Aug 27 21:00:35 2020
+* Created: Tue Sep  1 20:16:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pxi.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pxi.spice
index 16b2f89..ef5e163 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_2.pxi.spice
-* Created: Thu Aug 27 21:00:35 2020
+* Created: Tue Sep  1 20:16:28 2020
 * 
 x_PM_SKY130_FD_SC_HS__O22AI_2%B1 N_B1_M1009_g N_B1_c_83_n N_B1_M1002_g
 + N_B1_c_84_n N_B1_M1006_g N_B1_M1012_g B1 B1 B1 N_B1_c_82_n

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.spice
index 0efc92e..21014e9 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_2.spice
-* Created: Thu Aug 27 21:00:35 2020
+* Created: Tue Sep  1 20:16:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.lvs.report b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.lvs.report
new file mode 100644
index 0000000..390bc63
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o22ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o22ai_4.sp ('sky130_fd_sc_hs__o22ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o22ai/sky130_fd_sc_hs__o22ai_4.spice ('sky130_fd_sc_hs__o22ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:31 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o22ai_4      sky130_fd_sc_hs__o22ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o22ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o22ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         SMP2 (4 pins)
+                     1         1         SPMN_2_2 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    SMP2
+                        1          1            0            0    SPMN_2_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   32 layout mos transistors were reduced to 8.
+     24 mos transistors were deleted by parallel reduction.
+   32 source mos transistors were reduced to 8.
+     24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pex.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pex.spice
index e6b03f8..4cbfc48 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_4.pex.spice
-* Created: Thu Aug 27 21:00:43 2020
+* Created: Tue Sep  1 20:16:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pxi.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pxi.spice
index d49fd6c..ae8fb27 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_4.pxi.spice
-* Created: Thu Aug 27 21:00:43 2020
+* Created: Tue Sep  1 20:16:34 2020
 * 
 x_PM_SKY130_FD_SC_HS__O22AI_4%A1 N_A1_M1000_g N_A1_c_125_n N_A1_M1005_g
 + N_A1_c_126_n N_A1_M1006_g N_A1_M1011_g N_A1_M1025_g N_A1_c_127_n N_A1_M1007_g

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.spice b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.spice
index c160f24..044cba5 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.spice
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o22ai_4.spice
-* Created: Thu Aug 27 21:00:43 2020
+* Created: Tue Sep  1 20:16:34 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.lvs.report b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.lvs.report
new file mode 100644
index 0000000..baea9d9
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.lvs.report

@@ -0,0 +1,470 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2bb2a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2bb2a_1.sp ('sky130_fd_sc_hs__o2bb2a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.spice ('sky130_fd_sc_hs__o2bb2a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2bb2a_1     sky130_fd_sc_hs__o2bb2a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2bb2a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2bb2a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pex.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pex.spice
index ec8a02e..fae3a38 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_1.pex.spice
-* Created: Thu Aug 27 21:00:50 2020
+* Created: Tue Sep  1 20:16:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pxi.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pxi.spice
index 8e07de7..6a3fbc3 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_1.pxi.spice
-* Created: Thu Aug 27 21:00:50 2020
+* Created: Tue Sep  1 20:16:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2BB2A_1%A_83_260# N_A_83_260#_M1007_s N_A_83_260#_M1001_d
 + N_A_83_260#_M1002_g N_A_83_260#_c_78_n N_A_83_260#_M1006_g N_A_83_260#_c_79_n

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.spice
index f819844..b0aeeb4 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_1.spice
-* Created: Thu Aug 27 21:00:50 2020
+* Created: Tue Sep  1 20:16:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.lvs.report b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.lvs.report
new file mode 100644
index 0000000..3e8a956
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2bb2a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2bb2a_2.sp ('sky130_fd_sc_hs__o2bb2a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.spice ('sky130_fd_sc_hs__o2bb2a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2bb2a_2     sky130_fd_sc_hs__o2bb2a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2bb2a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2bb2a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pex.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pex.spice
index 82230cc..f3d8e7e 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_2.pex.spice
-* Created: Thu Aug 27 21:00:58 2020
+* Created: Tue Sep  1 20:16:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pxi.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pxi.spice
index c08ad5a..bb0d3e0 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_2.pxi.spice
-* Created: Thu Aug 27 21:00:58 2020
+* Created: Tue Sep  1 20:16:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2BB2A_2%B1 N_B1_M1011_g N_B1_c_84_n N_B1_M1001_g B1
 + N_B1_c_85_n PM_SKY130_FD_SC_HS__O2BB2A_2%B1

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.spice
index ad84e47..5feafc3 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_2.spice
-* Created: Thu Aug 27 21:00:58 2020
+* Created: Tue Sep  1 20:16:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.lvs.report b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.lvs.report
new file mode 100644
index 0000000..438ea71
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2bb2a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2bb2a_4.sp ('sky130_fd_sc_hs__o2bb2a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.spice ('sky130_fd_sc_hs__o2bb2a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2bb2a_4     sky130_fd_sc_hs__o2bb2a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2bb2a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2bb2a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        4          4            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pex.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pex.spice
index 881137c..5f6acea 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_4.pex.spice
-* Created: Thu Aug 27 21:01:06 2020
+* Created: Tue Sep  1 20:16:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pxi.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pxi.spice
index d8b6480..64d6abc 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_4.pxi.spice
-* Created: Thu Aug 27 21:01:06 2020
+* Created: Tue Sep  1 20:16:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2BB2A_4%B1 N_B1_M1022_g N_B1_c_128_n N_B1_c_134_n
 + N_B1_M1007_g N_B1_c_129_n N_B1_c_136_n N_B1_M1015_g N_B1_M1023_g B1 B1

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.spice b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.spice
index 6f4f71b..56712e2 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.spice
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2a_4.spice
-* Created: Thu Aug 27 21:01:06 2020
+* Created: Tue Sep  1 20:16:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.lvs.report b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.lvs.report
new file mode 100644
index 0000000..ff71967
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2bb2ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2bb2ai_1.sp ('sky130_fd_sc_hs__o2bb2ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.spice ('sky130_fd_sc_hs__o2bb2ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:16:56 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2bb2ai_1    sky130_fd_sc_hs__o2bb2ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2bb2ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2bb2ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pex.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pex.spice
index d9dbb09..2808a08 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_1.pex.spice
-* Created: Thu Aug 27 21:01:13 2020
+* Created: Tue Sep  1 20:16:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pxi.spice
index bf30de2..352d1ab 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_1.pxi.spice
-* Created: Thu Aug 27 21:01:13 2020
+* Created: Tue Sep  1 20:16:59 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2BB2AI_1%A1_N N_A1_N_M1007_g N_A1_N_c_65_n N_A1_N_c_69_n
 + N_A1_N_M1008_g N_A1_N_c_70_n A1_N N_A1_N_c_67_n

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.spice
index 5e6683f..faf9211 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_1.spice
-* Created: Thu Aug 27 21:01:13 2020
+* Created: Tue Sep  1 20:16:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.lvs.report b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.lvs.report
new file mode 100644
index 0000000..adf66d0
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2bb2ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2bb2ai_2.sp ('sky130_fd_sc_hs__o2bb2ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.spice ('sky130_fd_sc_hs__o2bb2ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2bb2ai_2    sky130_fd_sc_hs__o2bb2ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2bb2ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2bb2ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pex.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pex.spice
index efedd86..0aaa965 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_2.pex.spice
-* Created: Thu Aug 27 21:01:22 2020
+* Created: Tue Sep  1 20:17:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pxi.spice
index 00990ec..093071f 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_2.pxi.spice
-* Created: Thu Aug 27 21:01:22 2020
+* Created: Tue Sep  1 20:17:05 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2BB2AI_2%A1_N N_A1_N_c_97_n N_A1_N_M1004_g N_A1_N_M1006_g
 + N_A1_N_c_99_n N_A1_N_M1012_g N_A1_N_c_100_n N_A1_N_M1018_g N_A1_N_c_101_n

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.spice
index 61165e3..c08a25b 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_2.spice
-* Created: Thu Aug 27 21:01:22 2020
+* Created: Tue Sep  1 20:17:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.lvs.report b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.lvs.report
new file mode 100644
index 0000000..0325439
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o2bb2ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o2bb2ai_4.sp ('sky130_fd_sc_hs__o2bb2ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.spice ('sky130_fd_sc_hs__o2bb2ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o2bb2ai_4    sky130_fd_sc_hs__o2bb2ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o2bb2ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o2bb2ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pex.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pex.spice
index 90b54b0..dadea6d 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_4.pex.spice
-* Created: Thu Aug 27 21:01:30 2020
+* Created: Tue Sep  1 20:17:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pxi.spice
index 401c680..3afff84 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_4.pxi.spice
-* Created: Thu Aug 27 21:01:30 2020
+* Created: Tue Sep  1 20:17:12 2020
 * 
 x_PM_SKY130_FD_SC_HS__O2BB2AI_4%A1_N N_A1_N_M1009_g N_A1_N_c_173_n
 + N_A1_N_M1001_g N_A1_N_M1032_g N_A1_N_c_174_n N_A1_N_M1002_g N_A1_N_M1033_g

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.spice b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.spice
index 4265949..55fa506 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o2bb2ai_4.spice
-* Created: Thu Aug 27 21:01:30 2020
+* Created: Tue Sep  1 20:17:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_1.lvs.report b/cells/o311a/sky130_fd_sc_hs__o311a_1.lvs.report
new file mode 100644
index 0000000..910d0be
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o311a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o311a_1.sp ('sky130_fd_sc_hs__o311a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o311a/sky130_fd_sc_hs__o311a_1.spice ('sky130_fd_sc_hs__o311a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:15 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o311a_1      sky130_fd_sc_hs__o311a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o311a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o311a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A2 A3 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_1.pex.spice b/cells/o311a/sky130_fd_sc_hs__o311a_1.pex.spice
index 66a9a60..b187ecd 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_1.pex.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_1.pex.spice
-* Created: Thu Aug 27 21:01:41 2020
+* Created: Tue Sep  1 20:17:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_1.pxi.spice b/cells/o311a/sky130_fd_sc_hs__o311a_1.pxi.spice
index d33cfc3..e60d9d6 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_1.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_1.pxi.spice
-* Created: Thu Aug 27 21:01:41 2020
+* Created: Tue Sep  1 20:17:18 2020
 * 
 x_PM_SKY130_FD_SC_HS__O311A_1%C1 N_C1_c_79_n N_C1_c_84_n N_C1_M1007_g
 + N_C1_M1005_g C1 N_C1_c_82_n PM_SKY130_FD_SC_HS__O311A_1%C1

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_1.spice b/cells/o311a/sky130_fd_sc_hs__o311a_1.spice
index a251821..72d14d3 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_1.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_1.spice
-* Created: Thu Aug 27 21:01:41 2020
+* Created: Tue Sep  1 20:17:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_2.lvs.report b/cells/o311a/sky130_fd_sc_hs__o311a_2.lvs.report
new file mode 100644
index 0000000..ece7672
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o311a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o311a_2.sp ('sky130_fd_sc_hs__o311a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o311a/sky130_fd_sc_hs__o311a_2.spice ('sky130_fd_sc_hs__o311a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:21 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o311a_2      sky130_fd_sc_hs__o311a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o311a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o311a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_2.pex.spice b/cells/o311a/sky130_fd_sc_hs__o311a_2.pex.spice
index 4492882..218d93d 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_2.pex.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_2.pex.spice
-* Created: Thu Aug 27 21:01:49 2020
+* Created: Tue Sep  1 20:17:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_2.pxi.spice b/cells/o311a/sky130_fd_sc_hs__o311a_2.pxi.spice
index 4d40e4b..9ac6ceb 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_2.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_2.pxi.spice
-* Created: Thu Aug 27 21:01:49 2020
+* Created: Tue Sep  1 20:17:24 2020
 * 
 x_PM_SKY130_FD_SC_HS__O311A_2%C1 N_C1_M1001_g N_C1_c_72_n N_C1_M1010_g
 + N_C1_c_69_n N_C1_c_70_n C1 PM_SKY130_FD_SC_HS__O311A_2%C1

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_2.spice b/cells/o311a/sky130_fd_sc_hs__o311a_2.spice
index 167d39e..f1e38f4 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_2.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_2.spice
-* Created: Thu Aug 27 21:01:49 2020
+* Created: Tue Sep  1 20:17:24 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_4.lvs.report b/cells/o311a/sky130_fd_sc_hs__o311a_4.lvs.report
new file mode 100644
index 0000000..210a082
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o311a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o311a_4.sp ('sky130_fd_sc_hs__o311a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o311a/sky130_fd_sc_hs__o311a_4.spice ('sky130_fd_sc_hs__o311a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:27 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o311a_4      sky130_fd_sc_hs__o311a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o311a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o311a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 C1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_4.pex.spice b/cells/o311a/sky130_fd_sc_hs__o311a_4.pex.spice
index bde55dc..962b449 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_4.pex.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_4.pex.spice
-* Created: Thu Aug 27 21:01:56 2020
+* Created: Tue Sep  1 20:17:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_4.pxi.spice b/cells/o311a/sky130_fd_sc_hs__o311a_4.pxi.spice
index b73fc0b..70b9b4e 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_4.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_4.pxi.spice
-* Created: Thu Aug 27 21:01:56 2020
+* Created: Tue Sep  1 20:17:30 2020
 * 
 x_PM_SKY130_FD_SC_HS__O311A_4%A_83_244# N_A_83_244#_M1012_d N_A_83_244#_M1002_s
 + N_A_83_244#_M1005_d N_A_83_244#_M1011_d N_A_83_244#_c_158_n

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_4.spice b/cells/o311a/sky130_fd_sc_hs__o311a_4.spice
index a6c6f63..7b967d4 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_4.spice
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311a_4.spice
-* Created: Thu Aug 27 21:01:56 2020
+* Created: Tue Sep  1 20:17:30 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.lvs.report b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.lvs.report
new file mode 100644
index 0000000..1d162f9
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o311ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o311ai_1.sp ('sky130_fd_sc_hs__o311ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o311ai/sky130_fd_sc_hs__o311ai_1.spice ('sky130_fd_sc_hs__o311ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:34 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o311ai_1     sky130_fd_sc_hs__o311ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o311ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o311ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pex.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pex.spice
index 1b5be1a..3303fe8 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_1.pex.spice
-* Created: Thu Aug 27 21:02:04 2020
+* Created: Tue Sep  1 20:17:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pxi.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pxi.spice
index c8c571f..e824dce 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_1.pxi.spice
-* Created: Thu Aug 27 21:02:04 2020
+* Created: Tue Sep  1 20:17:37 2020
 * 
 x_PM_SKY130_FD_SC_HS__O311AI_1%A1 N_A1_M1005_g N_A1_c_50_n N_A1_M1006_g A1
 + N_A1_c_51_n PM_SKY130_FD_SC_HS__O311AI_1%A1

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.spice
index bcad760..186aa73 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_1.spice
-* Created: Thu Aug 27 21:02:04 2020
+* Created: Tue Sep  1 20:17:37 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.lvs.report b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.lvs.report
new file mode 100644
index 0000000..f3a8138
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o311ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o311ai_2.sp ('sky130_fd_sc_hs__o311ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o311ai/sky130_fd_sc_hs__o311ai_2.spice ('sky130_fd_sc_hs__o311ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:40 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o311ai_2     sky130_fd_sc_hs__o311ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o311ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o311ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pex.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pex.spice
index 1ec4547..280dd58 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_2.pex.spice
-* Created: Thu Aug 27 21:02:12 2020
+* Created: Tue Sep  1 20:17:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pxi.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pxi.spice
index f88088c..0c73943 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_2.pxi.spice
-* Created: Thu Aug 27 21:02:12 2020
+* Created: Tue Sep  1 20:17:43 2020
 * 
 x_PM_SKY130_FD_SC_HS__O311AI_2%A1 N_A1_M1000_g N_A1_c_103_n N_A1_M1009_g
 + N_A1_c_104_n N_A1_M1018_g N_A1_M1019_g A1 A1 N_A1_c_102_n

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.spice
index a82a6a9..f85be42 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_2.spice
-* Created: Thu Aug 27 21:02:12 2020
+* Created: Tue Sep  1 20:17:43 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.lvs.report b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.lvs.report
new file mode 100644
index 0000000..e8ae4f6
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o311ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o311ai_4.sp ('sky130_fd_sc_hs__o311ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o311ai/sky130_fd_sc_hs__o311ai_4.spice ('sky130_fd_sc_hs__o311ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:46 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o311ai_4     sky130_fd_sc_hs__o311ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o311ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o311ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        37        36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1_1 (7 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   36 layout mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+   36 source mos transistors were reduced to 10.
+     26 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C1 B1 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pex.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pex.spice
index cbe76be..bf6da28 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_4.pex.spice
-* Created: Thu Aug 27 21:02:19 2020
+* Created: Tue Sep  1 20:17:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pxi.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pxi.spice
index e06f650..6ffccae 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_4.pxi.spice
-* Created: Thu Aug 27 21:02:19 2020
+* Created: Tue Sep  1 20:17:49 2020
 * 
 x_PM_SKY130_FD_SC_HS__O311AI_4%C1 N_C1_c_146_n N_C1_M1004_g N_C1_c_153_n
 + N_C1_M1008_g N_C1_c_147_n N_C1_M1023_g N_C1_c_154_n N_C1_M1026_g N_C1_c_148_n

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.spice b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.spice
index 0772e6b..b893bd5 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.spice
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o311ai_4.spice
-* Created: Thu Aug 27 21:02:19 2020
+* Created: Tue Sep  1 20:17:49 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_1.lvs.report b/cells/o31a/sky130_fd_sc_hs__o31a_1.lvs.report
new file mode 100644
index 0000000..9126e83
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o31a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o31a_1.sp ('sky130_fd_sc_hs__o31a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o31a/sky130_fd_sc_hs__o31a_1.spice ('sky130_fd_sc_hs__o31a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:53 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o31a_1       sky130_fd_sc_hs__o31a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o31a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o31a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_1.pex.spice b/cells/o31a/sky130_fd_sc_hs__o31a_1.pex.spice
index 578c59c..8c6ed8b 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_1.pex.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_1.pex.spice
-* Created: Thu Aug 27 21:02:28 2020
+* Created: Tue Sep  1 20:17:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_1.pxi.spice b/cells/o31a/sky130_fd_sc_hs__o31a_1.pxi.spice
index 0c0a52e..d04c823 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_1.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_1.pxi.spice
-* Created: Thu Aug 27 21:02:28 2020
+* Created: Tue Sep  1 20:17:55 2020
 * 
 x_PM_SKY130_FD_SC_HS__O31A_1%A_84_48# N_A_84_48#_M1004_d N_A_84_48#_M1001_d
 + N_A_84_48#_M1009_g N_A_84_48#_c_61_n N_A_84_48#_M1002_g N_A_84_48#_c_62_n

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_1.spice b/cells/o31a/sky130_fd_sc_hs__o31a_1.spice
index 6552cab..93c67f7 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_1.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_1.spice
-* Created: Thu Aug 27 21:02:28 2020
+* Created: Tue Sep  1 20:17:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_2.lvs.report b/cells/o31a/sky130_fd_sc_hs__o31a_2.lvs.report
new file mode 100644
index 0000000..3dc72db
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o31a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o31a_2.sp ('sky130_fd_sc_hs__o31a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o31a/sky130_fd_sc_hs__o31a_2.spice ('sky130_fd_sc_hs__o31a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:17:59 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o31a_2       sky130_fd_sc_hs__o31a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o31a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o31a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_2.pex.spice b/cells/o31a/sky130_fd_sc_hs__o31a_2.pex.spice
index e1d34ee..189b54f 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_2.pex.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_2.pex.spice
-* Created: Thu Aug 27 21:02:36 2020
+* Created: Tue Sep  1 20:18:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_2.pxi.spice b/cells/o31a/sky130_fd_sc_hs__o31a_2.pxi.spice
index 91befbe..be4c18d 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_2.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_2.pxi.spice
-* Created: Thu Aug 27 21:02:36 2020
+* Created: Tue Sep  1 20:18:01 2020
 * 
 x_PM_SKY130_FD_SC_HS__O31A_2%A_55_264# N_A_55_264#_M1001_d N_A_55_264#_M1003_d
 + N_A_55_264#_c_69_n N_A_55_264#_M1002_g N_A_55_264#_M1005_g N_A_55_264#_c_71_n

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_2.spice b/cells/o31a/sky130_fd_sc_hs__o31a_2.spice
index e2d949f..4b070e7 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_2.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_2.spice
-* Created: Thu Aug 27 21:02:36 2020
+* Created: Tue Sep  1 20:18:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_4.lvs.report b/cells/o31a/sky130_fd_sc_hs__o31a_4.lvs.report
new file mode 100644
index 0000000..8e17aae
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o31a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o31a_4.sp ('sky130_fd_sc_hs__o31a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o31a/sky130_fd_sc_hs__o31a_4.spice ('sky130_fd_sc_hs__o31a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:05 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o31a_4       sky130_fd_sc_hs__o31a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o31a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o31a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A3 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_4.pex.spice b/cells/o31a/sky130_fd_sc_hs__o31a_4.pex.spice
index 80c819b..ebb1f0b 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_4.pex.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_4.pex.spice
-* Created: Thu Aug 27 21:02:47 2020
+* Created: Tue Sep  1 20:18:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_4.pxi.spice b/cells/o31a/sky130_fd_sc_hs__o31a_4.pxi.spice
index d3f90c6..1e5d829 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_4.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_4.pxi.spice
-* Created: Thu Aug 27 21:02:47 2020
+* Created: Tue Sep  1 20:18:08 2020
 * 
 x_PM_SKY130_FD_SC_HS__O31A_4%A_86_260# N_A_86_260#_M1007_s N_A_86_260#_M1004_d
 + N_A_86_260#_M1016_d N_A_86_260#_c_140_n N_A_86_260#_M1012_g

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_4.spice b/cells/o31a/sky130_fd_sc_hs__o31a_4.spice
index 3049d80..0e53530 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_4.spice
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31a_4.spice
-* Created: Thu Aug 27 21:02:47 2020
+* Created: Tue Sep  1 20:18:08 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.lvs.report b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.lvs.report
new file mode 100644
index 0000000..0712f00
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o31ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o31ai_1.sp ('sky130_fd_sc_hs__o31ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o31ai/sky130_fd_sc_hs__o31ai_1.spice ('sky130_fd_sc_hs__o31ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:11 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o31ai_1      sky130_fd_sc_hs__o31ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o31ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o31ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pex.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pex.spice
index 250f85b..cd59561 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_1.pex.spice
-* Created: Thu Aug 27 21:02:54 2020
+* Created: Tue Sep  1 20:18:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pxi.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pxi.spice
index d4ebcb3..16013c9 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_1.pxi.spice
-* Created: Thu Aug 27 21:02:54 2020
+* Created: Tue Sep  1 20:18:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__O31AI_1%A1 N_A1_c_43_n N_A1_M1005_g N_A1_c_44_n
 + N_A1_M1004_g A1 PM_SKY130_FD_SC_HS__O31AI_1%A1

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.spice
index d4b2229..c52d3a0 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_1.spice
-* Created: Thu Aug 27 21:02:54 2020
+* Created: Tue Sep  1 20:18:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.lvs.report b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.lvs.report
new file mode 100644
index 0000000..e347d98
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o31ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o31ai_2.sp ('sky130_fd_sc_hs__o31ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o31ai/sky130_fd_sc_hs__o31ai_2.spice ('sky130_fd_sc_hs__o31ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o31ai_2      sky130_fd_sc_hs__o31ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o31ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o31ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pex.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pex.spice
index a3541f9..c113ab2 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_2.pex.spice
-* Created: Thu Aug 27 21:03:02 2020
+* Created: Tue Sep  1 20:18:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pxi.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pxi.spice
index 5852e2d..99ea76d 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_2.pxi.spice
-* Created: Thu Aug 27 21:03:02 2020
+* Created: Tue Sep  1 20:18:20 2020
 * 
 x_PM_SKY130_FD_SC_HS__O31AI_2%A1 N_A1_M1014_g N_A1_c_85_n N_A1_M1006_g
 + N_A1_c_86_n N_A1_M1007_g N_A1_c_82_n N_A1_M1015_g A1 A1 A1 N_A1_c_84_n

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.spice
index 08f6ab4..e5e2465 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_2.spice
-* Created: Thu Aug 27 21:03:02 2020
+* Created: Tue Sep  1 20:18:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.lvs.report b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.lvs.report
new file mode 100644
index 0000000..de53ccf
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o31ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o31ai_4.sp ('sky130_fd_sc_hs__o31ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o31ai/sky130_fd_sc_hs__o31ai_4.spice ('sky130_fd_sc_hs__o31ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:23 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o31ai_4      sky130_fd_sc_hs__o31ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o31ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o31ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         16        16         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_1 (6 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   30 layout mos transistors were reduced to 8.
+     22 mos transistors were deleted by parallel reduction.
+   30 source mos transistors were reduced to 8.
+     22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pex.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pex.spice
index e53e6d0..3e209f9 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_4.pex.spice
-* Created: Thu Aug 27 21:03:10 2020
+* Created: Tue Sep  1 20:18:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pxi.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pxi.spice
index fd0b584..02566ea 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_4.pxi.spice
-* Created: Thu Aug 27 21:03:10 2020
+* Created: Tue Sep  1 20:18:26 2020
 * 
 x_PM_SKY130_FD_SC_HS__O31AI_4%A1 N_A1_M1000_g N_A1_c_140_n N_A1_M1011_g
 + N_A1_c_141_n N_A1_M1012_g N_A1_M1004_g N_A1_c_142_n N_A1_M1013_g N_A1_M1022_g

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.spice b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.spice
index a1fafd3..439d42e 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.spice
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o31ai_4.spice
-* Created: Thu Aug 27 21:03:10 2020
+* Created: Tue Sep  1 20:18:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_1.lvs.report b/cells/o32a/sky130_fd_sc_hs__o32a_1.lvs.report
new file mode 100644
index 0000000..abca219
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_1.lvs.report

@@ -0,0 +1,470 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o32a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o32a_1.sp ('sky130_fd_sc_hs__o32a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o32a/sky130_fd_sc_hs__o32a_1.spice ('sky130_fd_sc_hs__o32a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o32a_1       sky130_fd_sc_hs__o32a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o32a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o32a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_2 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_1.pex.spice b/cells/o32a/sky130_fd_sc_hs__o32a_1.pex.spice
index a98ee46..081ac36 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_1.pex.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_1.pex.spice
-* Created: Thu Aug 27 21:03:18 2020
+* Created: Tue Sep  1 20:18:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_1.pxi.spice b/cells/o32a/sky130_fd_sc_hs__o32a_1.pxi.spice
index bcc2e5a..a833459 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_1.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_1.pxi.spice
-* Created: Thu Aug 27 21:03:18 2020
+* Created: Tue Sep  1 20:18:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__O32A_1%A_83_264# N_A_83_264#_M1003_d N_A_83_264#_M1005_d
 + N_A_83_264#_c_68_n N_A_83_264#_M1008_g N_A_83_264#_M1004_g N_A_83_264#_c_70_n

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_1.spice b/cells/o32a/sky130_fd_sc_hs__o32a_1.spice
index 54f0261..a5f9b55 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_1.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_1.spice
-* Created: Thu Aug 27 21:03:18 2020
+* Created: Tue Sep  1 20:18:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_2.lvs.report b/cells/o32a/sky130_fd_sc_hs__o32a_2.lvs.report
new file mode 100644
index 0000000..84e708e
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_2.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o32a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o32a_2.sp ('sky130_fd_sc_hs__o32a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o32a/sky130_fd_sc_hs__o32a_2.spice ('sky130_fd_sc_hs__o32a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o32a_2       sky130_fd_sc_hs__o32a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o32a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o32a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_2 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_2.pex.spice b/cells/o32a/sky130_fd_sc_hs__o32a_2.pex.spice
index 1ac0848..f0441eb 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_2.pex.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_2.pex.spice
-* Created: Thu Aug 27 21:03:25 2020
+* Created: Tue Sep  1 20:18:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_2.pxi.spice b/cells/o32a/sky130_fd_sc_hs__o32a_2.pxi.spice
index 9f5af49..c0adf1b 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_2.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_2.pxi.spice
-* Created: Thu Aug 27 21:03:25 2020
+* Created: Tue Sep  1 20:18:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__O32A_2%A_83_264# N_A_83_264#_M1001_d N_A_83_264#_M1008_d
 + N_A_83_264#_c_80_n N_A_83_264#_c_88_n N_A_83_264#_M1004_g N_A_83_264#_M1009_g

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_2.spice b/cells/o32a/sky130_fd_sc_hs__o32a_2.spice
index 0c6d6a5..27b31c8 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_2.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_2.spice
-* Created: Thu Aug 27 21:03:25 2020
+* Created: Tue Sep  1 20:18:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_4.lvs.report b/cells/o32a/sky130_fd_sc_hs__o32a_4.lvs.report
new file mode 100644
index 0000000..77ad510
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_4.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o32a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o32a_4.sp ('sky130_fd_sc_hs__o32a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o32a/sky130_fd_sc_hs__o32a_4.spice ('sky130_fd_sc_hs__o32a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o32a_4       sky130_fd_sc_hs__o32a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o32a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o32a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_2 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_4.pex.spice b/cells/o32a/sky130_fd_sc_hs__o32a_4.pex.spice
index 4d84f67..06f9a11 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_4.pex.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_4.pex.spice
-* Created: Thu Aug 27 21:03:34 2020
+* Created: Tue Sep  1 20:18:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_4.pxi.spice b/cells/o32a/sky130_fd_sc_hs__o32a_4.pxi.spice
index 34420e8..369144a 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_4.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_4.pxi.spice
-* Created: Thu Aug 27 21:03:34 2020
+* Created: Tue Sep  1 20:18:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__O32A_4%A_83_256# N_A_83_256#_M1008_d N_A_83_256#_M1021_s
 + N_A_83_256#_M1004_d N_A_83_256#_M1003_d N_A_83_256#_c_161_n

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_4.spice b/cells/o32a/sky130_fd_sc_hs__o32a_4.spice
index fa0c220..a9a16db 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_4.spice
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32a_4.spice
-* Created: Thu Aug 27 21:03:34 2020
+* Created: Tue Sep  1 20:18:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.lvs.report b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.lvs.report
new file mode 100644
index 0000000..04609fd
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o32ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o32ai_1.sp ('sky130_fd_sc_hs__o32ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o32ai/sky130_fd_sc_hs__o32ai_1.spice ('sky130_fd_sc_hs__o32ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o32ai_1      sky130_fd_sc_hs__o32ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o32ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o32ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_2 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pex.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pex.spice
index 4f90daf..3962817 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_1.pex.spice
-* Created: Thu Aug 27 21:03:42 2020
+* Created: Tue Sep  1 20:18:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pxi.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pxi.spice
index 09a9b0f..47da8b4 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_1.pxi.spice
-* Created: Thu Aug 27 21:03:42 2020
+* Created: Tue Sep  1 20:18:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__O32AI_1%B1 N_B1_c_48_n N_B1_M1008_g N_B1_c_49_n
 + N_B1_M1000_g B1 PM_SKY130_FD_SC_HS__O32AI_1%B1

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.spice
index 220bab2..1f1dc83 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_1.spice
-* Created: Thu Aug 27 21:03:42 2020
+* Created: Tue Sep  1 20:18:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.lvs.report b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.lvs.report
new file mode 100644
index 0000000..8f15b67
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o32ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o32ai_2.sp ('sky130_fd_sc_hs__o32ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o32ai/sky130_fd_sc_hs__o32ai_2.spice ('sky130_fd_sc_hs__o32ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:18:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o32ai_2      sky130_fd_sc_hs__o32ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o32ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o32ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_2 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pex.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pex.spice
index a49b4be..36b428a 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_2.pex.spice
-* Created: Thu Aug 27 21:03:53 2020
+* Created: Tue Sep  1 20:18:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pxi.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pxi.spice
index a95c1f2..4fdd565 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_2.pxi.spice
-* Created: Thu Aug 27 21:03:53 2020
+* Created: Tue Sep  1 20:18:58 2020
 * 
 x_PM_SKY130_FD_SC_HS__O32AI_2%B2 N_B2_M1017_g N_B2_c_101_n N_B2_M1007_g
 + N_B2_M1018_g N_B2_c_102_n N_B2_M1008_g B2 B2 B2 N_B2_c_100_n

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.spice
index 1d13309..67695bb 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_2.spice
-* Created: Thu Aug 27 21:03:53 2020
+* Created: Tue Sep  1 20:18:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.lvs.report b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.lvs.report
new file mode 100644
index 0000000..b962437
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o32ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o32ai_4.sp ('sky130_fd_sc_hs__o32ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o32ai/sky130_fd_sc_hs__o32ai_4.spice ('sky130_fd_sc_hs__o32ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o32ai_4      sky130_fd_sc_hs__o32ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o32ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o32ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         SMP2 (4 pins)
+                     1         1         SMP3 (5 pins)
+                     1         1         SPMN_3_2 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    SMP2
+                        1          1            0            0    SMP3
+                        1          1            0            0    SPMN_3_2
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   40 layout mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+   40 source mos transistors were reduced to 10.
+     30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pex.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pex.spice
index 8362d1d..1609837 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_4.pex.spice
-* Created: Thu Aug 27 21:04:00 2020
+* Created: Tue Sep  1 20:19:04 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pxi.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pxi.spice
index 9d20a58..5cdd773 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_4.pxi.spice
-* Created: Thu Aug 27 21:04:00 2020
+* Created: Tue Sep  1 20:19:04 2020
 * 
 x_PM_SKY130_FD_SC_HS__O32AI_4%B2 N_B2_M1014_g N_B2_c_159_n N_B2_M1016_g
 + N_B2_M1029_g N_B2_c_160_n N_B2_M1020_g N_B2_c_161_n N_B2_M1022_g N_B2_M1032_g

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.spice b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.spice
index 2f5f936..cedef2f 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.spice
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o32ai_4.spice
-* Created: Thu Aug 27 21:04:00 2020
+* Created: Tue Sep  1 20:19:04 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_1.lvs.report b/cells/o41a/sky130_fd_sc_hs__o41a_1.lvs.report
new file mode 100644
index 0000000..42d559f
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o41a_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o41a_1.sp ('sky130_fd_sc_hs__o41a_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o41a/sky130_fd_sc_hs__o41a_1.spice ('sky130_fd_sc_hs__o41a_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o41a_1       sky130_fd_sc_hs__o41a_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o41a_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o41a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                     1         1         SPMN_4_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                        1          1            0            0    SPMN_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A4 A3 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_1.pex.spice b/cells/o41a/sky130_fd_sc_hs__o41a_1.pex.spice
index 185702a..c0394c6 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_1.pex.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_1.pex.spice
-* Created: Thu Aug 27 21:04:08 2020
+* Created: Tue Sep  1 20:19:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_1.pxi.spice b/cells/o41a/sky130_fd_sc_hs__o41a_1.pxi.spice
index dce84a8..e6fdaa8 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_1.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_1.pxi.spice
-* Created: Thu Aug 27 21:04:08 2020
+* Created: Tue Sep  1 20:19:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__O41A_1%A_83_270# N_A_83_270#_M1004_s N_A_83_270#_M1006_d
 + N_A_83_270#_M1010_g N_A_83_270#_c_70_n N_A_83_270#_M1005_g N_A_83_270#_c_75_n

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_1.spice b/cells/o41a/sky130_fd_sc_hs__o41a_1.spice
index 4dd86a4..ad4f1b1 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_1.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_1.spice
-* Created: Thu Aug 27 21:04:08 2020
+* Created: Tue Sep  1 20:19:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_2.lvs.report b/cells/o41a/sky130_fd_sc_hs__o41a_2.lvs.report
new file mode 100644
index 0000000..22a6dc7
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o41a_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o41a_2.sp ('sky130_fd_sc_hs__o41a_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o41a/sky130_fd_sc_hs__o41a_2.spice ('sky130_fd_sc_hs__o41a_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:13 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o41a_2       sky130_fd_sc_hs__o41a_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o41a_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o41a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                     1         1         SPMN_4_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                        1          1            0            0    SPMN_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 A3 A4 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_2.pex.spice b/cells/o41a/sky130_fd_sc_hs__o41a_2.pex.spice
index 73d2a2d..fbae934 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_2.pex.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_2.pex.spice
-* Created: Thu Aug 27 21:04:16 2020
+* Created: Tue Sep  1 20:19:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_2.pxi.spice b/cells/o41a/sky130_fd_sc_hs__o41a_2.pxi.spice
index 6f6bbd6..44dc918 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_2.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_2.pxi.spice
-* Created: Thu Aug 27 21:04:16 2020
+* Created: Tue Sep  1 20:19:16 2020
 * 
 x_PM_SKY130_FD_SC_HS__O41A_2%A1 N_A1_M1011_g N_A1_c_73_n N_A1_M1007_g A1
 + N_A1_c_74_n PM_SKY130_FD_SC_HS__O41A_2%A1

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_2.spice b/cells/o41a/sky130_fd_sc_hs__o41a_2.spice
index 0e02b70..2fae0fc 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_2.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_2.spice
-* Created: Thu Aug 27 21:04:16 2020
+* Created: Tue Sep  1 20:19:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_4.lvs.report b/cells/o41a/sky130_fd_sc_hs__o41a_4.lvs.report
new file mode 100644
index 0000000..244ddce
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o41a_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o41a_4.sp ('sky130_fd_sc_hs__o41a_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o41a/sky130_fd_sc_hs__o41a_4.spice ('sky130_fd_sc_hs__o41a_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:19 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o41a_4       sky130_fd_sc_hs__o41a_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o41a_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o41a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          1         1         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                     1         1         SPMN_4_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                        1          1            0            0    SPMN_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A4 A3 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_4.pex.spice b/cells/o41a/sky130_fd_sc_hs__o41a_4.pex.spice
index c74ce19..6be9012 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_4.pex.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_4.pex.spice
-* Created: Thu Aug 27 21:04:24 2020
+* Created: Tue Sep  1 20:19:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_4.pxi.spice b/cells/o41a/sky130_fd_sc_hs__o41a_4.pxi.spice
index 7781dd1..7449aeb 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_4.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_4.pxi.spice
-* Created: Thu Aug 27 21:04:24 2020
+* Created: Tue Sep  1 20:19:23 2020
 * 
 x_PM_SKY130_FD_SC_HS__O41A_4%A_110_48# N_A_110_48#_M1005_s N_A_110_48#_M1016_d
 + N_A_110_48#_M1004_d N_A_110_48#_M1009_g N_A_110_48#_c_151_n

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_4.spice b/cells/o41a/sky130_fd_sc_hs__o41a_4.spice
index 2631f49..d785863 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_4.spice
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41a_4.spice
-* Created: Thu Aug 27 21:04:24 2020
+* Created: Tue Sep  1 20:19:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.lvs.report b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.lvs.report
new file mode 100644
index 0000000..27b308b
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o41ai_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o41ai_1.sp ('sky130_fd_sc_hs__o41ai_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o41ai/sky130_fd_sc_hs__o41ai_1.spice ('sky130_fd_sc_hs__o41ai_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o41ai_1      sky130_fd_sc_hs__o41ai_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o41ai_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__o41ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                     1         1         SPMN_4_1 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                        1          1            0            0    SPMN_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pex.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pex.spice
index 2a84ef1..a245cd3 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_1.pex.spice
-* Created: Thu Aug 27 21:04:31 2020
+* Created: Tue Sep  1 20:19:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pxi.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pxi.spice
index 3c175e2..550444d 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_1.pxi.spice
-* Created: Thu Aug 27 21:04:31 2020
+* Created: Tue Sep  1 20:19:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__O41AI_1%B1 N_B1_M1009_g N_B1_c_60_n N_B1_M1003_g
 + N_B1_c_57_n N_B1_c_58_n B1 PM_SKY130_FD_SC_HS__O41AI_1%B1

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.spice
index eeb6f21..e2b1bd5 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_1.spice
-* Created: Thu Aug 27 21:04:31 2020
+* Created: Tue Sep  1 20:19:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.lvs.report b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.lvs.report
new file mode 100644
index 0000000..7ef2b06
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o41ai_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o41ai_2.sp ('sky130_fd_sc_hs__o41ai_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o41ai/sky130_fd_sc_hs__o41ai_2.spice ('sky130_fd_sc_hs__o41ai_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o41ai_2      sky130_fd_sc_hs__o41ai_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o41ai_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__o41ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                     1         1         SPMN_4_1 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                        1          1            0            0    SPMN_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 10.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pex.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pex.spice
index a772bbc..1a435a0 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_2.pex.spice
-* Created: Thu Aug 27 21:04:40 2020
+* Created: Tue Sep  1 20:19:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pxi.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pxi.spice
index cef02ee..080b688 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_2.pxi.spice
-* Created: Thu Aug 27 21:04:40 2020
+* Created: Tue Sep  1 20:19:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__O41AI_2%B1 N_B1_c_120_n N_B1_M1001_g N_B1_c_121_n
 + N_B1_M1002_g N_B1_c_112_n N_B1_M1008_g N_B1_c_113_n N_B1_c_114_n N_B1_c_115_n

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.spice
index c3e7607..bc99e34 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_2.spice
-* Created: Thu Aug 27 21:04:40 2020
+* Created: Tue Sep  1 20:19:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.lvs.report b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.lvs.report
new file mode 100644
index 0000000..d903e5d
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__o41ai_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__o41ai_4.sp ('sky130_fd_sc_hs__o41ai_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/o41ai/sky130_fd_sc_hs__o41ai_4.spice ('sky130_fd_sc_hs__o41ai_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__o41ai_4      sky130_fd_sc_hs__o41ai_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__o41ai_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__o41ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         20        20         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        39        38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                     1         1         SPMN_4_1 (7 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                        1          1            0            0    SPMN_4_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   38 layout mos transistors were reduced to 10.
+     28 mos transistors were deleted by parallel reduction.
+   38 source mos transistors were reduced to 10.
+     28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pex.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pex.spice
index fbdcfdd..402fce2 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_4.pex.spice
-* Created: Thu Aug 27 21:04:48 2020
+* Created: Tue Sep  1 20:19:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pxi.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pxi.spice
index 9807683..44fd91d 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_4.pxi.spice
-* Created: Thu Aug 27 21:04:48 2020
+* Created: Tue Sep  1 20:19:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__O41AI_4%B1 N_B1_c_149_n N_B1_M1017_g N_B1_c_156_n
 + N_B1_M1015_g N_B1_c_150_n N_B1_M1022_g N_B1_c_157_n N_B1_M1026_g N_B1_c_151_n

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.spice b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.spice
index 40c5fba..07115c6 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.spice
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__o41ai_4.spice
-* Created: Thu Aug 27 21:04:48 2020
+* Created: Tue Sep  1 20:19:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or2/sky130_fd_sc_hs__or2_1.lvs.report b/cells/or2/sky130_fd_sc_hs__or2_1.lvs.report
new file mode 100644
index 0000000..c314134
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_hs__or2_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or2_1.sp ('sky130_fd_sc_hs__or2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or2/sky130_fd_sc_hs__or2_1.spice ('sky130_fd_sc_hs__or2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:45 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or2_1        sky130_fd_sc_hs__or2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or2/sky130_fd_sc_hs__or2_1.pex.spice b/cells/or2/sky130_fd_sc_hs__or2_1.pex.spice
index 3f86bf6..d3461a7 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_1.pex.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_1.pex.spice
-* Created: Thu Aug 27 21:04:59 2020
+* Created: Tue Sep  1 20:19:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or2/sky130_fd_sc_hs__or2_1.pxi.spice b/cells/or2/sky130_fd_sc_hs__or2_1.pxi.spice
index 023f6d7..4490e84 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_1.pxi.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_1.pxi.spice
-* Created: Thu Aug 27 21:04:59 2020
+* Created: Tue Sep  1 20:19:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR2_1%B N_B_c_41_n N_B_c_45_n N_B_M1000_g N_B_M1005_g B
 + N_B_c_42_n N_B_c_43_n PM_SKY130_FD_SC_HS__OR2_1%B

diff --git a/cells/or2/sky130_fd_sc_hs__or2_1.spice b/cells/or2/sky130_fd_sc_hs__or2_1.spice
index 685c8cf..a9db219 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_1.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_1.spice
-* Created: Thu Aug 27 21:04:59 2020
+* Created: Tue Sep  1 20:19:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or2/sky130_fd_sc_hs__or2_2.lvs.report b/cells/or2/sky130_fd_sc_hs__or2_2.lvs.report
new file mode 100644
index 0000000..cb1855c
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_hs__or2_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or2_2.sp ('sky130_fd_sc_hs__or2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or2/sky130_fd_sc_hs__or2_2.spice ('sky130_fd_sc_hs__or2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:51 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or2_2        sky130_fd_sc_hs__or2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or2/sky130_fd_sc_hs__or2_2.pex.spice b/cells/or2/sky130_fd_sc_hs__or2_2.pex.spice
index e55f9a6..e8a52b6 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_2.pex.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_2.pex.spice
-* Created: Thu Aug 27 21:05:07 2020
+* Created: Tue Sep  1 20:19:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or2/sky130_fd_sc_hs__or2_2.pxi.spice b/cells/or2/sky130_fd_sc_hs__or2_2.pxi.spice
index 5948e2e..2e1b0ea 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_2.pxi.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_2.pxi.spice
-* Created: Thu Aug 27 21:05:07 2020
+* Created: Tue Sep  1 20:19:54 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR2_2%B N_B_c_48_n N_B_M1004_g N_B_c_49_n N_B_M1001_g B
 + PM_SKY130_FD_SC_HS__OR2_2%B

diff --git a/cells/or2/sky130_fd_sc_hs__or2_2.spice b/cells/or2/sky130_fd_sc_hs__or2_2.spice
index cb82f33..493c341 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_2.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_2.spice
-* Created: Thu Aug 27 21:05:07 2020
+* Created: Tue Sep  1 20:19:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or2/sky130_fd_sc_hs__or2_4.lvs.report b/cells/or2/sky130_fd_sc_hs__or2_4.lvs.report
new file mode 100644
index 0000000..7f78821
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_hs__or2_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or2_4.sp ('sky130_fd_sc_hs__or2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or2/sky130_fd_sc_hs__or2_4.spice ('sky130_fd_sc_hs__or2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:19:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or2_4        sky130_fd_sc_hs__or2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 4.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or2/sky130_fd_sc_hs__or2_4.pex.spice b/cells/or2/sky130_fd_sc_hs__or2_4.pex.spice
index 3ceda22..b667084 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_4.pex.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_4.pex.spice
-* Created: Thu Aug 27 21:05:14 2020
+* Created: Tue Sep  1 20:20:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or2/sky130_fd_sc_hs__or2_4.pxi.spice b/cells/or2/sky130_fd_sc_hs__or2_4.pxi.spice
index b33b7a0..6e5f21e 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_4.pxi.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_4.pxi.spice
-* Created: Thu Aug 27 21:05:14 2020
+* Created: Tue Sep  1 20:20:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR2_4%A_83_260# N_A_83_260#_M1001_d N_A_83_260#_M1009_d
 + N_A_83_260#_M1002_g N_A_83_260#_c_87_n N_A_83_260#_M1004_g N_A_83_260#_M1003_g

diff --git a/cells/or2/sky130_fd_sc_hs__or2_4.spice b/cells/or2/sky130_fd_sc_hs__or2_4.spice
index 27bf1e1..4b3e6ad 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_4.spice
+++ b/cells/or2/sky130_fd_sc_hs__or2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2_4.spice
-* Created: Thu Aug 27 21:05:14 2020
+* Created: Tue Sep  1 20:20:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_1.lvs.report b/cells/or2b/sky130_fd_sc_hs__or2b_1.lvs.report
new file mode 100644
index 0000000..1d195ae
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or2b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or2b_1.sp ('sky130_fd_sc_hs__or2b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or2b/sky130_fd_sc_hs__or2b_1.spice ('sky130_fd_sc_hs__or2b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or2b_1       sky130_fd_sc_hs__or2b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or2b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_1.pex.spice b/cells/or2b/sky130_fd_sc_hs__or2b_1.pex.spice
index 20e406c..72e55c5 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_1.pex.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_1.pex.spice
-* Created: Thu Aug 27 21:05:22 2020
+* Created: Tue Sep  1 20:20:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_1.pxi.spice b/cells/or2b/sky130_fd_sc_hs__or2b_1.pxi.spice
index 1b8b4c8..91122dc 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_1.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_1.pxi.spice
-* Created: Thu Aug 27 21:05:22 2020
+* Created: Tue Sep  1 20:20:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR2B_1%B_N N_B_N_c_59_n N_B_N_c_64_n N_B_N_c_65_n
 + N_B_N_M1005_g N_B_N_c_60_n N_B_N_c_61_n N_B_N_M1002_g B_N

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_1.spice b/cells/or2b/sky130_fd_sc_hs__or2b_1.spice
index be5cc78..987ee72 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_1.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_1.spice
-* Created: Thu Aug 27 21:05:22 2020
+* Created: Tue Sep  1 20:20:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_2.lvs.report b/cells/or2b/sky130_fd_sc_hs__or2b_2.lvs.report
new file mode 100644
index 0000000..2fe3759
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or2b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or2b_2.sp ('sky130_fd_sc_hs__or2b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or2b/sky130_fd_sc_hs__or2b_2.spice ('sky130_fd_sc_hs__or2b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or2b_2       sky130_fd_sc_hs__or2b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or2b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_2.pex.spice b/cells/or2b/sky130_fd_sc_hs__or2b_2.pex.spice
index e5a6f3e..e657603 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_2.pex.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_2.pex.spice
-* Created: Thu Aug 27 21:05:30 2020
+* Created: Tue Sep  1 20:20:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_2.pxi.spice b/cells/or2b/sky130_fd_sc_hs__or2b_2.pxi.spice
index 5743206..477d3d5 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_2.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_2.pxi.spice
-* Created: Thu Aug 27 21:05:30 2020
+* Created: Tue Sep  1 20:20:13 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR2B_2%B_N N_B_N_M1002_g N_B_N_c_64_n N_B_N_M1007_g B_N
 + N_B_N_c_65_n PM_SKY130_FD_SC_HS__OR2B_2%B_N

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_2.spice b/cells/or2b/sky130_fd_sc_hs__or2b_2.spice
index 6ebe04b..8dda662 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_2.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_2.spice
-* Created: Thu Aug 27 21:05:30 2020
+* Created: Tue Sep  1 20:20:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_4.lvs.report b/cells/or2b/sky130_fd_sc_hs__or2b_4.lvs.report
new file mode 100644
index 0000000..368c76d
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or2b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or2b_4.sp ('sky130_fd_sc_hs__or2b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or2b/sky130_fd_sc_hs__or2b_4.spice ('sky130_fd_sc_hs__or2b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:16 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or2b_4       sky130_fd_sc_hs__or2b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or2b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              10        10
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        19        18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP2 (4 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_4.pex.spice b/cells/or2b/sky130_fd_sc_hs__or2b_4.pex.spice
index 194ac35..2e1ecf8 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_4.pex.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_4.pex.spice
-* Created: Thu Aug 27 21:05:38 2020
+* Created: Tue Sep  1 20:20:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_4.pxi.spice b/cells/or2b/sky130_fd_sc_hs__or2b_4.pxi.spice
index 229f3fb..2755637 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_4.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_4.pxi.spice
-* Created: Thu Aug 27 21:05:38 2020
+* Created: Tue Sep  1 20:20:19 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR2B_4%A_81_296# N_A_81_296#_M1005_d N_A_81_296#_M1008_d
 + N_A_81_296#_M1006_d N_A_81_296#_M1007_g N_A_81_296#_c_129_n

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_4.spice b/cells/or2b/sky130_fd_sc_hs__or2b_4.spice
index a4fa464..7112548 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_4.spice
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or2b_4.spice
-* Created: Thu Aug 27 21:05:38 2020
+* Created: Tue Sep  1 20:20:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or3/sky130_fd_sc_hs__or3_1.lvs.report b/cells/or3/sky130_fd_sc_hs__or3_1.lvs.report
new file mode 100644
index 0000000..9bee658
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_hs__or3_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or3_1.sp ('sky130_fd_sc_hs__or3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or3/sky130_fd_sc_hs__or3_1.spice ('sky130_fd_sc_hs__or3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:22 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or3_1        sky130_fd_sc_hs__or3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or3/sky130_fd_sc_hs__or3_1.pex.spice b/cells/or3/sky130_fd_sc_hs__or3_1.pex.spice
index a2b9980..a580159 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_1.pex.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_1.pex.spice
-* Created: Thu Aug 27 21:05:47 2020
+* Created: Tue Sep  1 20:20:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or3/sky130_fd_sc_hs__or3_1.pxi.spice b/cells/or3/sky130_fd_sc_hs__or3_1.pxi.spice
index b000c1b..6ca81f4 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_1.pxi.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_1.pxi.spice
-* Created: Thu Aug 27 21:05:47 2020
+* Created: Tue Sep  1 20:20:25 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR3_1%C N_C_M1006_g N_C_c_50_n N_C_M1005_g C N_C_c_51_n
 + PM_SKY130_FD_SC_HS__OR3_1%C

diff --git a/cells/or3/sky130_fd_sc_hs__or3_1.spice b/cells/or3/sky130_fd_sc_hs__or3_1.spice
index 7fc7606..1b24887 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_1.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_1.spice
-* Created: Thu Aug 27 21:05:47 2020
+* Created: Tue Sep  1 20:20:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or3/sky130_fd_sc_hs__or3_2.lvs.report b/cells/or3/sky130_fd_sc_hs__or3_2.lvs.report
new file mode 100644
index 0000000..be19afc
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_hs__or3_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or3_2.sp ('sky130_fd_sc_hs__or3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or3/sky130_fd_sc_hs__or3_2.spice ('sky130_fd_sc_hs__or3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:29 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or3_2        sky130_fd_sc_hs__or3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or3/sky130_fd_sc_hs__or3_2.pex.spice b/cells/or3/sky130_fd_sc_hs__or3_2.pex.spice
index a3e5e5f..acfdcb4 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_2.pex.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_2.pex.spice
-* Created: Thu Aug 27 21:05:55 2020
+* Created: Tue Sep  1 20:20:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or3/sky130_fd_sc_hs__or3_2.pxi.spice b/cells/or3/sky130_fd_sc_hs__or3_2.pxi.spice
index fb72917..522c56e 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_2.pxi.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_2.pxi.spice
-* Created: Thu Aug 27 21:05:55 2020
+* Created: Tue Sep  1 20:20:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR3_2%C N_C_M1009_g N_C_c_61_n N_C_c_66_n N_C_M1001_g C C
 + N_C_c_62_n N_C_c_63_n N_C_c_64_n PM_SKY130_FD_SC_HS__OR3_2%C

diff --git a/cells/or3/sky130_fd_sc_hs__or3_2.spice b/cells/or3/sky130_fd_sc_hs__or3_2.spice
index 2c3a888..9b0591a 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_2.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_2.spice
-* Created: Thu Aug 27 21:05:55 2020
+* Created: Tue Sep  1 20:20:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or3/sky130_fd_sc_hs__or3_4.lvs.report b/cells/or3/sky130_fd_sc_hs__or3_4.lvs.report
new file mode 100644
index 0000000..d6f5f0a
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_hs__or3_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or3_4.sp ('sky130_fd_sc_hs__or3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or3/sky130_fd_sc_hs__or3_4.spice ('sky130_fd_sc_hs__or3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:35 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or3_4        sky130_fd_sc_hs__or3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        18        17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or3/sky130_fd_sc_hs__or3_4.pex.spice b/cells/or3/sky130_fd_sc_hs__or3_4.pex.spice
index 33a8afa..03deb01 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_4.pex.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_4.pex.spice
-* Created: Thu Aug 27 21:06:05 2020
+* Created: Tue Sep  1 20:20:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or3/sky130_fd_sc_hs__or3_4.pxi.spice b/cells/or3/sky130_fd_sc_hs__or3_4.pxi.spice
index 140684b..7bb0096 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_4.pxi.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_4.pxi.spice
-* Created: Thu Aug 27 21:06:05 2020
+* Created: Tue Sep  1 20:20:38 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR3_4%A N_A_c_93_n N_A_c_105_n N_A_M1008_g N_A_c_94_n
 + N_A_c_107_n N_A_M1014_g N_A_M1004_g N_A_c_95_n N_A_c_96_n N_A_c_97_n

diff --git a/cells/or3/sky130_fd_sc_hs__or3_4.spice b/cells/or3/sky130_fd_sc_hs__or3_4.spice
index 7195ff3..e19d88c 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_4.spice
+++ b/cells/or3/sky130_fd_sc_hs__or3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3_4.spice
-* Created: Thu Aug 27 21:06:05 2020
+* Created: Tue Sep  1 20:20:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_1.lvs.report b/cells/or3b/sky130_fd_sc_hs__or3b_1.lvs.report
new file mode 100644
index 0000000..fc4e193
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or3b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or3b_1.sp ('sky130_fd_sc_hs__or3b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or3b/sky130_fd_sc_hs__or3b_1.spice ('sky130_fd_sc_hs__or3b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:41 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or3b_1       sky130_fd_sc_hs__or3b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or3b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_1.pex.spice b/cells/or3b/sky130_fd_sc_hs__or3b_1.pex.spice
index 94fc512..d9bf92e 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_1.pex.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_1.pex.spice
-* Created: Thu Aug 27 21:06:13 2020
+* Created: Tue Sep  1 20:20:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_1.pxi.spice b/cells/or3b/sky130_fd_sc_hs__or3b_1.pxi.spice
index bd63594..23de946 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_1.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_1.pxi.spice
-* Created: Thu Aug 27 21:06:13 2020
+* Created: Tue Sep  1 20:20:44 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR3B_1%C_N N_C_N_c_77_n N_C_N_c_82_n N_C_N_c_83_n
 + N_C_N_M1001_g N_C_N_M1008_g N_C_N_c_79_n C_N C_N N_C_N_c_80_n N_C_N_c_81_n

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_1.spice b/cells/or3b/sky130_fd_sc_hs__or3b_1.spice
index ba0b2f9..12a76d7 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_1.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_1.spice
-* Created: Thu Aug 27 21:06:13 2020
+* Created: Tue Sep  1 20:20:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_2.lvs.report b/cells/or3b/sky130_fd_sc_hs__or3b_2.lvs.report
new file mode 100644
index 0000000..ba806c0
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or3b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or3b_2.sp ('sky130_fd_sc_hs__or3b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or3b/sky130_fd_sc_hs__or3b_2.spice ('sky130_fd_sc_hs__or3b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:47 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or3b_2       sky130_fd_sc_hs__or3b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or3b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_2.pex.spice b/cells/or3b/sky130_fd_sc_hs__or3b_2.pex.spice
index 3e64f95..d0c3309 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_2.pex.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_2.pex.spice
-* Created: Thu Aug 27 21:06:21 2020
+* Created: Tue Sep  1 20:20:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_2.pxi.spice b/cells/or3b/sky130_fd_sc_hs__or3b_2.pxi.spice
index a6f595c..55e6aac 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_2.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_2.pxi.spice
-* Created: Thu Aug 27 21:06:21 2020
+* Created: Tue Sep  1 20:20:50 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR3B_2%C_N N_C_N_c_68_n N_C_N_M1009_g N_C_N_M1007_g C_N
 + N_C_N_c_70_n PM_SKY130_FD_SC_HS__OR3B_2%C_N

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_2.spice b/cells/or3b/sky130_fd_sc_hs__or3b_2.spice
index 817f1a4..4db5c45 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_2.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_2.spice
-* Created: Thu Aug 27 21:06:21 2020
+* Created: Tue Sep  1 20:20:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_4.lvs.report b/cells/or3b/sky130_fd_sc_hs__or3b_4.lvs.report
new file mode 100644
index 0000000..ad8adc7
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or3b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or3b_4.sp ('sky130_fd_sc_hs__or3b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or3b/sky130_fd_sc_hs__or3b_4.spice ('sky130_fd_sc_hs__or3b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:20:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or3b_4       sky130_fd_sc_hs__or3b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or3b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          8         8         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        20        19
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP3 (5 pins)
+                ------    ------
+ Total Inst:         8         8
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP3
+                  -------    -------    ---------    ---------
+   Total Inst:          8          8            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 5.
+     9 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_4.pex.spice b/cells/or3b/sky130_fd_sc_hs__or3b_4.pex.spice
index 8a10604..2095b9a 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_4.pex.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_4.pex.spice
-* Created: Thu Aug 27 21:06:29 2020
+* Created: Tue Sep  1 20:20:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_4.pxi.spice b/cells/or3b/sky130_fd_sc_hs__or3b_4.pxi.spice
index 1d43f8e..737ca7f 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_4.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_4.pxi.spice
-* Created: Thu Aug 27 21:06:29 2020
+* Created: Tue Sep  1 20:20:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR3B_4%C_N N_C_N_c_112_n N_C_N_c_113_n N_C_N_c_119_n
 + N_C_N_M1013_g N_C_N_M1017_g C_N N_C_N_c_115_n N_C_N_c_116_n N_C_N_c_117_n

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_4.spice b/cells/or3b/sky130_fd_sc_hs__or3b_4.spice
index c7e8d5f..e89a20f 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_4.spice
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or3b_4.spice
-* Created: Thu Aug 27 21:06:29 2020
+* Created: Tue Sep  1 20:20:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4/sky130_fd_sc_hs__or4_1.lvs.report b/cells/or4/sky130_fd_sc_hs__or4_1.lvs.report
new file mode 100644
index 0000000..3864dba
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_hs__or4_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4_1.sp ('sky130_fd_sc_hs__or4_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4/sky130_fd_sc_hs__or4_1.spice ('sky130_fd_sc_hs__or4_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4_1        sky130_fd_sc_hs__or4_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4/sky130_fd_sc_hs__or4_1.pex.spice b/cells/or4/sky130_fd_sc_hs__or4_1.pex.spice
index 2181719..9020097 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_1.pex.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_1.pex.spice
-* Created: Thu Aug 27 21:06:37 2020
+* Created: Tue Sep  1 20:21:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4/sky130_fd_sc_hs__or4_1.pxi.spice b/cells/or4/sky130_fd_sc_hs__or4_1.pxi.spice
index 784c189..9136185 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_1.pxi.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_1.pxi.spice
-* Created: Thu Aug 27 21:06:37 2020
+* Created: Tue Sep  1 20:21:03 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4_1%D N_D_M1005_g N_D_c_59_n N_D_M1008_g D N_D_c_60_n
 + PM_SKY130_FD_SC_HS__OR4_1%D

diff --git a/cells/or4/sky130_fd_sc_hs__or4_1.spice b/cells/or4/sky130_fd_sc_hs__or4_1.spice
index 88bff24..4f92453 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_1.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_1.spice
-* Created: Thu Aug 27 21:06:37 2020
+* Created: Tue Sep  1 20:21:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4/sky130_fd_sc_hs__or4_2.lvs.report b/cells/or4/sky130_fd_sc_hs__or4_2.lvs.report
new file mode 100644
index 0000000..43254da
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_hs__or4_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4_2.sp ('sky130_fd_sc_hs__or4_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4/sky130_fd_sc_hs__or4_2.spice ('sky130_fd_sc_hs__or4_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4_2        sky130_fd_sc_hs__or4_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4/sky130_fd_sc_hs__or4_2.pex.spice b/cells/or4/sky130_fd_sc_hs__or4_2.pex.spice
index e6d9c30..39e38b1 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_2.pex.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_2.pex.spice
-* Created: Thu Aug 27 21:06:44 2020
+* Created: Tue Sep  1 20:21:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4/sky130_fd_sc_hs__or4_2.pxi.spice b/cells/or4/sky130_fd_sc_hs__or4_2.pxi.spice
index c7d28e5..f58d91f 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_2.pxi.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_2.pxi.spice
-* Created: Thu Aug 27 21:06:44 2020
+* Created: Tue Sep  1 20:21:09 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4_2%D N_D_M1007_g N_D_c_67_n N_D_M1002_g D
 + PM_SKY130_FD_SC_HS__OR4_2%D

diff --git a/cells/or4/sky130_fd_sc_hs__or4_2.spice b/cells/or4/sky130_fd_sc_hs__or4_2.spice
index 445dd65..c1bf361 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_2.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_2.spice
-* Created: Thu Aug 27 21:06:44 2020
+* Created: Tue Sep  1 20:21:09 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4/sky130_fd_sc_hs__or4_4.lvs.report b/cells/or4/sky130_fd_sc_hs__or4_4.lvs.report
new file mode 100644
index 0000000..e80ec15
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_hs__or4_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4_4.sp ('sky130_fd_sc_hs__or4_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4/sky130_fd_sc_hs__or4_4.spice ('sky130_fd_sc_hs__or4_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:13 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4_4        sky130_fd_sc_hs__or4_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          8         8         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           5          5            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A C D VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4/sky130_fd_sc_hs__or4_4.pex.spice b/cells/or4/sky130_fd_sc_hs__or4_4.pex.spice
index 37d3be0..f866aa8 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_4.pex.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_4.pex.spice
-* Created: Thu Aug 27 21:06:53 2020
+* Created: Tue Sep  1 20:21:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4/sky130_fd_sc_hs__or4_4.pxi.spice b/cells/or4/sky130_fd_sc_hs__or4_4.pxi.spice
index a34f481..ff7a672 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_4.pxi.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_4.pxi.spice
-* Created: Thu Aug 27 21:06:53 2020
+* Created: Tue Sep  1 20:21:16 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4_4%A_83_264# N_A_83_264#_M1003_d N_A_83_264#_M1015_d
 + N_A_83_264#_M1014_d N_A_83_264#_c_120_n N_A_83_264#_M1010_g

diff --git a/cells/or4/sky130_fd_sc_hs__or4_4.spice b/cells/or4/sky130_fd_sc_hs__or4_4.spice
index 71514af..383a92d 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_4.spice
+++ b/cells/or4/sky130_fd_sc_hs__or4_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4_4.spice
-* Created: Thu Aug 27 21:06:53 2020
+* Created: Tue Sep  1 20:21:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_1.lvs.report b/cells/or4b/sky130_fd_sc_hs__or4b_1.lvs.report
new file mode 100644
index 0000000..333c626
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4b_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4b_1.sp ('sky130_fd_sc_hs__or4b_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4b/sky130_fd_sc_hs__or4b_1.spice ('sky130_fd_sc_hs__or4b_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:19 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4b_1       sky130_fd_sc_hs__or4b_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4b_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N C B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_1.pex.spice b/cells/or4b/sky130_fd_sc_hs__or4b_1.pex.spice
index ca0be3f..c478bee 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_1.pex.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_1.pex.spice
-* Created: Thu Aug 27 21:07:01 2020
+* Created: Tue Sep  1 20:21:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_1.pxi.spice b/cells/or4b/sky130_fd_sc_hs__or4b_1.pxi.spice
index b09c195..222e493 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_1.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_1.pxi.spice
-* Created: Thu Aug 27 21:07:01 2020
+* Created: Tue Sep  1 20:21:22 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4B_1%D_N N_D_N_M1008_g N_D_N_c_81_n N_D_N_c_84_n
 + N_D_N_c_85_n N_D_N_M1004_g D_N N_D_N_c_82_n PM_SKY130_FD_SC_HS__OR4B_1%D_N

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_1.spice b/cells/or4b/sky130_fd_sc_hs__or4b_1.spice
index d4dbfea..f83e1bc 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_1.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_1.spice
-* Created: Thu Aug 27 21:07:01 2020
+* Created: Tue Sep  1 20:21:22 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_2.lvs.report b/cells/or4b/sky130_fd_sc_hs__or4b_2.lvs.report
new file mode 100644
index 0000000..05aeb10
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4b_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4b_2.sp ('sky130_fd_sc_hs__or4b_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4b/sky130_fd_sc_hs__or4b_2.spice ('sky130_fd_sc_hs__or4b_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:25 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4b_2       sky130_fd_sc_hs__or4b_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4b_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_2.pex.spice b/cells/or4b/sky130_fd_sc_hs__or4b_2.pex.spice
index b3ea591..5d086cd 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_2.pex.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_2.pex.spice
-* Created: Thu Aug 27 21:07:12 2020
+* Created: Tue Sep  1 20:21:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_2.pxi.spice b/cells/or4b/sky130_fd_sc_hs__or4b_2.pxi.spice
index ef157e7..d6a247e 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_2.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_2.pxi.spice
-* Created: Thu Aug 27 21:07:12 2020
+* Created: Tue Sep  1 20:21:28 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4B_2%D_N N_D_N_c_80_n N_D_N_M1006_g N_D_N_M1010_g D_N
 + N_D_N_c_82_n PM_SKY130_FD_SC_HS__OR4B_2%D_N

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_2.spice b/cells/or4b/sky130_fd_sc_hs__or4b_2.spice
index e7d7d1f..a665816 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_2.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_2.spice
-* Created: Thu Aug 27 21:07:12 2020
+* Created: Tue Sep  1 20:21:28 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_4.lvs.report b/cells/or4b/sky130_fd_sc_hs__or4b_4.lvs.report
new file mode 100644
index 0000000..4b903a9
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4b_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4b_4.sp ('sky130_fd_sc_hs__or4b_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4b/sky130_fd_sc_hs__or4b_4.spice ('sky130_fd_sc_hs__or4b_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4b_4       sky130_fd_sc_hs__or4b_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4b_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              14        14
+
+ Instances:          9         9         MN (4 pins)
+                    13        13         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              11        11
+
+ Instances:          6         6         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:         9         9
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           6          6            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:          9          9            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A C D_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_4.pex.spice b/cells/or4b/sky130_fd_sc_hs__or4b_4.pex.spice
index 39126e1..f332c56 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_4.pex.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_4.pex.spice
-* Created: Thu Aug 27 21:07:20 2020
+* Created: Tue Sep  1 20:21:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_4.pxi.spice b/cells/or4b/sky130_fd_sc_hs__or4b_4.pxi.spice
index 0451380..cbadc49 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_4.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_4.pxi.spice
-* Created: Thu Aug 27 21:07:20 2020
+* Created: Tue Sep  1 20:21:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4B_4%B N_B_c_130_n N_B_M1020_g N_B_c_140_n N_B_M1006_g
 + N_B_c_131_n N_B_c_142_n N_B_M1011_g N_B_c_132_n N_B_c_133_n N_B_c_134_n B B

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_4.spice b/cells/or4b/sky130_fd_sc_hs__or4b_4.spice
index 79cc478..c7b7224 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_4.spice
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4b_4.spice
-* Created: Thu Aug 27 21:07:20 2020
+* Created: Tue Sep  1 20:21:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.lvs.report b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.lvs.report
new file mode 100644
index 0000000..d627999
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.lvs.report

@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4bb_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4bb_1.sp ('sky130_fd_sc_hs__or4bb_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4bb/sky130_fd_sc_hs__or4bb_1.spice ('sky130_fd_sc_hs__or4bb_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:38 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4bb_1      sky130_fd_sc_hs__or4bb_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4bb_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          7         7         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:        11        11
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:         11         11            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C_N D_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pex.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pex.spice
index 6d7a189..a78371f 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_1.pex.spice
-* Created: Thu Aug 27 21:07:28 2020
+* Created: Tue Sep  1 20:21:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pxi.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pxi.spice
index 8eca669..9260078 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_1.pxi.spice
-* Created: Thu Aug 27 21:07:28 2020
+* Created: Tue Sep  1 20:21:41 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4BB_1%C_N N_C_N_c_93_n N_C_N_c_98_n N_C_N_M1009_g
 + N_C_N_M1003_g C_N N_C_N_c_95_n N_C_N_c_96_n PM_SKY130_FD_SC_HS__OR4BB_1%C_N

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.spice
index 79e21cf..fe5e057 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_1.spice
-* Created: Thu Aug 27 21:07:28 2020
+* Created: Tue Sep  1 20:21:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.lvs.report b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.lvs.report
new file mode 100644
index 0000000..1116a45
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4bb_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4bb_2.sp ('sky130_fd_sc_hs__or4bb_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4bb/sky130_fd_sc_hs__or4bb_2.spice ('sky130_fd_sc_hs__or4bb_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:44 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4bb_2      sky130_fd_sc_hs__or4bb_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4bb_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          7         7         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:        11        11
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:         11         11            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N B A C_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pex.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pex.spice
index 84e256e..c7490b5 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_2.pex.spice
-* Created: Thu Aug 27 21:07:35 2020
+* Created: Tue Sep  1 20:21:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pxi.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pxi.spice
index ee1380a..67e0df1 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_2.pxi.spice
-* Created: Thu Aug 27 21:07:35 2020
+* Created: Tue Sep  1 20:21:47 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4BB_2%D_N N_D_N_c_96_n N_D_N_c_100_n N_D_N_c_101_n
 + N_D_N_M1002_g N_D_N_c_97_n N_D_N_M1007_g D_N N_D_N_c_98_n

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.spice
index 1a15c53..a7af212 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_2.spice
-* Created: Thu Aug 27 21:07:35 2020
+* Created: Tue Sep  1 20:21:47 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.lvs.report b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.lvs.report
new file mode 100644
index 0000000..30edc88
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.lvs.report

@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__or4bb_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__or4bb_4.sp ('sky130_fd_sc_hs__or4bb_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/or4bb/sky130_fd_sc_hs__or4bb_4.spice ('sky130_fd_sc_hs__or4bb_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__or4bb_4      sky130_fd_sc_hs__or4bb_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__or4bb_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__or4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              15        15
+
+ Instances:         10        10         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          7         7         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         1         SMP4 (6 pins)
+                ------    ------
+ Total Inst:        11        11
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               12         12            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMP4
+                  -------    -------    ---------    ---------
+   Total Inst:         11         11            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 6.
+     10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D_N C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pex.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pex.spice
index 3681d15..235a389 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_4.pex.spice
-* Created: Thu Aug 27 21:07:43 2020
+* Created: Tue Sep  1 20:21:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pxi.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pxi.spice
index 94373a4..dded8ce 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_4.pxi.spice
-* Created: Thu Aug 27 21:07:43 2020
+* Created: Tue Sep  1 20:21:53 2020
 * 
 x_PM_SKY130_FD_SC_HS__OR4BB_4%D_N N_D_N_M1004_g N_D_N_c_139_n N_D_N_M1013_g D_N
 + N_D_N_c_140_n PM_SKY130_FD_SC_HS__OR4BB_4%D_N

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.spice b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.spice
index ec3d566..20223b0 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.spice
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__or4bb_4.spice
-* Created: Thu Aug 27 21:07:43 2020
+* Created: Tue Sep  1 20:21:53 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.lvs.report b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.lvs.report
new file mode 100644
index 0000000..550f85a
--- /dev/null
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.lvs.report

@@ -0,0 +1,470 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfbbn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfbbn_1.sp ('sky130_fd_sc_hs__sdfbbn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.spice ('sky130_fd_sc_hs__sdfbbn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:21:57 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfbbn_1     sky130_fd_sc_hs__sdfbbn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfbbn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfbbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             12        12
+
+ Nets:              36        36
+
+ Instances:         24        24         MN (4 pins)
+                    24        24         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        49        48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             12        12
+
+ Nets:              22        22
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     7         7         SMP2 (4 pins)
+                     2         2         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              12         12            0            0
+
+   Nets:               22         22            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        7          7            0            0    SMP2
+                        2          2            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pex.spice b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pex.spice
index a0f2871..ae6f8ed 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pex.spice
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbn_1.pex.spice
-* Created: Thu Aug 27 21:07:51 2020
+* Created: Tue Sep  1 20:22:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pxi.spice b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pxi.spice
index d295228..a96c96a 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pxi.spice
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbn_1.pxi.spice
-* Created: Thu Aug 27 21:07:51 2020
+* Created: Tue Sep  1 20:22:00 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFBBN_1%SCD N_SCD_c_375_n N_SCD_c_380_n N_SCD_c_381_n
 + N_SCD_M1020_g N_SCD_M1004_g N_SCD_c_382_n SCD N_SCD_c_377_n N_SCD_c_378_n

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.spice b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.spice
index bab846f..42bf8fa 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.spice
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbn_1.spice
-* Created: Thu Aug 27 21:07:51 2020
+* Created: Tue Sep  1 20:22:00 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.lvs.report b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.lvs.report
new file mode 100644
index 0000000..eab7fdd
--- /dev/null
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfbbn_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfbbn_2.sp ('sky130_fd_sc_hs__sdfbbn_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.spice ('sky130_fd_sc_hs__sdfbbn_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfbbn_2     sky130_fd_sc_hs__sdfbbn_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfbbn_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfbbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             12        12
+
+ Nets:              36        36
+
+ Instances:         26        26         MN (4 pins)
+                    26        26         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        53        52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             12        12
+
+ Nets:              22        22
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     7         7         SMP2 (4 pins)
+                     2         2         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              12         12            0            0
+
+   Nets:               22         22            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        7          7            0            0    SMP2
+                        2          2            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pex.spice b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pex.spice
index 1984f8e..20267e0 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pex.spice
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbn_2.pex.spice
-* Created: Thu Aug 27 21:08:00 2020
+* Created: Tue Sep  1 20:22:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pxi.spice b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pxi.spice
index e8ecd7b..ead46f8 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pxi.spice
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbn_2.pxi.spice
-* Created: Thu Aug 27 21:08:00 2020
+* Created: Tue Sep  1 20:22:06 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFBBN_2%SCD N_SCD_c_377_n N_SCD_c_382_n N_SCD_M1024_g
 + N_SCD_M1004_g SCD SCD N_SCD_c_378_n N_SCD_c_379_n N_SCD_c_380_n

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.spice b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.spice
index edef594..fee87fe 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.spice
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbn_2.spice
-* Created: Thu Aug 27 21:08:00 2020
+* Created: Tue Sep  1 20:22:06 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.lvs.report b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.lvs.report
new file mode 100644
index 0000000..32b4612
--- /dev/null
+++ b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.lvs.report

@@ -0,0 +1,470 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfbbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfbbp_1.sp ('sky130_fd_sc_hs__sdfbbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.spice ('sky130_fd_sc_hs__sdfbbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfbbp_1     sky130_fd_sc_hs__sdfbbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfbbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfbbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             12        12
+
+ Nets:              36        36
+
+ Instances:         24        24         MN (4 pins)
+                    24        24         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        49        48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             12        12
+
+ Nets:              22        22
+
+ Instances:          8         8         MN (4 pins)
+                    10        10         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     7         7         SMP2 (4 pins)
+                     2         2         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              12         12            0            0
+
+   Nets:               22         22            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        7          7            0            0    SMP2
+                        2          2            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCD D SCE CLK SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pex.spice b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pex.spice
index c840714..d51196e 100644
--- a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pex.spice
+++ b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbp_1.pex.spice
-* Created: Thu Aug 27 21:08:08 2020
+* Created: Tue Sep  1 20:22:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pxi.spice b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pxi.spice
index db581bd..bd6f5c2 100644
--- a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pxi.spice
+++ b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbp_1.pxi.spice
-* Created: Thu Aug 27 21:08:08 2020
+* Created: Tue Sep  1 20:22:13 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFBBP_1%SCD N_SCD_c_329_n N_SCD_c_334_n N_SCD_M1022_g
 + N_SCD_M1008_g SCD SCD N_SCD_c_330_n N_SCD_c_331_n N_SCD_c_332_n

diff --git a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.spice b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.spice
index f450fc9..37384b2 100644
--- a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.spice
+++ b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfbbp_1.spice
-* Created: Thu Aug 27 21:08:08 2020
+* Created: Tue Sep  1 20:22:13 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.lvs.report b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.lvs.report
new file mode 100644
index 0000000..27f6bda
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.lvs.report

@@ -0,0 +1,472 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfrbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfrbp_1.sp ('sky130_fd_sc_hs__sdfrbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.spice ('sky130_fd_sc_hs__sdfrbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:16 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfrbp_1     sky130_fd_sc_hs__sdfrbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfrbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              31        31
+
+ Instances:         21        21         MN (4 pins)
+                    21        21         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        43        42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              20        20
+
+ Instances:          9         9         MN (4 pins)
+                    13        13         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     4         4         SMP2 (4 pins)
+                     1         1         SPMN((2+2)*1) (7 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           9          9            0            0    MN(NLOWVT)
+                       13         13            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SMN3
+                        4          4            0            0    SMP2
+                        1          1            0            0    SPMN((2+2)*1)
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pex.spice b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pex.spice
index e8d3e7a..65ce4b6 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrbp_1.pex.spice
-* Created: Thu Aug 27 21:08:19 2020
+* Created: Tue Sep  1 20:22:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pxi.spice b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pxi.spice
index 5697df0..8c76d96 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrbp_1.pxi.spice
-* Created: Thu Aug 27 21:08:19 2020
+* Created: Tue Sep  1 20:22:19 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFRBP_1%A_27_74# N_A_27_74#_M1040_s N_A_27_74#_M1027_s
 + N_A_27_74#_c_288_n N_A_27_74#_M1021_g N_A_27_74#_c_294_n N_A_27_74#_M1014_g

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.spice b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.spice
index 8b49998..93d04f5 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrbp_1.spice
-* Created: Thu Aug 27 21:08:19 2020
+* Created: Tue Sep  1 20:22:19 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.lvs.report b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.lvs.report
new file mode 100644
index 0000000..1dd6043
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.lvs.report

@@ -0,0 +1,477 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfrbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfrbp_2.sp ('sky130_fd_sc_hs__sdfrbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.spice ('sky130_fd_sc_hs__sdfrbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:22 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfrbp_2     sky130_fd_sc_hs__sdfrbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfrbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              31        31
+
+ Instances:         23        23         MN (4 pins)
+                    23        23         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        47        46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              20        20
+
+ Instances:          9         9         MN (4 pins)
+                    13        13         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     4         4         SMP2 (4 pins)
+                     1         1         SPMN((2+2)*1) (7 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           9          9            0            0    MN(NLOWVT)
+                       13         13            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SMN3
+                        4          4            0            0    SMP2
+                        1          1            0            0    SPMN((2+2)*1)
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pex.spice b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pex.spice
index fd7d8e5..378b008 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrbp_2.pex.spice
-* Created: Thu Aug 27 21:08:27 2020
+* Created: Tue Sep  1 20:22:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pxi.spice b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pxi.spice
index 0e1a998..db40a9d 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrbp_2.pxi.spice
-* Created: Thu Aug 27 21:08:27 2020
+* Created: Tue Sep  1 20:22:25 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFRBP_2%A_27_79# N_A_27_79#_M1033_s N_A_27_79#_M1023_s
 + N_A_27_79#_M1014_g N_A_27_79#_c_289_n N_A_27_79#_M1026_g N_A_27_79#_c_284_n

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.spice b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.spice
index 01ceb3f..8f2e282 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.spice
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrbp_2.spice
-* Created: Thu Aug 27 21:08:27 2020
+* Created: Tue Sep  1 20:22:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.lvs.report b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.lvs.report
new file mode 100644
index 0000000..bba7336
--- /dev/null
+++ b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.lvs.report

@@ -0,0 +1,472 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfrtn_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfrtn_1.sp ('sky130_fd_sc_hs__sdfrtn_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.spice ('sky130_fd_sc_hs__sdfrtn_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:29 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfrtn_1     sky130_fd_sc_hs__sdfrtn_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfrtn_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              30        30
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    12        12         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     4         4         SMP2 (4 pins)
+                     1         1         SPMN((2+2)*1) (7 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SMN3
+                        4          4            0            0    SMP2
+                        1          1            0            0    SPMN((2+2)*1)
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD RESET_B CLK_N VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pex.spice b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pex.spice
index 5dde280..4012d8f 100644
--- a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pex.spice
+++ b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtn_1.pex.spice
-* Created: Thu Aug 27 21:08:35 2020
+* Created: Tue Sep  1 20:22:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pxi.spice b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pxi.spice
index 1c659cc..b64deb0 100644
--- a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pxi.spice
+++ b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtn_1.pxi.spice
-* Created: Thu Aug 27 21:08:35 2020
+* Created: Tue Sep  1 20:22:32 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFRTN_1%SCE N_SCE_M1037_g N_SCE_c_277_n N_SCE_c_286_n
 + N_SCE_M1016_g N_SCE_M1017_g N_SCE_M1003_g N_SCE_c_279_n N_SCE_c_280_n

diff --git a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.spice b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.spice
index 1b1f9c9..a5b4204 100644
--- a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.spice
+++ b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtn_1.spice
-* Created: Thu Aug 27 21:08:35 2020
+* Created: Tue Sep  1 20:22:32 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.lvs.report b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.lvs.report
new file mode 100644
index 0000000..a481346
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.lvs.report

@@ -0,0 +1,472 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfrtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfrtp_1.sp ('sky130_fd_sc_hs__sdfrtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.spice ('sky130_fd_sc_hs__sdfrtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:35 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfrtp_1     sky130_fd_sc_hs__sdfrtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfrtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              30        30
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    12        12         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     4         4         SMP2 (4 pins)
+                     1         1         SPMN((2+2)*1) (7 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SMN3
+                        4          4            0            0    SMP2
+                        1          1            0            0    SPMN((2+2)*1)
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pex.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pex.spice
index 6a7102c..8f1ce35 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_1.pex.spice
-* Created: Thu Aug 27 21:08:43 2020
+* Created: Tue Sep  1 20:22:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pxi.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pxi.spice
index 4f55dea..bd929cf 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_1.pxi.spice
-* Created: Thu Aug 27 21:08:43 2020
+* Created: Tue Sep  1 20:22:38 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFRTP_1%SCE N_SCE_c_298_n N_SCE_M1037_g N_SCE_c_299_n
 + N_SCE_M1023_g N_SCE_c_300_n N_SCE_c_301_n N_SCE_M1020_g N_SCE_M1030_g

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.spice
index c85895d..b53edaf 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_1.spice
-* Created: Thu Aug 27 21:08:43 2020
+* Created: Tue Sep  1 20:22:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.lvs.report b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.lvs.report
new file mode 100644
index 0000000..45c6c76
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.lvs.report

@@ -0,0 +1,477 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfrtp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfrtp_2.sp ('sky130_fd_sc_hs__sdfrtp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.spice ('sky130_fd_sc_hs__sdfrtp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:42 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfrtp_2     sky130_fd_sc_hs__sdfrtp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfrtp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              30        30
+
+ Instances:         21        21         MN (4 pins)
+                    21        21         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        43        42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    12        12         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     4         4         SMP2 (4 pins)
+                     1         1         SPMN((2+2)*1) (7 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SMN3
+                        4          4            0            0    SMP2
+                        1          1            0            0    SPMN((2+2)*1)
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pex.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pex.spice
index 2715344..9d911f7 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_2.pex.spice
-* Created: Thu Aug 27 21:08:51 2020
+* Created: Tue Sep  1 20:22:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pxi.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pxi.spice
index b9345a9..3b20b2a 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_2.pxi.spice
-* Created: Thu Aug 27 21:08:51 2020
+* Created: Tue Sep  1 20:22:45 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFRTP_2%A_27_74# N_A_27_74#_M1039_s N_A_27_74#_M1020_s
 + N_A_27_74#_c_280_n N_A_27_74#_c_281_n N_A_27_74#_M1010_g N_A_27_74#_c_287_n

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.spice
index 2276577..ef88b84 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_2.spice
-* Created: Thu Aug 27 21:08:51 2020
+* Created: Tue Sep  1 20:22:45 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.lvs.report b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.lvs.report
new file mode 100644
index 0000000..bfb8f8d
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.lvs.report

@@ -0,0 +1,477 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfrtp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfrtp_4.sp ('sky130_fd_sc_hs__sdfrtp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.spice ('sky130_fd_sc_hs__sdfrtp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfrtp_4     sky130_fd_sc_hs__sdfrtp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfrtp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              30        30
+
+ Instances:         23        23         MN (4 pins)
+                    24        24         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        48        47
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          8         8         MN (4 pins)
+                    12        12         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     4         4         SMP2 (4 pins)
+                     1         1         SPMN((2+2)*1) (7 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       12         12            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SMN3
+                        4          4            0            0    SMP2
+                        1          1            0            0    SPMN((2+2)*1)
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pex.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pex.spice
index 0a43844..7bc1e14 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_4.pex.spice
-* Created: Thu Aug 27 21:08:59 2020
+* Created: Tue Sep  1 20:22:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pxi.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pxi.spice
index e11543a..eb65f9b 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_4.pxi.spice
-* Created: Thu Aug 27 21:08:59 2020
+* Created: Tue Sep  1 20:22:51 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFRTP_4%A_27_74# N_A_27_74#_M1037_s N_A_27_74#_M1021_s
 + N_A_27_74#_c_299_n N_A_27_74#_c_300_n N_A_27_74#_M1009_g N_A_27_74#_c_306_n

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.spice b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.spice
index c9a6bb6..5e654cf 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.spice
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfrtp_4.spice
-* Created: Thu Aug 27 21:08:59 2020
+* Created: Tue Sep  1 20:22:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.lvs.report b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.lvs.report
new file mode 100644
index 0000000..0d7b1fe
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.lvs.report

@@ -0,0 +1,470 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfsbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfsbp_1.sp ('sky130_fd_sc_hs__sdfsbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.spice ('sky130_fd_sc_hs__sdfsbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:22:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfsbp_1     sky130_fd_sc_hs__sdfsbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfsbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              32        32
+
+ Instances:         21        21         MN (4 pins)
+                    21        21         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        43        42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              20        20
+
+ Instances:          8         8         MN (4 pins)
+                    11        11         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        1          1            0            0    SMN3
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pex.spice b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pex.spice
index 883583d..7fddd31 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfsbp_1.pex.spice
-* Created: Thu Aug 27 21:09:08 2020
+* Created: Tue Sep  1 20:22:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pxi.spice b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pxi.spice
index 9a441f4..a8e6da1 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfsbp_1.pxi.spice
-* Created: Thu Aug 27 21:09:08 2020
+* Created: Tue Sep  1 20:22:57 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFSBP_1%A_27_74# N_A_27_74#_M1032_s N_A_27_74#_M1019_s
 + N_A_27_74#_M1039_g N_A_27_74#_c_302_n N_A_27_74#_M1015_g N_A_27_74#_c_297_n

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.spice b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.spice
index 77a0f80..c7c8c5e 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfsbp_1.spice
-* Created: Thu Aug 27 21:09:08 2020
+* Created: Tue Sep  1 20:22:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.lvs.report b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.lvs.report
new file mode 100644
index 0000000..92e2e96
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfsbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfsbp_2.sp ('sky130_fd_sc_hs__sdfsbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.spice ('sky130_fd_sc_hs__sdfsbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfsbp_2     sky130_fd_sc_hs__sdfsbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfsbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfsbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              32        32
+
+ Instances:         25        25         MN (4 pins)
+                    25        25         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        51        50
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              20        20
+
+ Instances:          8         8         MN (4 pins)
+                    11        11         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        1          1            0            0    SMN3
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   16 layout mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+   16 source mos transistors were reduced to 8.
+     8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pex.spice b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pex.spice
index 6bc640a..55db60a 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfsbp_2.pex.spice
-* Created: Thu Aug 27 21:09:16 2020
+* Created: Tue Sep  1 20:23:04 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pxi.spice b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pxi.spice
index 9c56884..117d5a8 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfsbp_2.pxi.spice
-* Created: Thu Aug 27 21:09:16 2020
+* Created: Tue Sep  1 20:23:04 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFSBP_2%A_27_74# N_A_27_74#_M1046_s N_A_27_74#_M1043_s
 + N_A_27_74#_M1035_g N_A_27_74#_c_379_n N_A_27_74#_M1044_g N_A_27_74#_c_373_n

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.spice b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.spice
index a6c95c9..78fb150 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.spice
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfsbp_2.spice
-* Created: Thu Aug 27 21:09:16 2020
+* Created: Tue Sep  1 20:23:04 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.lvs.report b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.lvs.report
new file mode 100644
index 0000000..7bc0d2b
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.lvs.report

@@ -0,0 +1,470 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfstp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfstp_1.sp ('sky130_fd_sc_hs__sdfstp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.spice ('sky130_fd_sc_hs__sdfstp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfstp_1     sky130_fd_sc_hs__sdfstp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfstp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              31        31
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        1          1            0            0    SMN3
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pex.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pex.spice
index ef3f877..27b5c75 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_1.pex.spice
-* Created: Thu Aug 27 21:09:27 2020
+* Created: Tue Sep  1 20:23:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pxi.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pxi.spice
index 05cbbec..ec81fdd 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_1.pxi.spice
-* Created: Thu Aug 27 21:09:27 2020
+* Created: Tue Sep  1 20:23:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFSTP_1%SCE N_SCE_c_302_n N_SCE_c_303_n N_SCE_M1025_g
 + N_SCE_M1021_g N_SCE_c_304_n N_SCE_c_305_n N_SCE_c_306_n N_SCE_M1024_g

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.spice
index 1762daa..2a39579 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_1.spice
-* Created: Thu Aug 27 21:09:27 2020
+* Created: Tue Sep  1 20:23:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.lvs.report b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.lvs.report
new file mode 100644
index 0000000..d894664
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfstp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfstp_2.sp ('sky130_fd_sc_hs__sdfstp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.spice ('sky130_fd_sc_hs__sdfstp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:13 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfstp_2     sky130_fd_sc_hs__sdfstp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfstp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfstp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              31        31
+
+ Instances:         23        23         MN (4 pins)
+                    23        23         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        47        46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        1          1            0            0    SMN3
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pex.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pex.spice
index 76442b9..c994650 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_2.pex.spice
-* Created: Thu Aug 27 21:09:35 2020
+* Created: Tue Sep  1 20:23:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pxi.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pxi.spice
index 947fbb9..bfa2561 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_2.pxi.spice
-* Created: Thu Aug 27 21:09:35 2020
+* Created: Tue Sep  1 20:23:17 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFSTP_2%SCE N_SCE_c_327_n N_SCE_M1042_g N_SCE_c_328_n
 + N_SCE_M1023_g N_SCE_c_329_n N_SCE_M1024_g N_SCE_M1039_g N_SCE_c_322_n

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.spice
index 0ee1992..d6ed373 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_2.spice
-* Created: Thu Aug 27 21:09:35 2020
+* Created: Tue Sep  1 20:23:17 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.lvs.report b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.lvs.report
new file mode 100644
index 0000000..8ab8d05
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.lvs.report

@@ -0,0 +1,475 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfstp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfstp_4.sp ('sky130_fd_sc_hs__sdfstp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.spice ('sky130_fd_sc_hs__sdfstp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfstp_4     sky130_fd_sc_hs__sdfstp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfstp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfstp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              31        31
+
+ Instances:         25        25         MN (4 pins)
+                    26        26         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        52        51
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     5         5         SMN2 (4 pins)
+                     1         1         SMN3 (5 pins)
+                     5         5         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        5          5            0            0    SMN2
+                        1          1            0            0    SMN3
+                        5          5            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   18 layout mos transistors were reduced to 7.
+     11 mos transistors were deleted by parallel reduction.
+   18 source mos transistors were reduced to 7.
+     11 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pex.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pex.spice
index 2f294fa..ec72339 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_4.pex.spice
-* Created: Thu Aug 27 21:09:43 2020
+* Created: Tue Sep  1 20:23:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pxi.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pxi.spice
index 5a18bd5..dbdff19 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_4.pxi.spice
-* Created: Thu Aug 27 21:09:43 2020
+* Created: Tue Sep  1 20:23:23 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFSTP_4%SCE N_SCE_M1043_g N_SCE_c_346_n N_SCE_M1046_g
 + N_SCE_c_347_n N_SCE_M1047_g N_SCE_M1015_g N_SCE_c_341_n N_SCE_c_342_n

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.spice b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.spice
index 5d698b8..cc52d7a 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.spice
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfstp_4.spice
-* Created: Thu Aug 27 21:09:43 2020
+* Created: Tue Sep  1 20:23:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.lvs.report b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.lvs.report
new file mode 100644
index 0000000..764fa8c
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfxbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfxbp_1.sp ('sky130_fd_sc_hs__sdfxbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.spice ('sky130_fd_sc_hs__sdfxbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfxbp_1     sky130_fd_sc_hs__sdfxbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfxbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              27        27
+
+ Instances:         18        18         MN (4 pins)
+                    18        18         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        37        36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          10         10            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pex.spice b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pex.spice
index ee41087..9ef3c61 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxbp_1.pex.spice
-* Created: Thu Aug 27 21:09:51 2020
+* Created: Tue Sep  1 20:23:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pxi.spice b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pxi.spice
index ff85633..2491467 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxbp_1.pxi.spice
-* Created: Thu Aug 27 21:09:51 2020
+* Created: Tue Sep  1 20:23:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFXBP_1%A_31_74# N_A_31_74#_M1028_s N_A_31_74#_M1033_s
 + N_A_31_74#_M1010_g N_A_31_74#_c_258_n N_A_31_74#_M1006_g N_A_31_74#_c_254_n

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.spice b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.spice
index 0186a3a..9cfffb8 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxbp_1.spice
-* Created: Thu Aug 27 21:09:51 2020
+* Created: Tue Sep  1 20:23:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.lvs.report b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.lvs.report
new file mode 100644
index 0000000..aec6d2c
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfxbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfxbp_2.sp ('sky130_fd_sc_hs__sdfxbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.spice ('sky130_fd_sc_hs__sdfxbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:33 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfxbp_2     sky130_fd_sc_hs__sdfxbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfxbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              27        27
+
+ Instances:         20        20         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        41        40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              19        19
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        28        28
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               19         19            0            0
+
+   Instances:          10         10            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         28         28            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pex.spice b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pex.spice
index b2b9fd2..943478c 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxbp_2.pex.spice
-* Created: Thu Aug 27 21:09:58 2020
+* Created: Tue Sep  1 20:23:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pxi.spice b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pxi.spice
index 20e6724..d01c4f9 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxbp_2.pxi.spice
-* Created: Thu Aug 27 21:09:58 2020
+* Created: Tue Sep  1 20:23:36 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFXBP_2%A_36_74# N_A_36_74#_M1036_s N_A_36_74#_M1010_s
 + N_A_36_74#_M1016_g N_A_36_74#_c_273_n N_A_36_74#_M1030_g N_A_36_74#_c_269_n

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.spice b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.spice
index bdcbfc5..d806ddf 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.spice
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxbp_2.spice
-* Created: Thu Aug 27 21:09:58 2020
+* Created: Tue Sep  1 20:23:36 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.lvs.report b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.lvs.report
new file mode 100644
index 0000000..5c71d38
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfxtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfxtp_1.sp ('sky130_fd_sc_hs__sdfxtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.spice ('sky130_fd_sc_hs__sdfxtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:39 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfxtp_1     sky130_fd_sc_hs__sdfxtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfxtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              25        25
+
+ Instances:         16        16         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        33        32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pex.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pex.spice
index 3da928b..da236a0 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_1.pex.spice
-* Created: Thu Aug 27 21:10:06 2020
+* Created: Tue Sep  1 20:23:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pxi.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pxi.spice
index 448d60f..d880b3b 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_1.pxi.spice
-* Created: Thu Aug 27 21:10:06 2020
+* Created: Tue Sep  1 20:23:42 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFXTP_1%A_35_74# N_A_35_74#_M1006_s N_A_35_74#_M1019_s
 + N_A_35_74#_M1014_g N_A_35_74#_c_231_n N_A_35_74#_M1009_g N_A_35_74#_c_232_n

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.spice
index bf97424..2e2494a 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_1.spice
-* Created: Thu Aug 27 21:10:06 2020
+* Created: Tue Sep  1 20:23:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.lvs.report b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.lvs.report
new file mode 100644
index 0000000..4b264fb
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfxtp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfxtp_2.sp ('sky130_fd_sc_hs__sdfxtp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.spice ('sky130_fd_sc_hs__sdfxtp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:45 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfxtp_2     sky130_fd_sc_hs__sdfxtp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfxtp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              25        25
+
+ Instances:         17        17         MN (4 pins)
+                    17        17         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pex.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pex.spice
index d03403b..2702995 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_2.pex.spice
-* Created: Thu Aug 27 21:10:15 2020
+* Created: Tue Sep  1 20:23:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pxi.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pxi.spice
index d6b9505..3d5a34b 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_2.pxi.spice
-* Created: Thu Aug 27 21:10:15 2020
+* Created: Tue Sep  1 20:23:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFXTP_2%A_27_74# N_A_27_74#_M1033_s N_A_27_74#_M1016_s
 + N_A_27_74#_M1019_g N_A_27_74#_c_234_n N_A_27_74#_M1008_g N_A_27_74#_c_230_n

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.spice
index c492371..41b5bb6 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_2.spice
-* Created: Thu Aug 27 21:10:15 2020
+* Created: Tue Sep  1 20:23:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.lvs.report b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.lvs.report
new file mode 100644
index 0000000..bc914c1
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdfxtp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdfxtp_4.sp ('sky130_fd_sc_hs__sdfxtp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.spice ('sky130_fd_sc_hs__sdfxtp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:52 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdfxtp_4     sky130_fd_sc_hs__sdfxtp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdfxtp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              25        25
+
+ Instances:         19        19         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        40        39
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              17        17
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     4         4         SMN2 (4 pins)
+                     4         4         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        24        24
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               17         17            0            0
+
+   Instances:           8          8            0            0    MN(NLOWVT)
+                        8          8            0            0    MP(PSHORT)
+                        4          4            0            0    SMN2
+                        4          4            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         24         24            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 3.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE D SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pex.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pex.spice
index 2d55df8..44dd50a 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_4.pex.spice
-* Created: Thu Aug 27 21:10:23 2020
+* Created: Tue Sep  1 20:23:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pxi.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pxi.spice
index 4d236ad..b26d33d 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_4.pxi.spice
-* Created: Thu Aug 27 21:10:23 2020
+* Created: Tue Sep  1 20:23:55 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDFXTP_4%A_36_74# N_A_36_74#_M1037_s N_A_36_74#_M1025_s
 + N_A_36_74#_M1023_g N_A_36_74#_c_255_n N_A_36_74#_M1011_g N_A_36_74#_c_249_n

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.spice b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.spice
index f0128cf..d957434 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.spice
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdfxtp_4.spice
-* Created: Thu Aug 27 21:10:23 2020
+* Created: Tue Sep  1 20:23:55 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.lvs.report b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.lvs.report
new file mode 100644
index 0000000..0354fdc
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdlclkp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdlclkp_1.sp ('sky130_fd_sc_hs__sdlclkp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.spice ('sky130_fd_sc_hs__sdlclkp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:23:58 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdlclkp_1    sky130_fd_sc_hs__sdlclkp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdlclkp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pex.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pex.spice
index 4fe3e61..7e30eb3 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_1.pex.spice
-* Created: Thu Aug 27 21:10:34 2020
+* Created: Tue Sep  1 20:24:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pxi.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pxi.spice
index 71de704..109abdf 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_1.pxi.spice
-* Created: Thu Aug 27 21:10:34 2020
+* Created: Tue Sep  1 20:24:01 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDLCLKP_1%SCE N_SCE_c_159_n N_SCE_M1010_g N_SCE_c_164_n
 + N_SCE_M1015_g SCE N_SCE_c_161_n N_SCE_c_162_n

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.spice
index 4164ebf..5b25146 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_1.spice
-* Created: Thu Aug 27 21:10:34 2020
+* Created: Tue Sep  1 20:24:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.lvs.report b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.lvs.report
new file mode 100644
index 0000000..f301b71
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdlclkp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdlclkp_2.sp ('sky130_fd_sc_hs__sdlclkp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.spice ('sky130_fd_sc_hs__sdlclkp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:04 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdlclkp_2    sky130_fd_sc_hs__sdlclkp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdlclkp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdlclkp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pex.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pex.spice
index 3958330..384b7f1 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_2.pex.spice
-* Created: Thu Aug 27 21:10:42 2020
+* Created: Tue Sep  1 20:24:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pxi.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pxi.spice
index 35b2a81..7b8e73e 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_2.pxi.spice
-* Created: Thu Aug 27 21:10:42 2020
+* Created: Tue Sep  1 20:24:07 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDLCLKP_2%SCE N_SCE_c_169_n N_SCE_M1013_g N_SCE_c_174_n
 + N_SCE_M1005_g SCE N_SCE_c_171_n N_SCE_c_172_n

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.spice
index f602675..398d495 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_2.spice
-* Created: Thu Aug 27 21:10:42 2020
+* Created: Tue Sep  1 20:24:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.lvs.report b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.lvs.report
new file mode 100644
index 0000000..3354728
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sdlclkp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sdlclkp_4.sp ('sky130_fd_sc_hs__sdlclkp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.spice ('sky130_fd_sc_hs__sdlclkp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:11 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sdlclkp_4    sky130_fd_sc_hs__sdlclkp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sdlclkp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__sdlclkp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              18        18
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     2         2         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        18        18
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               14         14            0            0
+
+   Instances:           7          7            0            0    MN(NLOWVT)
+                        7          7            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        2          2            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         18         18            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pex.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pex.spice
index 7cf540f..23f76bd 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_4.pex.spice
-* Created: Thu Aug 27 21:10:50 2020
+* Created: Tue Sep  1 20:24:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pxi.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pxi.spice
index 1918048..eaa4b19 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_4.pxi.spice
-* Created: Thu Aug 27 21:10:50 2020
+* Created: Tue Sep  1 20:24:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__SDLCLKP_4%SCE N_SCE_c_177_n N_SCE_M1004_g N_SCE_M1021_g
 + SCE N_SCE_c_179_n PM_SKY130_FD_SC_HS__SDLCLKP_4%SCE

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.spice b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.spice
index e522cc6..684974d 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.spice
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sdlclkp_4.spice
-* Created: Thu Aug 27 21:10:50 2020
+* Created: Tue Sep  1 20:24:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.lvs.report b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.lvs.report
new file mode 100644
index 0000000..e88a450
--- /dev/null
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sedfxbp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sedfxbp_1.sp ('sky130_fd_sc_hs__sedfxbp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.spice ('sky130_fd_sc_hs__sedfxbp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sedfxbp_1    sky130_fd_sc_hs__sedfxbp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sedfxbp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sedfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              33        33
+
+ Instances:         22        22         MN (4 pins)
+                    22        22         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        45        44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              21        21
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     6         6         SMN2 (4 pins)
+                     6         6         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               21         21            0            0
+
+   Instances:          10         10            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        6          6            0            0    SMN2
+                        6          6            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE SCD SCE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pex.spice b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pex.spice
index d5b34ff..d3c0a26 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pex.spice
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxbp_1.pex.spice
-* Created: Thu Aug 27 21:10:58 2020
+* Created: Tue Sep  1 20:24:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pxi.spice b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pxi.spice
index e659ae8..73f26e6 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pxi.spice
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxbp_1.pxi.spice
-* Created: Thu Aug 27 21:10:58 2020
+* Created: Tue Sep  1 20:24:20 2020
 * 
 x_PM_SKY130_FD_SC_HS__SEDFXBP_1%D N_D_c_337_n N_D_c_342_n N_D_c_343_n
 + N_D_M1021_g N_D_M1022_g N_D_c_339_n D D N_D_c_340_n N_D_c_341_n

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.spice b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.spice
index 0c61205..66807d2 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.spice
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxbp_1.spice
-* Created: Thu Aug 27 21:10:58 2020
+* Created: Tue Sep  1 20:24:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.lvs.report b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.lvs.report
new file mode 100644
index 0000000..551778c
--- /dev/null
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sedfxbp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sedfxbp_2.sp ('sky130_fd_sc_hs__sedfxbp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.spice ('sky130_fd_sc_hs__sedfxbp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:23 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sedfxbp_2    sky130_fd_sc_hs__sedfxbp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sedfxbp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sedfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              33        33
+
+ Instances:         24        24         MN (4 pins)
+                    24        24         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        49        48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             11        11
+
+ Nets:              21        21
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     6         6         SMN2 (4 pins)
+                     6         6         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        32        32
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              11         11            0            0
+
+   Nets:               21         21            0            0
+
+   Instances:          10         10            0            0    MN(NLOWVT)
+                       10         10            0            0    MP(PSHORT)
+                        6          6            0            0    SMN2
+                        6          6            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         32         32            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 4.
+     4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE SCD SCE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pex.spice b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pex.spice
index 964bf00..8ab6f35 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pex.spice
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxbp_2.pex.spice
-* Created: Thu Aug 27 21:11:05 2020
+* Created: Tue Sep  1 20:24:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pxi.spice b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pxi.spice
index 5b37449..3086282 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pxi.spice
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxbp_2.pxi.spice
-* Created: Thu Aug 27 21:11:05 2020
+* Created: Tue Sep  1 20:24:26 2020
 * 
 x_PM_SKY130_FD_SC_HS__SEDFXBP_2%D N_D_c_350_n N_D_c_351_n N_D_M1003_g
 + N_D_M1002_g D D N_D_c_347_n N_D_c_348_n N_D_c_349_n N_D_c_354_n

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.spice b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.spice
index f1f3c19..f3812a3 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.spice
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxbp_2.spice
-* Created: Thu Aug 27 21:11:05 2020
+* Created: Tue Sep  1 20:24:26 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.lvs.report b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.lvs.report
new file mode 100644
index 0000000..1f0dddf
--- /dev/null
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sedfxtp_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sedfxtp_1.sp ('sky130_fd_sc_hs__sedfxtp_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.spice ('sky130_fd_sc_hs__sedfxtp_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:30 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sedfxtp_1    sky130_fd_sc_hs__sedfxtp_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sedfxtp_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__sedfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              32        32
+
+ Instances:         21        21         MN (4 pins)
+                    21        21         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        43        42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              20        20
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     6         6         SMN2 (4 pins)
+                     6         6         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           9          9            0            0    MN(NLOWVT)
+                        9          9            0            0    MP(PSHORT)
+                        6          6            0            0    SMN2
+                        6          6            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE SCD SCE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pex.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pex.spice
index 9b3b39e..afa2c51 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pex.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_1.pex.spice
-* Created: Thu Aug 27 21:11:13 2020
+* Created: Tue Sep  1 20:24:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pxi.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pxi.spice
index 25149a0..af231ee 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pxi.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_1.pxi.spice
-* Created: Thu Aug 27 21:11:13 2020
+* Created: Tue Sep  1 20:24:33 2020
 * 
 x_PM_SKY130_FD_SC_HS__SEDFXTP_1%D N_D_c_329_n N_D_c_334_n N_D_c_335_n
 + N_D_M1037_g N_D_M1017_g N_D_c_331_n D D N_D_c_332_n N_D_c_333_n

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.spice
index 0354e3a..cd11aab 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_1.spice
-* Created: Thu Aug 27 21:11:13 2020
+* Created: Tue Sep  1 20:24:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.lvs.report b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.lvs.report
new file mode 100644
index 0000000..e49efde
--- /dev/null
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sedfxtp_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sedfxtp_2.sp ('sky130_fd_sc_hs__sedfxtp_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.spice ('sky130_fd_sc_hs__sedfxtp_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:36 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sedfxtp_2    sky130_fd_sc_hs__sedfxtp_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sedfxtp_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__sedfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              32        32
+
+ Instances:         22        22         MN (4 pins)
+                    22        22         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        45        44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              20        20
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     6         6         SMN2 (4 pins)
+                     6         6         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           9          9            0            0    MN(NLOWVT)
+                        9          9            0            0    MP(PSHORT)
+                        6          6            0            0    SMN2
+                        6          6            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE SCD SCE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pex.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pex.spice
index 6a5ba18..2e34269 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pex.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_2.pex.spice
-* Created: Thu Aug 27 21:11:22 2020
+* Created: Tue Sep  1 20:24:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pxi.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pxi.spice
index 2f5532b..44d0e44 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pxi.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_2.pxi.spice
-* Created: Thu Aug 27 21:11:22 2020
+* Created: Tue Sep  1 20:24:39 2020
 * 
 x_PM_SKY130_FD_SC_HS__SEDFXTP_2%D N_D_c_339_n N_D_c_340_n N_D_M1027_g
 + N_D_M1006_g D D N_D_c_336_n N_D_c_337_n N_D_c_338_n N_D_c_343_n

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.spice
index 6b76310..5bff445 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_2.spice
-* Created: Thu Aug 27 21:11:22 2020
+* Created: Tue Sep  1 20:24:39 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.lvs.report b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.lvs.report
new file mode 100644
index 0000000..cc7aad7
--- /dev/null
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__sedfxtp_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__sedfxtp_4.sp ('sky130_fd_sc_hs__sedfxtp_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.spice ('sky130_fd_sc_hs__sedfxtp_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__sedfxtp_4    sky130_fd_sc_hs__sedfxtp_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__sedfxtp_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__sedfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              32        32
+
+ Instances:         24        24         MN (4 pins)
+                    24        24         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        49        48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              20        20
+
+ Instances:          9         9         MN (4 pins)
+                     9         9         MP (4 pins)
+                     6         6         SMN2 (4 pins)
+                     6         6         SMP2 (4 pins)
+                ------    ------
+ Total Inst:        30        30
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               20         20            0            0
+
+   Instances:           9          9            0            0    MN(NLOWVT)
+                        9          9            0            0    MP(PSHORT)
+                        6          6            0            0    SMN2
+                        6          6            0            0    SMP2
+                  -------    -------    ---------    ---------
+   Total Inst:         30         30            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D DE SCD SCE CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pex.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pex.spice
index cbde523..8d5b2ab 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pex.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_4.pex.spice
-* Created: Thu Aug 27 21:11:30 2020
+* Created: Tue Sep  1 20:24:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pxi.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pxi.spice
index 69af49d..8a80d46 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pxi.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_4.pxi.spice
-* Created: Thu Aug 27 21:11:30 2020
+* Created: Tue Sep  1 20:24:46 2020
 * 
 x_PM_SKY130_FD_SC_HS__SEDFXTP_4%D N_D_c_351_n N_D_c_352_n N_D_M1018_g
 + N_D_M1002_g D D N_D_c_348_n N_D_c_349_n N_D_c_350_n N_D_c_355_n

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.spice b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.spice
index 7b5b87a..1c54877 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.spice
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__sedfxtp_4.spice
-* Created: Thu Aug 27 21:11:30 2020
+* Created: Tue Sep  1 20:24:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/tap/sky130_fd_sc_hs__tap_1.lvs.report b/cells/tap/sky130_fd_sc_hs__tap_1.lvs.report
new file mode 100644
index 0000000..843e3b7
--- /dev/null
+++ b/cells/tap/sky130_fd_sc_hs__tap_1.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__tap_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__tap_1.sp ('sky130_fd_sc_hs__tap_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/tap/sky130_fd_sc_hs__tap_1.spice ('sky130_fd_sc_hs__tap_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:49 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/tap/sky130_fd_sc_hs__tap_2.lvs.report b/cells/tap/sky130_fd_sc_hs__tap_2.lvs.report
new file mode 100644
index 0000000..7251840
--- /dev/null
+++ b/cells/tap/sky130_fd_sc_hs__tap_2.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__tap_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__tap_2.sp ('sky130_fd_sc_hs__tap_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/tap/sky130_fd_sc_hs__tap_2.spice ('sky130_fd_sc_hs__tap_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:52 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.lvs.report b/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.lvs.report
new file mode 100644
index 0000000..d092d3a
--- /dev/null
+++ b/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__tapmet1_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__tapmet1_2.sp ('sky130_fd_sc_hs__tapmet1_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.spice ('sky130_fd_sc_hs__tapmet1_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.lvs.report b/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.lvs.report
new file mode 100644
index 0000000..6f0db43
--- /dev/null
+++ b/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__tapvgnd_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__tapvgnd_1.sp ('sky130_fd_sc_hs__tapvgnd_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.spice ('sky130_fd_sc_hs__tapvgnd_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:24:58 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.lvs.report b/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.lvs.report
new file mode 100644
index 0000000..2e53e16
--- /dev/null
+++ b/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__tapvgnd2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__tapvgnd2_1.sp ('sky130_fd_sc_hs__tapvgnd2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.spice ('sky130_fd_sc_hs__tapvgnd2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:01 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.lvs.report b/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.lvs.report
new file mode 100644
index 0000000..bb0c0b2
--- /dev/null
+++ b/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.lvs.report

@@ -0,0 +1,375 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__tapvpwrvgnd_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__tapvpwrvgnd_1.sp ('sky130_fd_sc_hs__tapvpwrvgnd_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.spice ('sky130_fd_sc_hs__tapvpwrvgnd_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                 #   #         ########################  
+                  # #          #                      #  
+                   #           #     NOT COMPARED     #  
+                  # #          #                      #  
+                 #   #         ########################  
+
+
+  Error:    Nothing in source.
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.lvs.report b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.lvs.report
new file mode 100644
index 0000000..5fb870d
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xnor2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xnor2_1.sp ('sky130_fd_sc_hs__xnor2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xnor2/sky130_fd_sc_hs__xnor2_1.spice ('sky130_fd_sc_hs__xnor2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:06 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xnor2_1      sky130_fd_sc_hs__xnor2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xnor2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__xnor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pex.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pex.spice
index d6f388c..ef4591e 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_1.pex.spice
-* Created: Thu Aug 27 21:12:02 2020
+* Created: Tue Sep  1 20:25:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pxi.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pxi.spice
index 89c1d8a..5615121 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_1.pxi.spice
-* Created: Thu Aug 27 21:12:02 2020
+* Created: Tue Sep  1 20:25:10 2020
 * 
 x_PM_SKY130_FD_SC_HS__XNOR2_1%B N_B_c_60_n N_B_M1005_g N_B_c_61_n N_B_M1004_g
 + N_B_c_62_n N_B_M1003_g N_B_M1009_g N_B_c_68_n N_B_c_80_p N_B_c_116_p

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.spice
index e9e4b6f..6121613 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_1.spice
-* Created: Thu Aug 27 21:12:02 2020
+* Created: Tue Sep  1 20:25:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.lvs.report b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.lvs.report
new file mode 100644
index 0000000..099d14a
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xnor2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xnor2_2.sp ('sky130_fd_sc_hs__xnor2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xnor2/sky130_fd_sc_hs__xnor2_2.spice ('sky130_fd_sc_hs__xnor2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:13 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xnor2_2      sky130_fd_sc_hs__xnor2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xnor2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__xnor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:          8         8         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        17        16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pex.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pex.spice
index b660932..86e1dac 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_2.pex.spice
-* Created: Thu Aug 27 21:12:10 2020
+* Created: Tue Sep  1 20:25:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pxi.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pxi.spice
index bf858c5..fb1105f 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_2.pxi.spice
-* Created: Thu Aug 27 21:12:10 2020
+* Created: Tue Sep  1 20:25:16 2020
 * 
 x_PM_SKY130_FD_SC_HS__XNOR2_2%A N_A_c_91_n N_A_M1015_g N_A_c_92_n N_A_M1011_g
 + N_A_c_93_n N_A_M1008_g N_A_c_94_n N_A_M1004_g N_A_c_95_n N_A_M1009_g

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.spice
index 66262c4..ae4c640 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_2.spice
-* Created: Thu Aug 27 21:12:10 2020
+* Created: Tue Sep  1 20:25:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.lvs.report b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.lvs.report
new file mode 100644
index 0000000..8dfae25
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xnor2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xnor2_4.sp ('sky130_fd_sc_hs__xnor2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xnor2/sky130_fd_sc_hs__xnor2_4.spice ('sky130_fd_sc_hs__xnor2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:19 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xnor2_4      sky130_fd_sc_hs__xnor2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xnor2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__xnor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:         16        16         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMN_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMN_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   30 layout mos transistors were reduced to 10.
+     20 mos transistors were deleted by parallel reduction.
+   30 source mos transistors were reduced to 10.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pex.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pex.spice
index a471b8e..5847ee7 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_4.pex.spice
-* Created: Thu Aug 27 21:12:17 2020
+* Created: Tue Sep  1 20:25:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pxi.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pxi.spice
index a6c44a7..9b21129 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_4.pxi.spice
-* Created: Thu Aug 27 21:12:17 2020
+* Created: Tue Sep  1 20:25:23 2020
 * 
 x_PM_SKY130_FD_SC_HS__XNOR2_4%A N_A_M1013_g N_A_c_157_n N_A_M1018_g N_A_c_158_n
 + N_A_M1020_g N_A_M1028_g N_A_M1001_g N_A_c_159_n N_A_M1004_g N_A_M1002_g

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.spice b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.spice
index 0a8d141..b8246cb 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.spice
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor2_4.spice
-* Created: Thu Aug 27 21:12:17 2020
+* Created: Tue Sep  1 20:25:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.lvs.report b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.lvs.report
new file mode 100644
index 0000000..adbfc1d
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xnor3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xnor3_1.sp ('sky130_fd_sc_hs__xnor3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xnor3/sky130_fd_sc_hs__xnor3_1.spice ('sky130_fd_sc_hs__xnor3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xnor3_1      sky130_fd_sc_hs__xnor3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xnor3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__xnor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                ------    ------
+ Total Inst:        22        22
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:          11         11            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         22         22            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB C B A X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pex.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pex.spice
index b1367a4..beb712a 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_1.pex.spice
-* Created: Thu Aug 27 21:12:26 2020
+* Created: Tue Sep  1 20:25:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pxi.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pxi.spice
index 2f0e742..84aa435 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_1.pxi.spice
-* Created: Thu Aug 27 21:12:26 2020
+* Created: Tue Sep  1 20:25:29 2020
 * 
 x_PM_SKY130_FD_SC_HS__XNOR3_1%A_81_268# N_A_81_268#_M1011_d N_A_81_268#_M1014_d
 + N_A_81_268#_c_168_n N_A_81_268#_M1002_g N_A_81_268#_c_169_n

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.spice
index e1282e6..365a642 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_1.spice
-* Created: Thu Aug 27 21:12:26 2020
+* Created: Tue Sep  1 20:25:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.lvs.report b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.lvs.report
new file mode 100644
index 0000000..edd2a73
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xnor3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xnor3_2.sp ('sky130_fd_sc_hs__xnor3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xnor3/sky130_fd_sc_hs__xnor3_2.spice ('sky130_fd_sc_hs__xnor3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xnor3_2      sky130_fd_sc_hs__xnor3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xnor3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__xnor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                ------    ------
+ Total Inst:        22        22
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:          11         11            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         22         22            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pex.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pex.spice
index 5aa2f2c..f27e830 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_2.pex.spice
-* Created: Thu Aug 27 21:12:34 2020
+* Created: Tue Sep  1 20:25:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pxi.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pxi.spice
index 5fcb381..f8536ba 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_2.pxi.spice
-* Created: Thu Aug 27 21:12:34 2020
+* Created: Tue Sep  1 20:25:35 2020
 * 
 x_PM_SKY130_FD_SC_HS__XNOR3_2%A_83_247# N_A_83_247#_M1008_d N_A_83_247#_M1001_d
 + N_A_83_247#_M1004_d N_A_83_247#_M1006_d N_A_83_247#_c_175_n

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.spice
index a78385e..0464fab 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_2.spice
-* Created: Thu Aug 27 21:12:34 2020
+* Created: Tue Sep  1 20:25:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.lvs.report b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.lvs.report
new file mode 100644
index 0000000..35c0b85
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xnor3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xnor3_4.sp ('sky130_fd_sc_hs__xnor3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xnor3/sky130_fd_sc_hs__xnor3_4.spice ('sky130_fd_sc_hs__xnor3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:39 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xnor3_4      sky130_fd_sc_hs__xnor3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xnor3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__xnor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                ------    ------
+ Total Inst:        22        22
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:          11         11            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         22         22            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pex.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pex.spice
index b4213d8..f857207 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_4.pex.spice
-* Created: Thu Aug 27 21:12:42 2020
+* Created: Tue Sep  1 20:25:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pxi.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pxi.spice
index 5b1d12e..cc3bd45 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_4.pxi.spice
-* Created: Thu Aug 27 21:12:42 2020
+* Created: Tue Sep  1 20:25:42 2020
 * 
 x_PM_SKY130_FD_SC_HS__XNOR3_4%A_75_227# N_A_75_227#_M1002_d N_A_75_227#_M1011_d
 + N_A_75_227#_M1023_d N_A_75_227#_M1009_d N_A_75_227#_c_190_n

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.spice b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.spice
index bec9bfb..e66ce7f 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.spice
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xnor3_4.spice
-* Created: Thu Aug 27 21:12:42 2020
+* Created: Tue Sep  1 20:25:42 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_1.lvs.report b/cells/xor2/sky130_fd_sc_hs__xor2_1.lvs.report
new file mode 100644
index 0000000..5d03606
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_1.lvs.report

@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xor2_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xor2_1.sp ('sky130_fd_sc_hs__xor2_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xor2/sky130_fd_sc_hs__xor2_1.spice ('sky130_fd_sc_hs__xor2_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:45 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xor2_1       sky130_fd_sc_hs__xor2_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xor2_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__xor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_1.pex.spice b/cells/xor2/sky130_fd_sc_hs__xor2_1.pex.spice
index dcd30dd..ee4c369 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_1.pex.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_1.pex.spice
-* Created: Thu Aug 27 21:12:50 2020
+* Created: Tue Sep  1 20:25:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_1.pxi.spice b/cells/xor2/sky130_fd_sc_hs__xor2_1.pxi.spice
index 6122e60..8ea8e23 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_1.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_1.pxi.spice
-* Created: Thu Aug 27 21:12:50 2020
+* Created: Tue Sep  1 20:25:48 2020
 * 
 x_PM_SKY130_FD_SC_HS__XOR2_1%B N_B_c_68_n N_B_M1005_g N_B_M1001_g N_B_M1003_g
 + N_B_c_64_n N_B_M1007_g N_B_c_65_n B N_B_c_66_n N_B_c_67_n

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_1.spice b/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
index ec08599..7f980bd 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_1.spice
-* Created: Thu Aug 27 21:12:50 2020
+* Created: Tue Sep  1 20:25:48 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_2.lvs.report b/cells/xor2/sky130_fd_sc_hs__xor2_2.lvs.report
new file mode 100644
index 0000000..7ac34df
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_2.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xor2_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xor2_2.sp ('sky130_fd_sc_hs__xor2_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xor2/sky130_fd_sc_hs__xor2_2.spice ('sky130_fd_sc_hs__xor2_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:51 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xor2_2       sky130_fd_sc_hs__xor2_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xor2_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__xor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        16        15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_2.pex.spice b/cells/xor2/sky130_fd_sc_hs__xor2_2.pex.spice
index d2fb79d..e160364 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_2.pex.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_2.pex.spice
-* Created: Thu Aug 27 21:12:58 2020
+* Created: Tue Sep  1 20:25:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_2.pxi.spice b/cells/xor2/sky130_fd_sc_hs__xor2_2.pxi.spice
index 0130fc2..3341c83 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_2.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_2.pxi.spice
-* Created: Thu Aug 27 21:12:58 2020
+* Created: Tue Sep  1 20:25:54 2020
 * 
 x_PM_SKY130_FD_SC_HS__XOR2_2%A N_A_c_80_n N_A_c_90_n N_A_M1003_g N_A_M1004_g
 + N_A_M1002_g N_A_c_91_n N_A_M1006_g N_A_M1009_g N_A_c_92_n N_A_M1007_g

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_2.spice b/cells/xor2/sky130_fd_sc_hs__xor2_2.spice
index 536f2f6..714dd34 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_2.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_2.spice
-* Created: Thu Aug 27 21:12:58 2020
+* Created: Tue Sep  1 20:25:54 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_4.lvs.report b/cells/xor2/sky130_fd_sc_hs__xor2_4.lvs.report
new file mode 100644
index 0000000..bafc6b0
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_4.lvs.report

@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xor2_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xor2_4.sp ('sky130_fd_sc_hs__xor2_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xor2/sky130_fd_sc_hs__xor2_4.spice ('sky130_fd_sc_hs__xor2_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:25:58 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xor2_4       sky130_fd_sc_hs__xor2_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xor2_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__xor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:              11        11
+
+ Instances:         14        14         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        31        30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              7         7
+
+ Nets:               8         8
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SMP2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               7          7            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SMP2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   30 layout mos transistors were reduced to 10.
+     20 mos transistors were deleted by parallel reduction.
+   30 source mos transistors were reduced to 10.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_4.pex.spice b/cells/xor2/sky130_fd_sc_hs__xor2_4.pex.spice
index 6a8c14f..f4913b2 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_4.pex.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_4.pex.spice
-* Created: Thu Aug 27 21:13:09 2020
+* Created: Tue Sep  1 20:26:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_4.pxi.spice b/cells/xor2/sky130_fd_sc_hs__xor2_4.pxi.spice
index 02e93c8..b79cc2f 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_4.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_4.pxi.spice
-* Created: Thu Aug 27 21:13:09 2020
+* Created: Tue Sep  1 20:26:01 2020
 * 
 x_PM_SKY130_FD_SC_HS__XOR2_4%A N_A_c_161_n N_A_M1013_g N_A_M1001_g N_A_c_162_n
 + N_A_M1018_g N_A_M1022_g N_A_c_163_n N_A_M1004_g N_A_M1012_g N_A_c_164_n

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_4.spice b/cells/xor2/sky130_fd_sc_hs__xor2_4.spice
index 57539f7..071a081 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_4.spice
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor2_4.spice
-* Created: Thu Aug 27 21:13:09 2020
+* Created: Tue Sep  1 20:26:01 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_1.lvs.report b/cells/xor3/sky130_fd_sc_hs__xor3_1.lvs.report
new file mode 100644
index 0000000..1c4bcca
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_1.lvs.report

@@ -0,0 +1,464 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xor3_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xor3_1.sp ('sky130_fd_sc_hs__xor3_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xor3/sky130_fd_sc_hs__xor3_1.spice ('sky130_fd_sc_hs__xor3_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:26:04 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xor3_1       sky130_fd_sc_hs__xor3_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xor3_1
+SOURCE CELL NAME:         sky130_fd_sc_hs__xor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                ------    ------
+ Total Inst:        22        22
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:          11         11            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         22         22            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_1.pex.spice b/cells/xor3/sky130_fd_sc_hs__xor3_1.pex.spice
index 51f6b0c..ac813fe 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_1.pex.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_1.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_1.pex.spice
-* Created: Thu Aug 27 21:13:17 2020
+* Created: Tue Sep  1 20:26:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_1.pxi.spice b/cells/xor3/sky130_fd_sc_hs__xor3_1.pxi.spice
index fdf97ae..e7338bb 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_1.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_1.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_1.pxi.spice
-* Created: Thu Aug 27 21:13:17 2020
+* Created: Tue Sep  1 20:26:07 2020
 * 
 x_PM_SKY130_FD_SC_HS__XOR3_1%A_84_108# N_A_84_108#_M1000_d N_A_84_108#_M1020_d
 + N_A_84_108#_M1003_d N_A_84_108#_M1015_d N_A_84_108#_M1019_g

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_1.spice b/cells/xor3/sky130_fd_sc_hs__xor3_1.spice
index cc2194d..0f738a0 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_1.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_1.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_1.spice
-* Created: Thu Aug 27 21:13:17 2020
+* Created: Tue Sep  1 20:26:07 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_2.lvs.report b/cells/xor3/sky130_fd_sc_hs__xor3_2.lvs.report
new file mode 100644
index 0000000..07bad1d
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_2.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xor3_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xor3_2.sp ('sky130_fd_sc_hs__xor3_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xor3/sky130_fd_sc_hs__xor3_2.spice ('sky130_fd_sc_hs__xor3_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:26:10 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xor3_2       sky130_fd_sc_hs__xor3_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xor3_2
+SOURCE CELL NAME:         sky130_fd_sc_hs__xor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                ------    ------
+ Total Inst:        22        22
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:          11         11            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         22         22            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_2.pex.spice b/cells/xor3/sky130_fd_sc_hs__xor3_2.pex.spice
index b50d9f1..2136701 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_2.pex.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_2.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_2.pex.spice
-* Created: Thu Aug 27 21:13:25 2020
+* Created: Tue Sep  1 20:26:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_2.pxi.spice b/cells/xor3/sky130_fd_sc_hs__xor3_2.pxi.spice
index ca3c154..9c662b7 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_2.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_2.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_2.pxi.spice
-* Created: Thu Aug 27 21:13:25 2020
+* Created: Tue Sep  1 20:26:14 2020
 * 
 x_PM_SKY130_FD_SC_HS__XOR3_2%A_83_289# N_A_83_289#_M1000_d N_A_83_289#_M1022_d
 + N_A_83_289#_M1015_d N_A_83_289#_M1007_d N_A_83_289#_M1019_g

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_2.spice b/cells/xor3/sky130_fd_sc_hs__xor3_2.spice
index 1b4f24d..2a48863 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_2.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_2.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_2.spice
-* Created: Thu Aug 27 21:13:25 2020
+* Created: Tue Sep  1 20:26:14 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_4.lvs.report b/cells/xor3/sky130_fd_sc_hs__xor3_4.lvs.report
new file mode 100644
index 0000000..8638620
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_4.lvs.report

@@ -0,0 +1,469 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_hs__xor3_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_hs__xor3_4.sp ('sky130_fd_sc_hs__xor3_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_hs/cells/xor3/sky130_fd_sc_hs__xor3_4.spice ('sky130_fd_sc_hs__xor3_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Tue Sep  1 20:26:17 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_hs__xor3_4       sky130_fd_sc_hs__xor3_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_hs__xor3_4
+SOURCE CELL NAME:         sky130_fd_sc_hs__xor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              15        15
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                ------    ------
+ Total Inst:        22        22
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               15         15            0            0
+
+   Instances:          11         11            0            0    MN(NLOWVT)
+                       11         11            0            0    MP(PSHORT)
+                  -------    -------    ---------    ---------
+   Total Inst:         22         22            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   8 layout mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+   8 source mos transistors were reduced to 2.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_4.pex.spice b/cells/xor3/sky130_fd_sc_hs__xor3_4.pex.spice
index a280c98..cfe5f1e 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_4.pex.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_4.pex.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_4.pex.spice
-* Created: Thu Aug 27 21:13:34 2020
+* Created: Tue Sep  1 20:26:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_4.pxi.spice b/cells/xor3/sky130_fd_sc_hs__xor3_4.pxi.spice
index 60059bd..4e1f1ae 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_4.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_4.pxi.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_4.pxi.spice
-* Created: Thu Aug 27 21:13:34 2020
+* Created: Tue Sep  1 20:26:20 2020
 * 
 x_PM_SKY130_FD_SC_HS__XOR3_4%A_74_294# N_A_74_294#_M1025_d N_A_74_294#_M1027_d
 + N_A_74_294#_M1006_d N_A_74_294#_M1002_d N_A_74_294#_M1012_g

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_4.spice b/cells/xor3/sky130_fd_sc_hs__xor3_4.spice
index eabaa85..95ab2e4 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_4.spice
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_4.spice

@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_hs__xor3_4.spice
-* Created: Thu Aug 27 21:13:34 2020
+* Created: Tue Sep  1 20:26:20 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 *