verilog: Fixing power pins usage in non-powerpin mode. Previously even when `USE_POWER_PIN` was not defined, the drive strength wrappers where still defining the power pins as ports. Fixes https://github.com/google/skywater-pdk/issues/181 Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>

commit: 2a82aa593da417e5b757736ef67ddd5d37a80ace [log] [tgz]
author: Tim 'mithro' Ansell <me@mith.ro> Wed Oct 28 20:05:43 2020 -0700
committer: Tim 'mithro' Ansell <tansell@google.com> Wed Oct 28 20:05:43 2020 -0700
tree: 565caf8648208a0ab399c244cb1fd6fd7425cf48
parent: d672c39737b5ca3963c3b9e64dd9d6bcbf929ec9 [diff]
parent: a145d4373b1449b5bee7521bea09c6e62db088f4 [diff]
diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.v b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.v
index a694793..6e387c8 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_1.v
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a2111o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.v b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.v
index 4bbfe04..6582746 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_2.v
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a2111o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.v b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.v
index d07f361..a159b52 100644
--- a/cells/a2111o/sky130_fd_sc_hs__a2111o_4.v
+++ b/cells/a2111o/sky130_fd_sc_hs__a2111o_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a2111o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.v b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.v
index 71239fb..66603f7 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.v
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a2111oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.v b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.v
index 5bb6d36..01bd237 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.v
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a2111oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.v b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.v
index 0c75a74..bbe6cf3 100644
--- a/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.v
+++ b/cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a2111oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_1.v b/cells/a211o/sky130_fd_sc_hs__a211o_1.v
index d1faa78..814276b 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_1.v
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a211o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_2.v b/cells/a211o/sky130_fd_sc_hs__a211o_2.v
index cf4d68f..e33a6ee 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_2.v
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a211o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a211o/sky130_fd_sc_hs__a211o_4.v b/cells/a211o/sky130_fd_sc_hs__a211o_4.v
index 40a0949..bd28703 100644
--- a/cells/a211o/sky130_fd_sc_hs__a211o_4.v
+++ b/cells/a211o/sky130_fd_sc_hs__a211o_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a211o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.v b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.v
index 174c761..e03d15c 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_1.v
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a211oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.v b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.v
index 5908f91..c0693f9 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_2.v
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a211oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.v b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.v
index 6823a67..0d8547a 100644
--- a/cells/a211oi/sky130_fd_sc_hs__a211oi_4.v
+++ b/cells/a211oi/sky130_fd_sc_hs__a211oi_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a211oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.v b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.v
index a1082ff..21b7aee 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_1.v
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_1.v

@@ -75,17 +75,13 @@
     X   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output X   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.v b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.v
index dbae316..6219de6 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_2.v
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_2.v

@@ -75,17 +75,13 @@
     X   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output X   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.v b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.v
index 6c3cc34..cdcdeb6 100644
--- a/cells/a21bo/sky130_fd_sc_hs__a21bo_4.v
+++ b/cells/a21bo/sky130_fd_sc_hs__a21bo_4.v

@@ -75,17 +75,13 @@
     X   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output X   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.v b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.v
index 1b5740c..2c29577 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_1.v
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_1.v

@@ -75,17 +75,13 @@
     Y   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output Y   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.v b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.v
index f5bb6ac..a0c8eaa 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_2.v
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_2.v

@@ -75,17 +75,13 @@
     Y   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output Y   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.v b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.v
index 142bb41..90557cd 100644
--- a/cells/a21boi/sky130_fd_sc_hs__a21boi_4.v
+++ b/cells/a21boi/sky130_fd_sc_hs__a21boi_4.v

@@ -75,17 +75,13 @@
     Y   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output Y   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_1.v b/cells/a21o/sky130_fd_sc_hs__a21o_1.v
index 9e8cd5a..cb7d8e2 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_1.v
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__a21o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_2.v b/cells/a21o/sky130_fd_sc_hs__a21o_2.v
index bdb0c58..9264a2e 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_2.v
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__a21o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21o/sky130_fd_sc_hs__a21o_4.v b/cells/a21o/sky130_fd_sc_hs__a21o_4.v
index 5856a55..9e37020 100644
--- a/cells/a21o/sky130_fd_sc_hs__a21o_4.v
+++ b/cells/a21o/sky130_fd_sc_hs__a21o_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__a21o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.v b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.v
index 58e9a36..04e7101 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_1.v
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__a21oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.v b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.v
index 925bf97..a512ffe 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_2.v
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__a21oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.v b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.v
index a59c4e7..6606f08 100644
--- a/cells/a21oi/sky130_fd_sc_hs__a21oi_4.v
+++ b/cells/a21oi/sky130_fd_sc_hs__a21oi_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__a21oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_1.v b/cells/a221o/sky130_fd_sc_hs__a221o_1.v
index 57b952d..debd0fd 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_1.v
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a221o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_2.v b/cells/a221o/sky130_fd_sc_hs__a221o_2.v
index 4393ba5..d380c7e 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_2.v
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a221o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a221o/sky130_fd_sc_hs__a221o_4.v b/cells/a221o/sky130_fd_sc_hs__a221o_4.v
index 68036d4..f9c45a3 100644
--- a/cells/a221o/sky130_fd_sc_hs__a221o_4.v
+++ b/cells/a221o/sky130_fd_sc_hs__a221o_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a221o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.v b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.v
index 62ecf25..470477c 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_1.v
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a221oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.v b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.v
index 48ae8cd..ef2d6b5 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_2.v
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a221oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.v b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.v
index bfdc17b..6602cd0 100644
--- a/cells/a221oi/sky130_fd_sc_hs__a221oi_4.v
+++ b/cells/a221oi/sky130_fd_sc_hs__a221oi_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a221oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_1.v b/cells/a222o/sky130_fd_sc_hs__a222o_1.v
index 31d6c90..a041935 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_1.v
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_1.v

@@ -80,26 +80,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__a222o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    C2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  C2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a222o/sky130_fd_sc_hs__a222o_2.v b/cells/a222o/sky130_fd_sc_hs__a222o_2.v
index e7da71a..f229067 100644
--- a/cells/a222o/sky130_fd_sc_hs__a222o_2.v
+++ b/cells/a222o/sky130_fd_sc_hs__a222o_2.v

@@ -80,26 +80,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__a222o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    C2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  C2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.v b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.v
index 73354b3..9d19dc7 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_1.v
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_1.v

@@ -80,26 +80,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__a222oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    C2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  C2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.v b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.v
index 278757b..d685658 100644
--- a/cells/a222oi/sky130_fd_sc_hs__a222oi_2.v
+++ b/cells/a222oi/sky130_fd_sc_hs__a222oi_2.v

@@ -80,26 +80,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__a222oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    C2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  C2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_1.v b/cells/a22o/sky130_fd_sc_hs__a22o_1.v
index 67ed431..253d0d2 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_1.v
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a22o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_2.v b/cells/a22o/sky130_fd_sc_hs__a22o_2.v
index dffc316..a0bde43 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_2.v
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a22o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a22o/sky130_fd_sc_hs__a22o_4.v b/cells/a22o/sky130_fd_sc_hs__a22o_4.v
index 4d7865c..d145bad 100644
--- a/cells/a22o/sky130_fd_sc_hs__a22o_4.v
+++ b/cells/a22o/sky130_fd_sc_hs__a22o_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a22o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.v b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.v
index 0004d25..b47ae55 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_1.v
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a22oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.v b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.v
index da280e7..f4941e2 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_2.v
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a22oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.v b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.v
index 2908bfb..466a7fd 100644
--- a/cells/a22oi/sky130_fd_sc_hs__a22oi_4.v
+++ b/cells/a22oi/sky130_fd_sc_hs__a22oi_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a22oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.v b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.v
index 1cabc9e..30377db 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.v
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_1.v

@@ -79,9 +79,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output X   ;
@@ -89,8 +87,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.v b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.v
index 3f32691..a710fdd 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.v
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.v

@@ -79,9 +79,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output X   ;
@@ -89,8 +87,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.v b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.v
index d3c0354..a56ba0c 100644
--- a/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.v
+++ b/cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_4.v

@@ -79,9 +79,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output X   ;
@@ -89,8 +87,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.v b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.v
index 61fc8f4..806d75f 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.v
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.v

@@ -79,9 +79,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output Y   ;
@@ -89,8 +87,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.v b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.v
index 704b89b..cd828df 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.v
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.v

@@ -79,9 +79,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output Y   ;
@@ -89,8 +87,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.v b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.v
index 23686fc..b3a3daa 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.v
+++ b/cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.v

@@ -79,9 +79,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output Y   ;
@@ -89,8 +87,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_1.v b/cells/a311o/sky130_fd_sc_hs__a311o_1.v
index 88bcfaf..b501bff 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_1.v
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a311o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_2.v b/cells/a311o/sky130_fd_sc_hs__a311o_2.v
index 19fb6e9..bd8af4f 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_2.v
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a311o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a311o/sky130_fd_sc_hs__a311o_4.v b/cells/a311o/sky130_fd_sc_hs__a311o_4.v
index 02b906d..833d9f4 100644
--- a/cells/a311o/sky130_fd_sc_hs__a311o_4.v
+++ b/cells/a311o/sky130_fd_sc_hs__a311o_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a311o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.v b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.v
index 5510362..69f5cc2 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_1.v
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a311oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.v b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.v
index 668a5b2..5deaca8 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_2.v
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a311oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.v b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.v
index bc878aa..e022c0f 100644
--- a/cells/a311oi/sky130_fd_sc_hs__a311oi_4.v
+++ b/cells/a311oi/sky130_fd_sc_hs__a311oi_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a311oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_1.v b/cells/a31o/sky130_fd_sc_hs__a31o_1.v
index 7d25056..5167774 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_1.v
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a31o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_2.v b/cells/a31o/sky130_fd_sc_hs__a31o_2.v
index 78b1ea1..70d9ec9 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_2.v
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a31o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a31o/sky130_fd_sc_hs__a31o_4.v b/cells/a31o/sky130_fd_sc_hs__a31o_4.v
index 3be567a..fde73f6 100644
--- a/cells/a31o/sky130_fd_sc_hs__a31o_4.v
+++ b/cells/a31o/sky130_fd_sc_hs__a31o_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a31o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.v b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.v
index 4d0a561..f8ba1aa 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_1.v
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a31oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.v b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.v
index 80750a4..aece7c0 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_2.v
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a31oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.v b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.v
index 3d11c0b..9f2d5df 100644
--- a/cells/a31oi/sky130_fd_sc_hs__a31oi_4.v
+++ b/cells/a31oi/sky130_fd_sc_hs__a31oi_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__a31oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_1.v b/cells/a32o/sky130_fd_sc_hs__a32o_1.v
index 1da3970..36ae30b 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_1.v
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_1.v

@@ -78,24 +78,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a32o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_2.v b/cells/a32o/sky130_fd_sc_hs__a32o_2.v
index 9242669..5e40501 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_2.v
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_2.v

@@ -78,24 +78,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a32o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a32o/sky130_fd_sc_hs__a32o_4.v b/cells/a32o/sky130_fd_sc_hs__a32o_4.v
index 69d8d82..019bdbf 100644
--- a/cells/a32o/sky130_fd_sc_hs__a32o_4.v
+++ b/cells/a32o/sky130_fd_sc_hs__a32o_4.v

@@ -78,24 +78,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a32o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.v b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.v
index deca76a..726f3bc 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_1.v
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_1.v

@@ -78,24 +78,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a32oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.v b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.v
index ba94218..41dfe5b 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_2.v
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_2.v

@@ -78,24 +78,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a32oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.v b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.v
index 3577f6c..05cd49d 100644
--- a/cells/a32oi/sky130_fd_sc_hs__a32oi_4.v
+++ b/cells/a32oi/sky130_fd_sc_hs__a32oi_4.v

@@ -78,24 +78,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a32oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_1.v b/cells/a41o/sky130_fd_sc_hs__a41o_1.v
index c2db040..46e3843 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_1.v
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a41o_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_2.v b/cells/a41o/sky130_fd_sc_hs__a41o_2.v
index 5c7db69..a383f41 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_2.v
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a41o_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a41o/sky130_fd_sc_hs__a41o_4.v b/cells/a41o/sky130_fd_sc_hs__a41o_4.v
index 77e682d..3ae084f 100644
--- a/cells/a41o/sky130_fd_sc_hs__a41o_4.v
+++ b/cells/a41o/sky130_fd_sc_hs__a41o_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a41o_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.v b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.v
index c4df54e..5cb54c2 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_1.v
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a41oi_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.v b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.v
index 7ad375b..8880c46 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_2.v
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a41oi_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.v b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.v
index 5b32df2..29e176e 100644
--- a/cells/a41oi/sky130_fd_sc_hs__a41oi_4.v
+++ b/cells/a41oi/sky130_fd_sc_hs__a41oi_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__a41oi_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and2/sky130_fd_sc_hs__and2_1.v b/cells/and2/sky130_fd_sc_hs__and2_1.v
index a657813..b32b43a 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_1.v
+++ b/cells/and2/sky130_fd_sc_hs__and2_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__and2_1 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and2/sky130_fd_sc_hs__and2_2.v b/cells/and2/sky130_fd_sc_hs__and2_2.v
index 36d0188..24b974c 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_2.v
+++ b/cells/and2/sky130_fd_sc_hs__and2_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__and2_2 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and2/sky130_fd_sc_hs__and2_4.v b/cells/and2/sky130_fd_sc_hs__and2_4.v
index 00bc67a..061f82c 100644
--- a/cells/and2/sky130_fd_sc_hs__and2_4.v
+++ b/cells/and2/sky130_fd_sc_hs__and2_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__and2_4 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_1.v b/cells/and2b/sky130_fd_sc_hs__and2b_1.v
index 829b754..08bf83b 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_1.v
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__and2b_1 (
-    X   ,
-    A_N ,
-    B   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_2.v b/cells/and2b/sky130_fd_sc_hs__and2b_2.v
index cf375af..98273ec 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_2.v
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__and2b_2 (
-    X   ,
-    A_N ,
-    B   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and2b/sky130_fd_sc_hs__and2b_4.v b/cells/and2b/sky130_fd_sc_hs__and2b_4.v
index ce61dd5..7069990 100644
--- a/cells/and2b/sky130_fd_sc_hs__and2b_4.v
+++ b/cells/and2b/sky130_fd_sc_hs__and2b_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__and2b_4 (
-    X   ,
-    A_N ,
-    B   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and3/sky130_fd_sc_hs__and3_1.v b/cells/and3/sky130_fd_sc_hs__and3_1.v
index 1bc067a..96d12e8 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_1.v
+++ b/cells/and3/sky130_fd_sc_hs__and3_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__and3_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and3/sky130_fd_sc_hs__and3_2.v b/cells/and3/sky130_fd_sc_hs__and3_2.v
index c0c1573..05606aa 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_2.v
+++ b/cells/and3/sky130_fd_sc_hs__and3_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__and3_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and3/sky130_fd_sc_hs__and3_4.v b/cells/and3/sky130_fd_sc_hs__and3_4.v
index e275239..1950409 100644
--- a/cells/and3/sky130_fd_sc_hs__and3_4.v
+++ b/cells/and3/sky130_fd_sc_hs__and3_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__and3_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_1.v b/cells/and3b/sky130_fd_sc_hs__and3b_1.v
index 1ab6f2e..f1c1006 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_1.v
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__and3b_1 (
-    X   ,
-    A_N ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B  ,
+    C
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_2.v b/cells/and3b/sky130_fd_sc_hs__and3b_2.v
index c321303..7dc5541 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_2.v
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__and3b_2 (
-    X   ,
-    A_N ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B  ,
+    C
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and3b/sky130_fd_sc_hs__and3b_4.v b/cells/and3b/sky130_fd_sc_hs__and3b_4.v
index 9f84013..ed3864c 100644
--- a/cells/and3b/sky130_fd_sc_hs__and3b_4.v
+++ b/cells/and3b/sky130_fd_sc_hs__and3b_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__and3b_4 (
-    X   ,
-    A_N ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B  ,
+    C
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4/sky130_fd_sc_hs__and4_1.v b/cells/and4/sky130_fd_sc_hs__and4_1.v
index 91ba17c..960a8db 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_1.v
+++ b/cells/and4/sky130_fd_sc_hs__and4_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C,
+    D
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4/sky130_fd_sc_hs__and4_2.v b/cells/and4/sky130_fd_sc_hs__and4_2.v
index 2b20a01..082e15e 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_2.v
+++ b/cells/and4/sky130_fd_sc_hs__and4_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C,
+    D
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4/sky130_fd_sc_hs__and4_4.v b/cells/and4/sky130_fd_sc_hs__and4_4.v
index c445431..f5d52c4 100644
--- a/cells/and4/sky130_fd_sc_hs__and4_4.v
+++ b/cells/and4/sky130_fd_sc_hs__and4_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C,
+    D
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_1.v b/cells/and4b/sky130_fd_sc_hs__and4b_1.v
index 23fd086..d4fc5f6 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_1.v
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4b_1 (
-    X   ,
-    A_N ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_2.v b/cells/and4b/sky130_fd_sc_hs__and4b_2.v
index 8f4effa..dcae6e1 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_2.v
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4b_2 (
-    X   ,
-    A_N ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4b/sky130_fd_sc_hs__and4b_4.v b/cells/and4b/sky130_fd_sc_hs__and4b_4.v
index 923d9f6..0066744 100644
--- a/cells/and4b/sky130_fd_sc_hs__and4b_4.v
+++ b/cells/and4b/sky130_fd_sc_hs__and4b_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4b_4 (
-    X   ,
-    A_N ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
 );
 
-    output X   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.v b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.v
index 1672753..ff1b2c9 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_1.v
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4bb_1 (
-    X   ,
-    A_N ,
-    B_N ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
 );
 
-    output X   ;
-    input  A_N ;
-    input  B_N ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.v b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.v
index 7a90cf1..53a192b 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_2.v
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4bb_2 (
-    X   ,
-    A_N ,
-    B_N ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
 );
 
-    output X   ;
-    input  A_N ;
-    input  B_N ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.v b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.v
index 7aea4de..d83bba8 100644
--- a/cells/and4bb/sky130_fd_sc_hs__and4bb_4.v
+++ b/cells/and4bb/sky130_fd_sc_hs__and4bb_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__and4bb_4 (
-    X   ,
-    A_N ,
-    B_N ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
 );
 
-    output X   ;
-    input  A_N ;
-    input  B_N ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/buf/sky130_fd_sc_hs__buf_1.v b/cells/buf/sky130_fd_sc_hs__buf_1.v
index 43d8385..263f56b 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_1.v
+++ b/cells/buf/sky130_fd_sc_hs__buf_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__buf_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/buf/sky130_fd_sc_hs__buf_16.v b/cells/buf/sky130_fd_sc_hs__buf_16.v
index 33a1eb7..524b5d4 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_16.v
+++ b/cells/buf/sky130_fd_sc_hs__buf_16.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__buf_16 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/buf/sky130_fd_sc_hs__buf_2.v b/cells/buf/sky130_fd_sc_hs__buf_2.v
index a420e3f..635890f 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_2.v
+++ b/cells/buf/sky130_fd_sc_hs__buf_2.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__buf_2 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/buf/sky130_fd_sc_hs__buf_4.v b/cells/buf/sky130_fd_sc_hs__buf_4.v
index da874e2..66e5ffb 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_4.v
+++ b/cells/buf/sky130_fd_sc_hs__buf_4.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__buf_4 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/buf/sky130_fd_sc_hs__buf_8.v b/cells/buf/sky130_fd_sc_hs__buf_8.v
index 91ed34a..006b6b8 100644
--- a/cells/buf/sky130_fd_sc_hs__buf_8.v
+++ b/cells/buf/sky130_fd_sc_hs__buf_8.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__buf_8 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.v b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.v
index cffa2b9..f3522a2 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.v
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__bufbuf_16 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.v b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.v
index a0f20d3..2289a08 100644
--- a/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.v
+++ b/cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__bufbuf_8 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.v b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.v
index de2dc4f..a3fec10 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_16.v
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_16.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__bufinv_16 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.v b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.v
index b69f4f1..9c8d673 100644
--- a/cells/bufinv/sky130_fd_sc_hs__bufinv_8.v
+++ b/cells/bufinv/sky130_fd_sc_hs__bufinv_8.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__bufinv_8 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.v b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.v
index 4ed4442..9e3ac2e 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.v
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkbuf_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.v b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.v
index e68c9fc..e904167 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.v
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_16.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkbuf_16 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.v b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.v
index e0b878c..2578a23 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.v
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_2.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkbuf_2 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.v b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.v
index d3e5a00..957a63c 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.v
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_4.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkbuf_4 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.v b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.v
index ef95b4b..fc43b60 100644
--- a/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.v
+++ b/cells/clkbuf/sky130_fd_sc_hs__clkbuf_8.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkbuf_8 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.v b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.v
index 9b97b20..1dfa0a6 100644
--- a/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.v
+++ b/cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkdlyinv3sd1_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.v b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.v
index 3b4d9a0..6f2cde1 100644
--- a/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.v
+++ b/cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkdlyinv3sd2_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.v b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.v
index 66057ac..8edf2dd 100644
--- a/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.v
+++ b/cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkdlyinv3sd3_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.v b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.v
index 72058ea..47425f0 100644
--- a/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.v
+++ b/cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkdlyinv5sd1_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.v b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.v
index d9404fd..c81c930 100644
--- a/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.v
+++ b/cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkdlyinv5sd2_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.v b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.v
index 9403245..81fc481 100644
--- a/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.v
+++ b/cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkdlyinv5sd3_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.v b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.v
index c1efe22..37d86e6 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_1.v
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkinv_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.v b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.v
index a800979..2ef994b 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_16.v
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_16.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkinv_16 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.v b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.v
index 36b2468..444b612 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_2.v
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_2.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkinv_2 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.v b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.v
index bfd3acb..5d5809c 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_4.v
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_4.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkinv_4 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.v b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.v
index 6bb46cd..cb733ba 100644
--- a/cells/clkinv/sky130_fd_sc_hs__clkinv_8.v
+++ b/cells/clkinv/sky130_fd_sc_hs__clkinv_8.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__clkinv_8 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/conb/sky130_fd_sc_hs__conb_1.v b/cells/conb/sky130_fd_sc_hs__conb_1.v
index 68b1ce0..656c4fe 100644
--- a/cells/conb/sky130_fd_sc_hs__conb_1.v
+++ b/cells/conb/sky130_fd_sc_hs__conb_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__conb_1 (
-    HI  ,
-    LO  ,
-    VPWR,
-    VGND
+    HI,
+    LO
 );
 
-    output HI  ;
-    output LO  ;
-    input  VPWR;
-    input  VGND;
+    output HI;
+    output LO;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/decap/sky130_fd_sc_hs__decap_4.v b/cells/decap/sky130_fd_sc_hs__decap_4.v
index f21d6dd..f951a2a 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_4.v
+++ b/cells/decap/sky130_fd_sc_hs__decap_4.v

@@ -56,14 +56,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__decap_4 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__decap_4 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/decap/sky130_fd_sc_hs__decap_8.v b/cells/decap/sky130_fd_sc_hs__decap_8.v
index c2b9a40..dcb1101 100644
--- a/cells/decap/sky130_fd_sc_hs__decap_8.v
+++ b/cells/decap/sky130_fd_sc_hs__decap_8.v

@@ -56,14 +56,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__decap_8 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__decap_8 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.v b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.v
index 09dd078..1c18152 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.v
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_1.v

@@ -81,9 +81,7 @@
     D      ,
     CLK_N  ,
     SET_B  ,
-    RESET_B,
-    VPWR   ,
-    VGND
+    RESET_B
 );
 
     output Q      ;
@@ -92,8 +90,6 @@
     input  CLK_N  ;
     input  SET_B  ;
     input  RESET_B;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.v b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.v
index f8b1a84..d5a1bd6 100644
--- a/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.v
+++ b/cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.v

@@ -81,9 +81,7 @@
     D      ,
     CLK_N  ,
     SET_B  ,
-    RESET_B,
-    VPWR   ,
-    VGND
+    RESET_B
 );
 
     output Q      ;
@@ -92,8 +90,6 @@
     input  CLK_N  ;
     input  SET_B  ;
     input  RESET_B;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.v b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.v
index f2537d5..9898fd2 100644
--- a/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.v
+++ b/cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.v

@@ -81,9 +81,7 @@
     D      ,
     CLK    ,
     SET_B  ,
-    RESET_B,
-    VPWR   ,
-    VGND
+    RESET_B
 );
 
     output Q      ;
@@ -92,8 +90,6 @@
     input  CLK    ;
     input  SET_B  ;
     input  RESET_B;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v
index 472a96b..f206598 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v

@@ -76,9 +76,7 @@
     CLK    ,
     D      ,
     Q      ,
-    Q_N    ,
-    VPWR   ,
-    VGND
+    Q_N
 );
 
     input  RESET_B;
@@ -86,8 +84,6 @@
     input  D      ;
     output Q      ;
     output Q_N    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.v b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.v
index 260941e..f62f8a5 100644
--- a/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.v
+++ b/cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.v

@@ -76,9 +76,7 @@
     CLK    ,
     D      ,
     Q      ,
-    Q_N    ,
-    VPWR   ,
-    VGND
+    Q_N
 );
 
     input  RESET_B;
@@ -86,8 +84,6 @@
     input  D      ;
     output Q      ;
     output Q_N    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.v b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.v
index 56e3e6d..5dd95d2 100644
--- a/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.v
+++ b/cells/dfrtn/sky130_fd_sc_hs__dfrtn_1.v

@@ -73,17 +73,13 @@
     RESET_B,
     CLK_N  ,
     D      ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  CLK_N  ;
     input  D      ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.v b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.v
index 6856e97..c7601d0 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.v
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.v

@@ -72,17 +72,13 @@
     RESET_B,
     CLK    ,
     D      ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  CLK    ;
     input  D      ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.v b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.v
index c8c78ac..be06f6f 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.v
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_2.v

@@ -72,17 +72,13 @@
     RESET_B,
     CLK    ,
     D      ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  CLK    ;
     input  D      ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.v b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.v
index 923a213..ba9440b 100644
--- a/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.v
+++ b/cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.v

@@ -72,17 +72,13 @@
     RESET_B,
     CLK    ,
     D      ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  CLK    ;
     input  D      ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.v b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.v
index d4ee7d7..062221c 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.v
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_1.v

@@ -76,9 +76,7 @@
     D    ,
     Q    ,
     Q_N  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -86,8 +84,6 @@
     output Q    ;
     output Q_N  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.v b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.v
index 215f027..682fb7c 100644
--- a/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.v
+++ b/cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.v

@@ -76,9 +76,7 @@
     D    ,
     Q    ,
     Q_N  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -86,8 +84,6 @@
     output Q    ;
     output Q_N  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.v b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.v
index adb15da..ae9511a 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_1.v
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_1.v

@@ -72,17 +72,13 @@
     CLK  ,
     D    ,
     Q    ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
     input  D    ;
     output Q    ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.v b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.v
index ba5fdd9..514ff72 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_2.v
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_2.v

@@ -72,17 +72,13 @@
     CLK  ,
     D    ,
     Q    ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
     input  D    ;
     output Q    ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.v b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.v
index 07ba85b..5bb5224 100644
--- a/cells/dfstp/sky130_fd_sc_hs__dfstp_4.v
+++ b/cells/dfstp/sky130_fd_sc_hs__dfstp_4.v

@@ -72,17 +72,13 @@
     CLK  ,
     D    ,
     Q    ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
     input  D    ;
     output Q    ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.v b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.v
index e05938a..dda3b36 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.v
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__dfxbp_1 (
-    CLK ,
-    D   ,
-    Q   ,
-    Q_N ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    Q_N
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    output Q_N ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    output Q_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.v b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.v
index b377bb0..0b7096b 100644
--- a/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.v
+++ b/cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__dfxbp_2 (
-    CLK ,
-    D   ,
-    Q   ,
-    Q_N ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    Q_N
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    output Q_N ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    output Q_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.v b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.v
index 2485df8..a55b39a 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.v
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__dfxtp_1 (
-    CLK ,
-    D   ,
-    Q   ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.v b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.v
index d9e7645..11c2c4f 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.v
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__dfxtp_2 (
-    CLK ,
-    D   ,
-    Q   ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.v b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.v
index 92b45c5..2342e8a 100644
--- a/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.v
+++ b/cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__dfxtp_4 (
-    CLK ,
-    D   ,
-    Q   ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/diode/sky130_fd_sc_hs__diode_2.v b/cells/diode/sky130_fd_sc_hs__diode_2.v
index 04bde83..fb36dcb 100644
--- a/cells/diode/sky130_fd_sc_hs__diode_2.v
+++ b/cells/diode/sky130_fd_sc_hs__diode_2.v

@@ -66,18 +66,10 @@
 
 `celldefine
 module sky130_fd_sc_hs__diode_2 (
-    DIODE,
-    VPWR ,
-    VGND ,
-    VPB  ,
-    VNB
+    DIODE
 );
 
     input DIODE;
-    input VPWR ;
-    input VGND ;
-    input VPB  ;
-    input VNB  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.v b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.v
index 9fa65c1..7af7341 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.v
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlclkp_1 (
     GCLK,
     GATE,
-    CLK ,
-    VPWR,
-    VGND
+    CLK
 );
 
     output GCLK;
     input  GATE;
     input  CLK ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.v b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.v
index 5a198dd..1f6b264 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.v
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlclkp_2 (
     GCLK,
     GATE,
-    CLK ,
-    VPWR,
-    VGND
+    CLK
 );
 
     output GCLK;
     input  GATE;
     input  CLK ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.v b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.v
index 7b7b64a..25ca380 100644
--- a/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.v
+++ b/cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlclkp_4 (
     GCLK,
     GATE,
-    CLK ,
-    VPWR,
-    VGND
+    CLK
 );
 
     output GCLK;
     input  GATE;
     input  CLK ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.v b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.v
index 18fc3a4..a3eb1f9 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.v
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.v

@@ -77,9 +77,7 @@
     D      ,
     GATE_N ,
     Q      ,
-    Q_N    ,
-    VPWR   ,
-    VGND
+    Q_N
 );
 
     input  RESET_B;
@@ -87,8 +85,6 @@
     input  GATE_N ;
     output Q      ;
     output Q_N    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.v b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.v
index 9d77cb0..6c3be56 100644
--- a/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.v
+++ b/cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.v

@@ -77,9 +77,7 @@
     D      ,
     GATE_N ,
     Q      ,
-    Q_N    ,
-    VPWR   ,
-    VGND
+    Q_N
 );
 
     input  RESET_B;
@@ -87,8 +85,6 @@
     input  GATE_N ;
     output Q      ;
     output Q_N    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.v b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.v
index 1eb6fba..a4a44cf 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.v
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_1.v

@@ -77,9 +77,7 @@
     D      ,
     GATE   ,
     Q      ,
-    Q_N    ,
-    VPWR   ,
-    VGND
+    Q_N
 );
 
     input  RESET_B;
@@ -87,8 +85,6 @@
     input  GATE   ;
     output Q      ;
     output Q_N    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.v b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.v
index 4b2e772..43e1a94 100644
--- a/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.v
+++ b/cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.v

@@ -77,9 +77,7 @@
     D      ,
     GATE   ,
     Q      ,
-    Q_N    ,
-    VPWR   ,
-    VGND
+    Q_N
 );
 
     input  RESET_B;
@@ -87,8 +85,6 @@
     input  GATE   ;
     output Q      ;
     output Q_N    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.v b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.v
index 980fa1d..8cb0e7e 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.v
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.v

@@ -72,17 +72,13 @@
     RESET_B,
     D      ,
     GATE_N ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  D      ;
     input  GATE_N ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.v b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.v
index ca6eba4..eebfbea 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.v
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_2.v

@@ -72,17 +72,13 @@
     RESET_B,
     D      ,
     GATE_N ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  D      ;
     input  GATE_N ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.v b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.v
index fd4a851..30ecc6e 100644
--- a/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.v
+++ b/cells/dlrtn/sky130_fd_sc_hs__dlrtn_4.v

@@ -72,17 +72,13 @@
     RESET_B,
     D      ,
     GATE_N ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  D      ;
     input  GATE_N ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.v b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.v
index 2304267..d6de6a9 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.v
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.v

@@ -73,17 +73,13 @@
     RESET_B,
     D      ,
     GATE   ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  D      ;
     input  GATE   ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.v b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.v
index 4a75f65..bd0ee73 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.v
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.v

@@ -73,17 +73,13 @@
     RESET_B,
     D      ,
     GATE   ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  D      ;
     input  GATE   ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.v b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.v
index 2879bfc..43ae529 100644
--- a/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.v
+++ b/cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.v

@@ -73,17 +73,13 @@
     RESET_B,
     D      ,
     GATE   ,
-    Q      ,
-    VPWR   ,
-    VGND
+    Q
 );
 
     input  RESET_B;
     input  D      ;
     input  GATE   ;
     output Q      ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.v b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.v
index 398ba1a..b1c405b 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.v
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.v

@@ -72,17 +72,13 @@
     Q     ,
     Q_N   ,
     D     ,
-    GATE_N,
-    VPWR  ,
-    VGND
+    GATE_N
 );
 
     output Q     ;
     output Q_N   ;
     input  D     ;
     input  GATE_N;
-    input  VPWR  ;
-    input  VGND  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.v b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.v
index a3089ca..c624c69 100644
--- a/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.v
+++ b/cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.v

@@ -72,17 +72,13 @@
     Q     ,
     Q_N   ,
     D     ,
-    GATE_N,
-    VPWR  ,
-    VGND
+    GATE_N
 );
 
     output Q     ;
     output Q_N   ;
     input  D     ;
     input  GATE_N;
-    input  VPWR  ;
-    input  VGND  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.v b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.v
index 992013c..5828e43 100644
--- a/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.v
+++ b/cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.v

@@ -72,17 +72,13 @@
     Q   ,
     Q_N ,
     D   ,
-    GATE,
-    VPWR,
-    VGND
+    GATE
 );
 
     output Q   ;
     output Q_N ;
     input  D   ;
     input  GATE;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.v b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.v
index 3ed955e..23e0cbb 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.v
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_1.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlxtn_1 (
     Q     ,
     D     ,
-    GATE_N,
-    VPWR  ,
-    VGND
+    GATE_N
 );
 
     output Q     ;
     input  D     ;
     input  GATE_N;
-    input  VPWR  ;
-    input  VGND  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.v b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.v
index d60f093..1c24853 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.v
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlxtn_2 (
     Q     ,
     D     ,
-    GATE_N,
-    VPWR  ,
-    VGND
+    GATE_N
 );
 
     output Q     ;
     input  D     ;
     input  GATE_N;
-    input  VPWR  ;
-    input  VGND  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.v b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.v
index a24a7c6..c3ec4e3 100644
--- a/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.v
+++ b/cells/dlxtn/sky130_fd_sc_hs__dlxtn_4.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlxtn_4 (
     Q     ,
     D     ,
-    GATE_N,
-    VPWR  ,
-    VGND
+    GATE_N
 );
 
     output Q     ;
     input  D     ;
     input  GATE_N;
-    input  VPWR  ;
-    input  VGND  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.v b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.v
index 671dcd8..23222c2 100644
--- a/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.v
+++ b/cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__dlxtp_1 (
     Q   ,
     D   ,
-    GATE,
-    VPWR,
-    VGND
+    GATE
 );
 
     output Q   ;
     input  D   ;
     input  GATE;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.v b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.v
index 523fda2..d4e6a76 100644
--- a/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.v
+++ b/cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__dlygate4sd1_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.v b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.v
index 98e6bfc..8d5b0ac 100644
--- a/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.v
+++ b/cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__dlygate4sd2_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.v b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.v
index c913859..280396a 100644
--- a/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.v
+++ b/cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__dlygate4sd3_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.v b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.v
index 38c4e69..397c157 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.v
+++ b/cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__dlymetal6s2s_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.v b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.v
index f8b4ac9..c0e83bc 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.v
+++ b/cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__dlymetal6s4s_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.v b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.v
index d21d3ba..3af7335 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.v
+++ b/cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.v

@@ -64,16 +64,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__dlymetal6s6s_1 (
-    X   ,
-    A   ,
-    VPWR,
-    VGND
+    X,
+    A
 );
 
-    output X   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.v b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.v
index 5dbb2d0..2b0462d 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_1.v
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_1.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__ebufn_1 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.v b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.v
index 8309284..9d15b86 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_2.v
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_2.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__ebufn_2 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.v b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.v
index f510264..59993a3 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_4.v
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_4.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__ebufn_4 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.v b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.v
index 16104ac..d83ab58 100644
--- a/cells/ebufn/sky130_fd_sc_hs__ebufn_8.v
+++ b/cells/ebufn/sky130_fd_sc_hs__ebufn_8.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__ebufn_8 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.v b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.v
index dba40fb..93dfc09 100644
--- a/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.v
+++ b/cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.v

@@ -73,22 +73,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__edfxbp_1 (
-    Q   ,
-    Q_N ,
-    CLK ,
-    D   ,
-    DE  ,
-    VPWR,
-    VGND
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
 );
 
-    output Q   ;
-    output Q_N ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.v b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.v
index 06ef506..fb7b2dd 100644
--- a/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.v
+++ b/cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.v

@@ -70,20 +70,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__edfxtp_1 (
-    Q   ,
-    CLK ,
-    D   ,
-    DE  ,
-    VPWR,
-    VGND
+    Q  ,
+    CLK,
+    D  ,
+    DE
 );
 
-    output Q   ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_1.v b/cells/einvn/sky130_fd_sc_hs__einvn_1.v
index 2ad6705..a5cb423 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_1.v
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_1.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__einvn_1 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_2.v b/cells/einvn/sky130_fd_sc_hs__einvn_2.v
index 660c2d9..aea497d 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_2.v
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_2.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__einvn_2 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_4.v b/cells/einvn/sky130_fd_sc_hs__einvn_4.v
index 4ba91ae..c5fbea6 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_4.v
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_4.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__einvn_4 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvn/sky130_fd_sc_hs__einvn_8.v b/cells/einvn/sky130_fd_sc_hs__einvn_8.v
index 8940e11..779b5d4 100644
--- a/cells/einvn/sky130_fd_sc_hs__einvn_8.v
+++ b/cells/einvn/sky130_fd_sc_hs__einvn_8.v

@@ -68,16 +68,12 @@
 module sky130_fd_sc_hs__einvn_8 (
     A   ,
     TE_B,
-    Z   ,
-    VPWR,
-    VGND
+    Z
 );
 
     input  A   ;
     input  TE_B;
     output Z   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_1.v b/cells/einvp/sky130_fd_sc_hs__einvp_1.v
index 5e531dc..0a1494b 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_1.v
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__einvp_1 (
-    A   ,
-    TE  ,
-    Z   ,
-    VPWR,
-    VGND
+    A ,
+    TE,
+    Z
 );
 
-    input  A   ;
-    input  TE  ;
-    output Z   ;
-    input  VPWR;
-    input  VGND;
+    input  A ;
+    input  TE;
+    output Z ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_2.v b/cells/einvp/sky130_fd_sc_hs__einvp_2.v
index 6b2fc96..bb4f63e 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_2.v
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__einvp_2 (
-    A   ,
-    TE  ,
-    Z   ,
-    VPWR,
-    VGND
+    A ,
+    TE,
+    Z
 );
 
-    input  A   ;
-    input  TE  ;
-    output Z   ;
-    input  VPWR;
-    input  VGND;
+    input  A ;
+    input  TE;
+    output Z ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_4.v b/cells/einvp/sky130_fd_sc_hs__einvp_4.v
index d88ff38..0917bb7 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_4.v
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__einvp_4 (
-    A   ,
-    TE  ,
-    Z   ,
-    VPWR,
-    VGND
+    A ,
+    TE,
+    Z
 );
 
-    input  A   ;
-    input  TE  ;
-    output Z   ;
-    input  VPWR;
-    input  VGND;
+    input  A ;
+    input  TE;
+    output Z ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/einvp/sky130_fd_sc_hs__einvp_8.v b/cells/einvp/sky130_fd_sc_hs__einvp_8.v
index 74f7d6c..6afbf73 100644
--- a/cells/einvp/sky130_fd_sc_hs__einvp_8.v
+++ b/cells/einvp/sky130_fd_sc_hs__einvp_8.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__einvp_8 (
-    A   ,
-    TE  ,
-    Z   ,
-    VPWR,
-    VGND
+    A ,
+    TE,
+    Z
 );
 
-    input  A   ;
-    input  TE  ;
-    output Z   ;
-    input  VPWR;
-    input  VGND;
+    input  A ;
+    input  TE;
+    output Z ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fa/sky130_fd_sc_hs__fa_1.v b/cells/fa/sky130_fd_sc_hs__fa_1.v
index 8768ddb..e556011 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_1.v
+++ b/cells/fa/sky130_fd_sc_hs__fa_1.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CIN ,
-    VPWR,
-    VGND
+    CIN
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CIN ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fa/sky130_fd_sc_hs__fa_2.v b/cells/fa/sky130_fd_sc_hs__fa_2.v
index eae2b4e..c2e29cc 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_2.v
+++ b/cells/fa/sky130_fd_sc_hs__fa_2.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CIN ,
-    VPWR,
-    VGND
+    CIN
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CIN ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fa/sky130_fd_sc_hs__fa_4.v b/cells/fa/sky130_fd_sc_hs__fa_4.v
index 6d3a4c1..f717fff 100644
--- a/cells/fa/sky130_fd_sc_hs__fa_4.v
+++ b/cells/fa/sky130_fd_sc_hs__fa_4.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CIN ,
-    VPWR,
-    VGND
+    CIN
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CIN ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fah/sky130_fd_sc_hs__fah_1.v b/cells/fah/sky130_fd_sc_hs__fah_1.v
index bb78f57..5b7e8f8 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_1.v
+++ b/cells/fah/sky130_fd_sc_hs__fah_1.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CI  ,
-    VPWR,
-    VGND
+    CI
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CI  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fah/sky130_fd_sc_hs__fah_2.v b/cells/fah/sky130_fd_sc_hs__fah_2.v
index e55b265..d72e35e 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_2.v
+++ b/cells/fah/sky130_fd_sc_hs__fah_2.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CI  ,
-    VPWR,
-    VGND
+    CI
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CI  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fah/sky130_fd_sc_hs__fah_4.v b/cells/fah/sky130_fd_sc_hs__fah_4.v
index 18e17fd..d770e8e 100644
--- a/cells/fah/sky130_fd_sc_hs__fah_4.v
+++ b/cells/fah/sky130_fd_sc_hs__fah_4.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CI  ,
-    VPWR,
-    VGND
+    CI
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CI  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.v b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.v
index e6d2f5e..9df9c25 100644
--- a/cells/fahcin/sky130_fd_sc_hs__fahcin_1.v
+++ b/cells/fahcin/sky130_fd_sc_hs__fahcin_1.v

@@ -76,9 +76,7 @@
     SUM ,
     A   ,
     B   ,
-    CIN ,
-    VPWR,
-    VGND
+    CIN
 );
 
     output COUT;
@@ -86,8 +84,6 @@
     input  A   ;
     input  B   ;
     input  CIN ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.v b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.v
index da6e152..56eb74a 100644
--- a/cells/fahcon/sky130_fd_sc_hs__fahcon_1.v
+++ b/cells/fahcon/sky130_fd_sc_hs__fahcon_1.v

@@ -76,9 +76,7 @@
     SUM   ,
     A     ,
     B     ,
-    CI    ,
-    VPWR  ,
-    VGND
+    CI
 );
 
     output COUT_N;
@@ -86,8 +84,6 @@
     input  A     ;
     input  B     ;
     input  CI    ;
-    input  VPWR  ;
-    input  VGND  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/fill/sky130_fd_sc_hs__fill_1.v b/cells/fill/sky130_fd_sc_hs__fill_1.v
index 9087099..c8147cd 100644
--- a/cells/fill/sky130_fd_sc_hs__fill_1.v
+++ b/cells/fill/sky130_fd_sc_hs__fill_1.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_1 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_1 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/fill/sky130_fd_sc_hs__fill_2.v b/cells/fill/sky130_fd_sc_hs__fill_2.v
index 656c3d6..826ae1c 100644
--- a/cells/fill/sky130_fd_sc_hs__fill_2.v
+++ b/cells/fill/sky130_fd_sc_hs__fill_2.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_2 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_2 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/fill/sky130_fd_sc_hs__fill_4.v b/cells/fill/sky130_fd_sc_hs__fill_4.v
index 3eccbda..427b092 100644
--- a/cells/fill/sky130_fd_sc_hs__fill_4.v
+++ b/cells/fill/sky130_fd_sc_hs__fill_4.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_4 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_4 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/fill/sky130_fd_sc_hs__fill_8.v b/cells/fill/sky130_fd_sc_hs__fill_8.v
index c91507e..11825d5 100644
--- a/cells/fill/sky130_fd_sc_hs__fill_8.v
+++ b/cells/fill/sky130_fd_sc_hs__fill_8.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_8 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_8 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.v b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.v
index 466da33..42a2955 100644
--- a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.v
+++ b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_2.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_diode_2 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_diode_2 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.v b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.v
index 3a28946..462f626 100644
--- a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.v
+++ b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_diode_4 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_diode_4 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.v b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.v
index f83f47b..3458b81 100644
--- a/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.v
+++ b/cells/fill_diode/sky130_fd_sc_hs__fill_diode_8.v

@@ -62,18 +62,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__fill_diode_8 (
-    VPWR,
-    VGND,
-    VPB ,
-    VNB
-);
-
-    input VPWR;
-    input VGND;
-    input VPB ;
-    input VNB ;
-
+module sky130_fd_sc_hs__fill_diode_8 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/ha/sky130_fd_sc_hs__ha_1.v b/cells/ha/sky130_fd_sc_hs__ha_1.v
index 63deba8..ec777b2 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_1.v
+++ b/cells/ha/sky130_fd_sc_hs__ha_1.v

@@ -72,17 +72,13 @@
     COUT,
     SUM ,
     A   ,
-    B   ,
-    VPWR,
-    VGND
+    B
 );
 
     output COUT;
     output SUM ;
     input  A   ;
     input  B   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/ha/sky130_fd_sc_hs__ha_2.v b/cells/ha/sky130_fd_sc_hs__ha_2.v
index 6b45b1e..c6142aa 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_2.v
+++ b/cells/ha/sky130_fd_sc_hs__ha_2.v

@@ -72,17 +72,13 @@
     COUT,
     SUM ,
     A   ,
-    B   ,
-    VPWR,
-    VGND
+    B
 );
 
     output COUT;
     output SUM ;
     input  A   ;
     input  B   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/ha/sky130_fd_sc_hs__ha_4.v b/cells/ha/sky130_fd_sc_hs__ha_4.v
index 919edf9..801fd8f 100644
--- a/cells/ha/sky130_fd_sc_hs__ha_4.v
+++ b/cells/ha/sky130_fd_sc_hs__ha_4.v

@@ -72,17 +72,13 @@
     COUT,
     SUM ,
     A   ,
-    B   ,
-    VPWR,
-    VGND
+    B
 );
 
     output COUT;
     output SUM ;
     input  A   ;
     input  B   ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/inv/sky130_fd_sc_hs__inv_1.v b/cells/inv/sky130_fd_sc_hs__inv_1.v
index 6e94dcf..e9c7a99 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_1.v
+++ b/cells/inv/sky130_fd_sc_hs__inv_1.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__inv_1 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/inv/sky130_fd_sc_hs__inv_16.v b/cells/inv/sky130_fd_sc_hs__inv_16.v
index ca097fd..5c78b63 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_16.v
+++ b/cells/inv/sky130_fd_sc_hs__inv_16.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__inv_16 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/inv/sky130_fd_sc_hs__inv_2.v b/cells/inv/sky130_fd_sc_hs__inv_2.v
index 1970abc..a9d18cd 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_2.v
+++ b/cells/inv/sky130_fd_sc_hs__inv_2.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__inv_2 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/inv/sky130_fd_sc_hs__inv_4.v b/cells/inv/sky130_fd_sc_hs__inv_4.v
index 32da34d..57ebd23 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_4.v
+++ b/cells/inv/sky130_fd_sc_hs__inv_4.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__inv_4 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/inv/sky130_fd_sc_hs__inv_8.v b/cells/inv/sky130_fd_sc_hs__inv_8.v
index 8583339..58f3ed6 100644
--- a/cells/inv/sky130_fd_sc_hs__inv_8.v
+++ b/cells/inv/sky130_fd_sc_hs__inv_8.v

@@ -63,16 +63,12 @@
 
 `celldefine
 module sky130_fd_sc_hs__inv_8 (
-    Y   ,
-    A   ,
-    VPWR,
-    VGND
+    Y,
+    A
 );
 
-    output Y   ;
-    input  A   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_1.v b/cells/maj3/sky130_fd_sc_hs__maj3_1.v
index 5a7379b..c29b154 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_1.v
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__maj3_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_2.v b/cells/maj3/sky130_fd_sc_hs__maj3_2.v
index f00347e..5fa259d 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_2.v
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__maj3_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/maj3/sky130_fd_sc_hs__maj3_4.v b/cells/maj3/sky130_fd_sc_hs__maj3_4.v
index c302fc6..698bfd0 100644
--- a/cells/maj3/sky130_fd_sc_hs__maj3_4.v
+++ b/cells/maj3/sky130_fd_sc_hs__maj3_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__maj3_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_1.v b/cells/mux2/sky130_fd_sc_hs__mux2_1.v
index 187ba42..097576c 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_1.v
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux2_1 (
-    X   ,
-    A0  ,
-    A1  ,
-    S   ,
-    VPWR,
-    VGND
+    X ,
+    A0,
+    A1,
+    S
 );
 
-    output X   ;
-    input  A0  ;
-    input  A1  ;
-    input  S   ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_2.v b/cells/mux2/sky130_fd_sc_hs__mux2_2.v
index 358cebe..12b5fad 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_2.v
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux2_2 (
-    X   ,
-    A0  ,
-    A1  ,
-    S   ,
-    VPWR,
-    VGND
+    X ,
+    A0,
+    A1,
+    S
 );
 
-    output X   ;
-    input  A0  ;
-    input  A1  ;
-    input  S   ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux2/sky130_fd_sc_hs__mux2_4.v b/cells/mux2/sky130_fd_sc_hs__mux2_4.v
index b262bdd..fac5e45 100644
--- a/cells/mux2/sky130_fd_sc_hs__mux2_4.v
+++ b/cells/mux2/sky130_fd_sc_hs__mux2_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux2_4 (
-    X   ,
-    A0  ,
-    A1  ,
-    S   ,
-    VPWR,
-    VGND
+    X ,
+    A0,
+    A1,
+    S
 );
 
-    output X   ;
-    input  A0  ;
-    input  A1  ;
-    input  S   ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.v b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.v
index f60138d..fbcbbdd 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_1.v
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux2i_1 (
-    Y   ,
-    A0  ,
-    A1  ,
-    S   ,
-    VPWR,
-    VGND
+    Y ,
+    A0,
+    A1,
+    S
 );
 
-    output Y   ;
-    input  A0  ;
-    input  A1  ;
-    input  S   ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.v b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.v
index ee37fbf..d7dc71b 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_2.v
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux2i_2 (
-    Y   ,
-    A0  ,
-    A1  ,
-    S   ,
-    VPWR,
-    VGND
+    Y ,
+    A0,
+    A1,
+    S
 );
 
-    output Y   ;
-    input  A0  ;
-    input  A1  ;
-    input  S   ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.v b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.v
index 3cc4a79..35b364a 100644
--- a/cells/mux2i/sky130_fd_sc_hs__mux2i_4.v
+++ b/cells/mux2i/sky130_fd_sc_hs__mux2i_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux2i_4 (
-    Y   ,
-    A0  ,
-    A1  ,
-    S   ,
-    VPWR,
-    VGND
+    Y ,
+    A0,
+    A1,
+    S
 );
 
-    output Y   ;
-    input  A0  ;
-    input  A1  ;
-    input  S   ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_1.v b/cells/mux4/sky130_fd_sc_hs__mux4_1.v
index 31ddb8c..bbc6abf 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_1.v
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_1.v

@@ -78,26 +78,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux4_1 (
-    X   ,
-    A0  ,
-    A1  ,
-    A2  ,
-    A3  ,
-    S0  ,
-    S1  ,
-    VPWR,
-    VGND
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
 );
 
-    output X   ;
-    input  A0  ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  S0  ;
-    input  S1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_2.v b/cells/mux4/sky130_fd_sc_hs__mux4_2.v
index 72da244..2e270ef 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_2.v
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_2.v

@@ -78,26 +78,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux4_2 (
-    X   ,
-    A0  ,
-    A1  ,
-    A2  ,
-    A3  ,
-    S0  ,
-    S1  ,
-    VPWR,
-    VGND
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
 );
 
-    output X   ;
-    input  A0  ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  S0  ;
-    input  S1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/mux4/sky130_fd_sc_hs__mux4_4.v b/cells/mux4/sky130_fd_sc_hs__mux4_4.v
index 039eb7d..3555eb9 100644
--- a/cells/mux4/sky130_fd_sc_hs__mux4_4.v
+++ b/cells/mux4/sky130_fd_sc_hs__mux4_4.v

@@ -78,26 +78,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__mux4_4 (
-    X   ,
-    A0  ,
-    A1  ,
-    A2  ,
-    A3  ,
-    S0  ,
-    S1  ,
-    VPWR,
-    VGND
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
 );
 
-    output X   ;
-    input  A0  ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  S0  ;
-    input  S1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_1.v b/cells/nand2/sky130_fd_sc_hs__nand2_1.v
index 51f50ed..179a4dd 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_1.v
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2_1 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_2.v b/cells/nand2/sky130_fd_sc_hs__nand2_2.v
index 9b3a0d2..431720c 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_2.v
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2_2 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_4.v b/cells/nand2/sky130_fd_sc_hs__nand2_4.v
index 380de40..460b267 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_4.v
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2_4 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2/sky130_fd_sc_hs__nand2_8.v b/cells/nand2/sky130_fd_sc_hs__nand2_8.v
index 4fe07e6..77e6147 100644
--- a/cells/nand2/sky130_fd_sc_hs__nand2_8.v
+++ b/cells/nand2/sky130_fd_sc_hs__nand2_8.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2_8 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.v b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.v
index c7519b1..b31ec37 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_1.v
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2b_1 (
-    Y   ,
-    A_N ,
-    B   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.v b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.v
index 493d5c9..7cf4ae0 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_2.v
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2b_2 (
-    Y   ,
-    A_N ,
-    B   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.v b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.v
index 1d26c0d..a8879e9 100644
--- a/cells/nand2b/sky130_fd_sc_hs__nand2b_4.v
+++ b/cells/nand2b/sky130_fd_sc_hs__nand2b_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand2b_4 (
-    Y   ,
-    A_N ,
-    B   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_1.v b/cells/nand3/sky130_fd_sc_hs__nand3_1.v
index 4bd98f0..f4d748a 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_1.v
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand3_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_2.v b/cells/nand3/sky130_fd_sc_hs__nand3_2.v
index b4194da..4be91fe 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_2.v
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand3_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand3/sky130_fd_sc_hs__nand3_4.v b/cells/nand3/sky130_fd_sc_hs__nand3_4.v
index 4c5ea94..b80476b 100644
--- a/cells/nand3/sky130_fd_sc_hs__nand3_4.v
+++ b/cells/nand3/sky130_fd_sc_hs__nand3_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand3_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.v b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.v
index 910cfa3..c299916 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_1.v
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand3b_1 (
-    Y   ,
-    A_N ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B  ,
+    C
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.v b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.v
index d20fa14..53273e3 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_2.v
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand3b_2 (
-    Y   ,
-    A_N ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B  ,
+    C
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.v b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.v
index a32c0d6..4f8bddd 100644
--- a/cells/nand3b/sky130_fd_sc_hs__nand3b_4.v
+++ b/cells/nand3b/sky130_fd_sc_hs__nand3b_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand3b_4 (
-    Y   ,
-    A_N ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B  ,
+    C
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_1.v b/cells/nand4/sky130_fd_sc_hs__nand4_1.v
index 31d2c84..07f9b0f 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_1.v
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C,
+    D
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_2.v b/cells/nand4/sky130_fd_sc_hs__nand4_2.v
index bf5bff5..89a4c47 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_2.v
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C,
+    D
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4/sky130_fd_sc_hs__nand4_4.v b/cells/nand4/sky130_fd_sc_hs__nand4_4.v
index cefd7df..bf2c9e1 100644
--- a/cells/nand4/sky130_fd_sc_hs__nand4_4.v
+++ b/cells/nand4/sky130_fd_sc_hs__nand4_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C,
+    D
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.v b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.v
index 2f261a1..de71b2b 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_1.v
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4b_1 (
-    Y   ,
-    A_N ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.v b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.v
index a7126d87..4f2ca07 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_2.v
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4b_2 (
-    Y   ,
-    A_N ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.v b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.v
index c3cef8c..ba253c2 100644
--- a/cells/nand4b/sky130_fd_sc_hs__nand4b_4.v
+++ b/cells/nand4b/sky130_fd_sc_hs__nand4b_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4b_4 (
-    Y   ,
-    A_N ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.v b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.v
index 2506b9e..2e4a26d 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.v
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4bb_1 (
-    Y   ,
-    A_N ,
-    B_N ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B_N ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.v b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.v
index 88596df..440bc89 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.v
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4bb_2 (
-    Y   ,
-    A_N ,
-    B_N ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B_N ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.v b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.v
index 3218d8e..19d8734 100644
--- a/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.v
+++ b/cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nand4bb_4 (
-    Y   ,
-    A_N ,
-    B_N ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
 );
 
-    output Y   ;
-    input  A_N ;
-    input  B_N ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_1.v b/cells/nor2/sky130_fd_sc_hs__nor2_1.v
index c13609f..5ec8e74 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_1.v
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2_1 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_2.v b/cells/nor2/sky130_fd_sc_hs__nor2_2.v
index 0d6067a..03acb02 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_2.v
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2_2 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_4.v b/cells/nor2/sky130_fd_sc_hs__nor2_4.v
index 058f12d..4f94d44 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_4.v
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2_4 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2/sky130_fd_sc_hs__nor2_8.v b/cells/nor2/sky130_fd_sc_hs__nor2_8.v
index 4364d20..733d63f 100644
--- a/cells/nor2/sky130_fd_sc_hs__nor2_8.v
+++ b/cells/nor2/sky130_fd_sc_hs__nor2_8.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2_8 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.v b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.v
index f20fcaf..d5fc1d3 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_1.v
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_1.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2b_1 (
-    Y   ,
-    A   ,
-    B_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.v b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.v
index ecc68d3..3e6b754 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_2.v
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_2.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2b_2 (
-    Y   ,
-    A   ,
-    B_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.v b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.v
index fb10c64..acc2f10 100644
--- a/cells/nor2b/sky130_fd_sc_hs__nor2b_4.v
+++ b/cells/nor2b/sky130_fd_sc_hs__nor2b_4.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor2b_4 (
-    Y   ,
-    A   ,
-    B_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_1.v b/cells/nor3/sky130_fd_sc_hs__nor3_1.v
index ca18596..d048234 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_1.v
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor3_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_2.v b/cells/nor3/sky130_fd_sc_hs__nor3_2.v
index 98689c4..278dd36 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_2.v
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor3_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor3/sky130_fd_sc_hs__nor3_4.v b/cells/nor3/sky130_fd_sc_hs__nor3_4.v
index 46e6f67..e6591d3 100644
--- a/cells/nor3/sky130_fd_sc_hs__nor3_4.v
+++ b/cells/nor3/sky130_fd_sc_hs__nor3_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor3_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.v b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.v
index e909f84..391b9fa 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_1.v
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor3b_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.v b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.v
index 94ba79a..247f844 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_2.v
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor3b_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.v b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.v
index 5c1bd1b..a6fdc6a 100644
--- a/cells/nor3b/sky130_fd_sc_hs__nor3b_4.v
+++ b/cells/nor3b/sky130_fd_sc_hs__nor3b_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor3b_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_1.v b/cells/nor4/sky130_fd_sc_hs__nor4_1.v
index fc81ce0..4907141 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_1.v
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C,
+    D
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_2.v b/cells/nor4/sky130_fd_sc_hs__nor4_2.v
index 07028c6..6e4b5ad 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_2.v
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C,
+    D
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4/sky130_fd_sc_hs__nor4_4.v b/cells/nor4/sky130_fd_sc_hs__nor4_4.v
index 663935d..ae3e51e 100644
--- a/cells/nor4/sky130_fd_sc_hs__nor4_4.v
+++ b/cells/nor4/sky130_fd_sc_hs__nor4_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B,
+    C,
+    D
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.v b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.v
index 1aab004..aa685c8 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_1.v
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4b_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.v b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.v
index 90f9776..cecb7cd 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_2.v
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4b_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.v b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.v
index c03589a..0f3e1bd 100644
--- a/cells/nor4b/sky130_fd_sc_hs__nor4b_4.v
+++ b/cells/nor4b/sky130_fd_sc_hs__nor4b_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4b_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C   ,
-    D_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.v b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.v
index 294d7c6..7311605 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.v
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4bb_1 (
-    Y   ,
-    A   ,
-    B   ,
-    C_N ,
-    D_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.v b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.v
index c8c45eb..8e9833e 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.v
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4bb_2 (
-    Y   ,
-    A   ,
-    B   ,
-    C_N ,
-    D_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.v b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.v
index 2d8fb7b..bc7cc5f 100644
--- a/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.v
+++ b/cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__nor4bb_4 (
-    Y   ,
-    A   ,
-    B   ,
-    C_N ,
-    D_N ,
-    VPWR,
-    VGND
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.v b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.v
index dc3ee4b..8dd9931 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_1.v
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o2111a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.v b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.v
index 44aa4cf..5c22547 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_2.v
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o2111a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.v b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.v
index e20398e..8afde33 100644
--- a/cells/o2111a/sky130_fd_sc_hs__o2111a_4.v
+++ b/cells/o2111a/sky130_fd_sc_hs__o2111a_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o2111a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.v b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.v
index 91b753c..0d525bd 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.v
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o2111ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.v b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.v
index 6d9bd42..227a513 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.v
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o2111ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.v b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.v
index d5fd18a..d6eaecb 100644
--- a/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.v
+++ b/cells/o2111ai/sky130_fd_sc_hs__o2111ai_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o2111ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    D1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  D1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_1.v b/cells/o211a/sky130_fd_sc_hs__o211a_1.v
index 634f6bb..eb96c31 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_1.v
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o211a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_2.v b/cells/o211a/sky130_fd_sc_hs__o211a_2.v
index d73948f..dd03e4e 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_2.v
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o211a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o211a/sky130_fd_sc_hs__o211a_4.v b/cells/o211a/sky130_fd_sc_hs__o211a_4.v
index 240e312..84566a5 100644
--- a/cells/o211a/sky130_fd_sc_hs__o211a_4.v
+++ b/cells/o211a/sky130_fd_sc_hs__o211a_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o211a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.v b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.v
index 1bb2e4c..c269aed 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_1.v
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o211ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.v b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.v
index eec1cfe..ca72122 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_2.v
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o211ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.v b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.v
index 14d6a74..81cca78 100644
--- a/cells/o211ai/sky130_fd_sc_hs__o211ai_4.v
+++ b/cells/o211ai/sky130_fd_sc_hs__o211ai_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o211ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_1.v b/cells/o21a/sky130_fd_sc_hs__o21a_1.v
index e10141a..280eb2e 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_1.v
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__o21a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_2.v b/cells/o21a/sky130_fd_sc_hs__o21a_2.v
index fc31325..cc607d8 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_2.v
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__o21a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21a/sky130_fd_sc_hs__o21a_4.v b/cells/o21a/sky130_fd_sc_hs__o21a_4.v
index 0827494..185d495 100644
--- a/cells/o21a/sky130_fd_sc_hs__o21a_4.v
+++ b/cells/o21a/sky130_fd_sc_hs__o21a_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__o21a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.v b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.v
index f84dc4c..59718ac 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_1.v
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__o21ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.v b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.v
index 3ea7fe8..b81d1ac 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_2.v
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__o21ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.v b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.v
index 5e7f0aa..e55d2af 100644
--- a/cells/o21ai/sky130_fd_sc_hs__o21ai_4.v
+++ b/cells/o21ai/sky130_fd_sc_hs__o21ai_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__o21ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.v b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.v
index c100470..09e9303 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_1.v
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_1.v

@@ -75,17 +75,13 @@
     X   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output X   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.v b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.v
index 58b740f..0180029 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_2.v
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_2.v

@@ -75,17 +75,13 @@
     X   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output X   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.v b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.v
index 89c525f..b1f3815 100644
--- a/cells/o21ba/sky130_fd_sc_hs__o21ba_4.v
+++ b/cells/o21ba/sky130_fd_sc_hs__o21ba_4.v

@@ -75,17 +75,13 @@
     X   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output X   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.v b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.v
index 500eef8..e59a530 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_1.v
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_1.v

@@ -75,17 +75,13 @@
     Y   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output Y   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.v b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.v
index 64f5400..7fc0947 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_2.v
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_2.v

@@ -75,17 +75,13 @@
     Y   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output Y   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.v b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.v
index 319218c..1e0f05c 100644
--- a/cells/o21bai/sky130_fd_sc_hs__o21bai_4.v
+++ b/cells/o21bai/sky130_fd_sc_hs__o21bai_4.v

@@ -75,17 +75,13 @@
     Y   ,
     A1  ,
     A2  ,
-    B1_N,
-    VPWR,
-    VGND
+    B1_N
 );
 
     output Y   ;
     input  A1  ;
     input  A2  ;
     input  B1_N;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_1.v b/cells/o221a/sky130_fd_sc_hs__o221a_1.v
index b93df3c..1a25e7b 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_1.v
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o221a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_2.v b/cells/o221a/sky130_fd_sc_hs__o221a_2.v
index d33d82b..7376951 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_2.v
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o221a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o221a/sky130_fd_sc_hs__o221a_4.v b/cells/o221a/sky130_fd_sc_hs__o221a_4.v
index 9d276cf..f262ec5 100644
--- a/cells/o221a/sky130_fd_sc_hs__o221a_4.v
+++ b/cells/o221a/sky130_fd_sc_hs__o221a_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o221a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.v b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.v
index 716bbfb..fd27492 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_1.v
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o221ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.v b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.v
index fe81958..4010532 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_2.v
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o221ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.v b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.v
index 4e45c7d..7ec0628 100644
--- a/cells/o221ai/sky130_fd_sc_hs__o221ai_4.v
+++ b/cells/o221ai/sky130_fd_sc_hs__o221ai_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o221ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_1.v b/cells/o22a/sky130_fd_sc_hs__o22a_1.v
index aa4a2a7..2812793 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_1.v
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o22a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_2.v b/cells/o22a/sky130_fd_sc_hs__o22a_2.v
index addfb13..d5774ad 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_2.v
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o22a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o22a/sky130_fd_sc_hs__o22a_4.v b/cells/o22a/sky130_fd_sc_hs__o22a_4.v
index e2a26a6..4564153 100644
--- a/cells/o22a/sky130_fd_sc_hs__o22a_4.v
+++ b/cells/o22a/sky130_fd_sc_hs__o22a_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o22a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.v b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.v
index 0f79d8a..a02c5c8 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_1.v
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o22ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.v b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.v
index 4df216d..0efee1c 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_2.v
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o22ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.v b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.v
index bc75516..17ff788 100644
--- a/cells/o22ai/sky130_fd_sc_hs__o22ai_4.v
+++ b/cells/o22ai/sky130_fd_sc_hs__o22ai_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o22ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.v b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.v
index 917ea1e..99d1e36 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.v
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.v

@@ -78,9 +78,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output X   ;
@@ -88,8 +86,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.v b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.v
index f77d251..0db5306 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.v
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.v

@@ -78,9 +78,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output X   ;
@@ -88,8 +86,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.v b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.v
index 8c2cd5c..1929d24 100644
--- a/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.v
+++ b/cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.v

@@ -78,9 +78,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output X   ;
@@ -88,8 +86,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.v b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.v
index 6138434..9c143f5 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.v
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.v

@@ -78,9 +78,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output Y   ;
@@ -88,8 +86,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.v b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.v
index a2f059d..0b9be3b 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.v
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.v

@@ -78,9 +78,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output Y   ;
@@ -88,8 +86,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.v b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.v
index 91b4325..4612c58 100644
--- a/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.v
+++ b/cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.v

@@ -78,9 +78,7 @@
     A1_N,
     A2_N,
     B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    B2
 );
 
     output Y   ;
@@ -88,8 +86,6 @@
     input  A2_N;
     input  B1  ;
     input  B2  ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_1.v b/cells/o311a/sky130_fd_sc_hs__o311a_1.v
index cdff647..ac9161c 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_1.v
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o311a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_2.v b/cells/o311a/sky130_fd_sc_hs__o311a_2.v
index 659ce44..cb506a9 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_2.v
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o311a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o311a/sky130_fd_sc_hs__o311a_4.v b/cells/o311a/sky130_fd_sc_hs__o311a_4.v
index 8f25f0c..58d798c 100644
--- a/cells/o311a/sky130_fd_sc_hs__o311a_4.v
+++ b/cells/o311a/sky130_fd_sc_hs__o311a_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o311a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.v b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.v
index cac084a..ba9abef 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_1.v
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o311ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.v b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.v
index 464c9cd..3327d8e 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_2.v
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o311ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.v b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.v
index d34673a..d6459a6 100644
--- a/cells/o311ai/sky130_fd_sc_hs__o311ai_4.v
+++ b/cells/o311ai/sky130_fd_sc_hs__o311ai_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o311ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    C1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  C1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_1.v b/cells/o31a/sky130_fd_sc_hs__o31a_1.v
index fd5e626..70a1b9f 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_1.v
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o31a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_2.v b/cells/o31a/sky130_fd_sc_hs__o31a_2.v
index 1d95368..db4bca8 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_2.v
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o31a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o31a/sky130_fd_sc_hs__o31a_4.v b/cells/o31a/sky130_fd_sc_hs__o31a_4.v
index 905b973..bdce6ba 100644
--- a/cells/o31a/sky130_fd_sc_hs__o31a_4.v
+++ b/cells/o31a/sky130_fd_sc_hs__o31a_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o31a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.v b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.v
index c49bad0..5fb15b0 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_1.v
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_1.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o31ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.v b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.v
index 490da0f..56f59fb 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_2.v
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_2.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o31ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.v b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.v
index a1b6972..ac00caf 100644
--- a/cells/o31ai/sky130_fd_sc_hs__o31ai_4.v
+++ b/cells/o31ai/sky130_fd_sc_hs__o31ai_4.v

@@ -74,22 +74,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__o31ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_1.v b/cells/o32a/sky130_fd_sc_hs__o32a_1.v
index 3c37614..590e9b4 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_1.v
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o32a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_2.v b/cells/o32a/sky130_fd_sc_hs__o32a_2.v
index 31f5b6a..aa4c2e1 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_2.v
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o32a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o32a/sky130_fd_sc_hs__o32a_4.v b/cells/o32a/sky130_fd_sc_hs__o32a_4.v
index 02a47db..1bb5a2a 100644
--- a/cells/o32a/sky130_fd_sc_hs__o32a_4.v
+++ b/cells/o32a/sky130_fd_sc_hs__o32a_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o32a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.v b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.v
index 85ba088..c34d685 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_1.v
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o32ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.v b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.v
index 7d8cdd8..a475a58 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_2.v
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o32ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.v b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.v
index 54c6e72..1496b57 100644
--- a/cells/o32ai/sky130_fd_sc_hs__o32ai_4.v
+++ b/cells/o32ai/sky130_fd_sc_hs__o32ai_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o32ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    B1  ,
-    B2  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  B1  ;
-    input  B2  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_1.v b/cells/o41a/sky130_fd_sc_hs__o41a_1.v
index 4a010cc..b77647c 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_1.v
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o41a_1 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_2.v b/cells/o41a/sky130_fd_sc_hs__o41a_2.v
index f57a152..d111c79 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_2.v
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o41a_2 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o41a/sky130_fd_sc_hs__o41a_4.v b/cells/o41a/sky130_fd_sc_hs__o41a_4.v
index 2c9f2f6..a75fc25 100644
--- a/cells/o41a/sky130_fd_sc_hs__o41a_4.v
+++ b/cells/o41a/sky130_fd_sc_hs__o41a_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o41a_4 (
-    X   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output X   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.v b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.v
index 0590819..39082b7 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_1.v
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_1.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o41ai_1 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.v b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.v
index edf8c1f..5f66c13 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_2.v
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_2.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o41ai_2 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.v b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.v
index 8b62f92..ab3d568 100644
--- a/cells/o41ai/sky130_fd_sc_hs__o41ai_4.v
+++ b/cells/o41ai/sky130_fd_sc_hs__o41ai_4.v

@@ -77,24 +77,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__o41ai_4 (
-    Y   ,
-    A1  ,
-    A2  ,
-    A3  ,
-    A4  ,
-    B1  ,
-    VPWR,
-    VGND
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
 );
 
-    output Y   ;
-    input  A1  ;
-    input  A2  ;
-    input  A3  ;
-    input  A4  ;
-    input  B1  ;
-    input  VPWR;
-    input  VGND;
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or2/sky130_fd_sc_hs__or2_1.v b/cells/or2/sky130_fd_sc_hs__or2_1.v
index 20f3f12..df687b6 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_1.v
+++ b/cells/or2/sky130_fd_sc_hs__or2_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__or2_1 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or2/sky130_fd_sc_hs__or2_2.v b/cells/or2/sky130_fd_sc_hs__or2_2.v
index 6a7f3e6..9ee0fd1 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_2.v
+++ b/cells/or2/sky130_fd_sc_hs__or2_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__or2_2 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or2/sky130_fd_sc_hs__or2_4.v b/cells/or2/sky130_fd_sc_hs__or2_4.v
index cba21bd..10eac0c 100644
--- a/cells/or2/sky130_fd_sc_hs__or2_4.v
+++ b/cells/or2/sky130_fd_sc_hs__or2_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__or2_4 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_1.v b/cells/or2b/sky130_fd_sc_hs__or2b_1.v
index 6ba73de..f669f67 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_1.v
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_1.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__or2b_1 (
-    X   ,
-    A   ,
-    B_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_2.v b/cells/or2b/sky130_fd_sc_hs__or2b_2.v
index 0115d70..5190cbc 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_2.v
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_2.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__or2b_2 (
-    X   ,
-    A   ,
-    B_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or2b/sky130_fd_sc_hs__or2b_4.v b/cells/or2b/sky130_fd_sc_hs__or2b_4.v
index 2bec9e1..e0f240a 100644
--- a/cells/or2b/sky130_fd_sc_hs__or2b_4.v
+++ b/cells/or2b/sky130_fd_sc_hs__or2b_4.v

@@ -66,18 +66,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__or2b_4 (
-    X   ,
-    A   ,
-    B_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or3/sky130_fd_sc_hs__or3_1.v b/cells/or3/sky130_fd_sc_hs__or3_1.v
index 098ba25..73c785e 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_1.v
+++ b/cells/or3/sky130_fd_sc_hs__or3_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__or3_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or3/sky130_fd_sc_hs__or3_2.v b/cells/or3/sky130_fd_sc_hs__or3_2.v
index 57b3e9c..35ebdeb 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_2.v
+++ b/cells/or3/sky130_fd_sc_hs__or3_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__or3_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or3/sky130_fd_sc_hs__or3_4.v b/cells/or3/sky130_fd_sc_hs__or3_4.v
index 6a3da0e..8325de2 100644
--- a/cells/or3/sky130_fd_sc_hs__or3_4.v
+++ b/cells/or3/sky130_fd_sc_hs__or3_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__or3_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_1.v b/cells/or3b/sky130_fd_sc_hs__or3b_1.v
index 0c65167..3727779 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_1.v
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__or3b_1 (
-    X   ,
-    A   ,
-    B   ,
-    C_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_2.v b/cells/or3b/sky130_fd_sc_hs__or3b_2.v
index 1250fa0..c518208 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_2.v
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__or3b_2 (
-    X   ,
-    A   ,
-    B   ,
-    C_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or3b/sky130_fd_sc_hs__or3b_4.v b/cells/or3b/sky130_fd_sc_hs__or3b_4.v
index 36e25d3..e06d15a 100644
--- a/cells/or3b/sky130_fd_sc_hs__or3b_4.v
+++ b/cells/or3b/sky130_fd_sc_hs__or3b_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__or3b_4 (
-    X   ,
-    A   ,
-    B   ,
-    C_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4/sky130_fd_sc_hs__or4_1.v b/cells/or4/sky130_fd_sc_hs__or4_1.v
index e3b8f9b..a248de6 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_1.v
+++ b/cells/or4/sky130_fd_sc_hs__or4_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C,
+    D
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4/sky130_fd_sc_hs__or4_2.v b/cells/or4/sky130_fd_sc_hs__or4_2.v
index 41f2c11..ac236f9 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_2.v
+++ b/cells/or4/sky130_fd_sc_hs__or4_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C,
+    D
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4/sky130_fd_sc_hs__or4_4.v b/cells/or4/sky130_fd_sc_hs__or4_4.v
index 1521690..f90fd44 100644
--- a/cells/or4/sky130_fd_sc_hs__or4_4.v
+++ b/cells/or4/sky130_fd_sc_hs__or4_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C,
+    D
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_1.v b/cells/or4b/sky130_fd_sc_hs__or4b_1.v
index 6b9dfcb..9b63145 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_1.v
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4b_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_2.v b/cells/or4b/sky130_fd_sc_hs__or4b_2.v
index ec0fb24..65cb573 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_2.v
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4b_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4b/sky130_fd_sc_hs__or4b_4.v b/cells/or4b/sky130_fd_sc_hs__or4b_4.v
index 8dcefb1..6e65986 100644
--- a/cells/or4b/sky130_fd_sc_hs__or4b_4.v
+++ b/cells/or4b/sky130_fd_sc_hs__or4b_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4b_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    D_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.v b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.v
index 0b6f8a8..cee6b6c 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_1.v
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4bb_1 (
-    X   ,
-    A   ,
-    B   ,
-    C_N ,
-    D_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.v b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.v
index b80b0f7..884e535 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_2.v
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4bb_2 (
-    X   ,
-    A   ,
-    B   ,
-    C_N ,
-    D_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.v b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.v
index d381411..00fe36c 100644
--- a/cells/or4bb/sky130_fd_sc_hs__or4bb_4.v
+++ b/cells/or4bb/sky130_fd_sc_hs__or4bb_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__or4bb_4 (
-    X   ,
-    A   ,
-    B   ,
-    C_N ,
-    D_N ,
-    VPWR,
-    VGND
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C_N ;
-    input  D_N ;
-    input  VPWR;
-    input  VGND;
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.v b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.v
index af14377..24ec8e3 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.v
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.v

@@ -89,9 +89,7 @@
     SCE    ,
     CLK_N  ,
     SET_B  ,
-    RESET_B,
-    VPWR   ,
-    VGND
+    RESET_B
 );
 
     output Q      ;
@@ -102,8 +100,6 @@
     input  CLK_N  ;
     input  SET_B  ;
     input  RESET_B;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.v b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.v
index 69513ed..fa4fd71 100644
--- a/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.v
+++ b/cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_2.v

@@ -89,9 +89,7 @@
     SCE    ,
     CLK_N  ,
     SET_B  ,
-    RESET_B,
-    VPWR   ,
-    VGND
+    RESET_B
 );
 
     output Q      ;
@@ -102,8 +100,6 @@
     input  CLK_N  ;
     input  SET_B  ;
     input  RESET_B;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.v b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.v
index 0cb19eb..5a26c26 100644
--- a/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.v
+++ b/cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.v

@@ -89,9 +89,7 @@
     SCE    ,
     CLK    ,
     SET_B  ,
-    RESET_B,
-    VPWR   ,
-    VGND
+    RESET_B
 );
 
     output Q      ;
@@ -102,8 +100,6 @@
     input  CLK    ;
     input  SET_B  ;
     input  RESET_B;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.v b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.v
index 44f3acb..51c8396 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.v
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.v

@@ -85,9 +85,7 @@
     Q      ,
     Q_N    ,
     SCD    ,
-    SCE    ,
-    VPWR   ,
-    VGND
+    SCE
 );
 
     input  RESET_B;
@@ -97,8 +95,6 @@
     output Q_N    ;
     input  SCD    ;
     input  SCE    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.v b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.v
index 141fbe9..4860b8b 100644
--- a/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.v
+++ b/cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.v

@@ -85,9 +85,7 @@
     Q      ,
     Q_N    ,
     SCD    ,
-    SCE    ,
-    VPWR   ,
-    VGND
+    SCE
 );
 
     input  RESET_B;
@@ -97,8 +95,6 @@
     output Q_N    ;
     input  SCD    ;
     input  SCE    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.v b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.v
index 8de412c..ea52560 100644
--- a/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.v
+++ b/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.v

@@ -81,9 +81,7 @@
     D      ,
     Q      ,
     SCD    ,
-    SCE    ,
-    VPWR   ,
-    VGND
+    SCE
 );
 
     input  RESET_B;
@@ -92,8 +90,6 @@
     output Q      ;
     input  SCD    ;
     input  SCE    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.v b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.v
index b5f3e00..f2152c9 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.v
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.v

@@ -81,9 +81,7 @@
     D      ,
     Q      ,
     SCD    ,
-    SCE    ,
-    VPWR   ,
-    VGND
+    SCE
 );
 
     input  RESET_B;
@@ -92,8 +90,6 @@
     output Q      ;
     input  SCD    ;
     input  SCE    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.v b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.v
index 041ae5f..54b09ed 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.v
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.v

@@ -81,9 +81,7 @@
     D      ,
     Q      ,
     SCD    ,
-    SCE    ,
-    VPWR   ,
-    VGND
+    SCE
 );
 
     input  RESET_B;
@@ -92,8 +90,6 @@
     output Q      ;
     input  SCD    ;
     input  SCE    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.v b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.v
index e3af838..9993ec9 100644
--- a/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.v
+++ b/cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.v

@@ -81,9 +81,7 @@
     D      ,
     Q      ,
     SCD    ,
-    SCE    ,
-    VPWR   ,
-    VGND
+    SCE
 );
 
     input  RESET_B;
@@ -92,8 +90,6 @@
     output Q      ;
     input  SCD    ;
     input  SCE    ;
-    input  VPWR   ;
-    input  VGND   ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.v b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.v
index a8becac..de86881 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.v
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_1.v

@@ -85,9 +85,7 @@
     Q_N  ,
     SCD  ,
     SCE  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -97,8 +95,6 @@
     input  SCD  ;
     input  SCE  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.v b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.v
index 87a6d27..be2b769 100644
--- a/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.v
+++ b/cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.v

@@ -85,9 +85,7 @@
     Q_N  ,
     SCD  ,
     SCE  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -97,8 +95,6 @@
     input  SCD  ;
     input  SCE  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.v b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.v
index dd0e9ac..2a11eea 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.v
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_1.v

@@ -81,9 +81,7 @@
     Q    ,
     SCD  ,
     SCE  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -92,8 +90,6 @@
     input  SCD  ;
     input  SCE  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.v b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.v
index b65dea0..91c6c49 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.v
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_2.v

@@ -81,9 +81,7 @@
     Q    ,
     SCD  ,
     SCE  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -92,8 +90,6 @@
     input  SCD  ;
     input  SCE  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.v b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.v
index bdbf605..f9a9c5d 100644
--- a/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.v
+++ b/cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.v

@@ -81,9 +81,7 @@
     Q    ,
     SCD  ,
     SCE  ,
-    SET_B,
-    VPWR ,
-    VGND
+    SET_B
 );
 
     input  CLK  ;
@@ -92,8 +90,6 @@
     input  SCD  ;
     input  SCE  ;
     input  SET_B;
-    input  VPWR ;
-    input  VGND ;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.v b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.v
index c1fe6d3..af948b5 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.v
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.v

@@ -75,24 +75,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__sdfxbp_1 (
-    CLK ,
-    D   ,
-    Q   ,
-    Q_N ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    Q_N,
+    SCD,
+    SCE
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    output Q_N ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    output Q_N;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.v b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.v
index 518c7fa..15d33d5 100644
--- a/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.v
+++ b/cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.v

@@ -75,24 +75,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__sdfxbp_2 (
-    CLK ,
-    D   ,
-    Q   ,
-    Q_N ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    Q_N,
+    SCD,
+    SCE
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    output Q_N ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    output Q_N;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.v b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.v
index edd36f2..4e80e68 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.v
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_1.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__sdfxtp_1 (
-    CLK ,
-    D   ,
-    Q   ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    SCD,
+    SCE
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.v b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.v
index 8dd02a9..d70087a 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.v
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__sdfxtp_2 (
-    CLK ,
-    D   ,
-    Q   ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    SCD,
+    SCE
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.v b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.v
index a106f36..67886e2 100644
--- a/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.v
+++ b/cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.v

@@ -72,22 +72,18 @@
 
 `celldefine
 module sky130_fd_sc_hs__sdfxtp_4 (
-    CLK ,
-    D   ,
-    Q   ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    CLK,
+    D  ,
+    Q  ,
+    SCD,
+    SCE
 );
 
-    input  CLK ;
-    input  D   ;
-    output Q   ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    input  CLK;
+    input  D  ;
+    output Q  ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.v b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.v
index 68c1bce..7067191 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.v
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.v

@@ -72,17 +72,13 @@
     GCLK,
     GATE,
     CLK ,
-    SCE ,
-    VPWR,
-    VGND
+    SCE
 );
 
     output GCLK;
     input  GATE;
     input  CLK ;
     input  SCE ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.v b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.v
index 36814ea..762685c 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.v
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.v

@@ -72,17 +72,13 @@
     GCLK,
     GATE,
     CLK ,
-    SCE ,
-    VPWR,
-    VGND
+    SCE
 );
 
     output GCLK;
     input  GATE;
     input  CLK ;
     input  SCE ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.v b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.v
index e31b494..8bc5e49 100644
--- a/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.v
+++ b/cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.v

@@ -72,17 +72,13 @@
     GCLK,
     GATE,
     CLK ,
-    SCE ,
-    VPWR,
-    VGND
+    SCE
 );
 
     output GCLK;
     input  GATE;
     input  CLK ;
     input  SCE ;
-    input  VPWR;
-    input  VGND;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.v b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.v
index 6b793ea..96e2de6 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.v
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_1.v

@@ -79,26 +79,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__sedfxbp_1 (
-    Q   ,
-    Q_N ,
-    CLK ,
-    D   ,
-    DE  ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
 );
 
-    output Q   ;
-    output Q_N ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.v b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.v
index e8f40df..67dbefe 100644
--- a/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.v
+++ b/cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.v

@@ -79,26 +79,22 @@
 
 `celldefine
 module sky130_fd_sc_hs__sedfxbp_2 (
-    Q   ,
-    Q_N ,
-    CLK ,
-    D   ,
-    DE  ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
 );
 
-    output Q   ;
-    output Q_N ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.v b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.v
index 6c75492..8a7ad79 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.v
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_1.v

@@ -76,24 +76,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__sedfxtp_1 (
-    Q   ,
-    CLK ,
-    D   ,
-    DE  ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
 );
 
-    output Q   ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.v b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.v
index 316e604..ef45b89 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.v
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.v

@@ -76,24 +76,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__sedfxtp_2 (
-    Q   ,
-    CLK ,
-    D   ,
-    DE  ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
 );
 
-    output Q   ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.v b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.v
index 04f49a7..badf73f 100644
--- a/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.v
+++ b/cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.v

@@ -76,24 +76,20 @@
 
 `celldefine
 module sky130_fd_sc_hs__sedfxtp_4 (
-    Q   ,
-    CLK ,
-    D   ,
-    DE  ,
-    SCD ,
-    SCE ,
-    VPWR,
-    VGND
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
 );
 
-    output Q   ;
-    input  CLK ;
-    input  D   ;
-    input  DE  ;
-    input  SCD ;
-    input  SCE ;
-    input  VPWR;
-    input  VGND;
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/tap/sky130_fd_sc_hs__tap_1.v b/cells/tap/sky130_fd_sc_hs__tap_1.v
index 78b5c89..d8d1a1f 100644
--- a/cells/tap/sky130_fd_sc_hs__tap_1.v
+++ b/cells/tap/sky130_fd_sc_hs__tap_1.v

@@ -56,14 +56,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__tap_1 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__tap_1 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/tap/sky130_fd_sc_hs__tap_2.v b/cells/tap/sky130_fd_sc_hs__tap_2.v
index a921ba5..142b0c7 100644
--- a/cells/tap/sky130_fd_sc_hs__tap_2.v
+++ b/cells/tap/sky130_fd_sc_hs__tap_2.v

@@ -56,14 +56,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__tap_2 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__tap_2 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.v b/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.v
index 701d07a..fcfc29e 100644
--- a/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.v
+++ b/cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.v

@@ -56,14 +56,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__tapmet1_2 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__tapmet1_2 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.v b/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.v
index 14c15e0..10ae576 100644
--- a/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.v
+++ b/cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.v

@@ -57,14 +57,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__tapvgnd_1 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__tapvgnd_1 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.v b/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.v
index c6a83ad..6e36866 100644
--- a/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.v
+++ b/cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.v

@@ -57,14 +57,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__tapvgnd2_1 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__tapvgnd2_1 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.v b/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.v
index cd74157..26cfc11 100644
--- a/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.v
+++ b/cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.v

@@ -56,14 +56,7 @@
 /*********************************************************/
 
 `celldefine
-module sky130_fd_sc_hs__tapvpwrvgnd_1 (
-    VPWR,
-    VGND
-);
-
-    input VPWR;
-    input VGND;
-
+module sky130_fd_sc_hs__tapvpwrvgnd_1 ();
     // Voltage supply signals
     supply1 VPWR;
     supply0 VGND;

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.v b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.v
index 399ccb5..85ebb91 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_1.v
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_1.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__xnor2_1 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.v b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.v
index ceb6e88..7718d35 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_2.v
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_2.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__xnor2_2 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.v b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.v
index fe48d07..954b214 100644
--- a/cells/xnor2/sky130_fd_sc_hs__xnor2_4.v
+++ b/cells/xnor2/sky130_fd_sc_hs__xnor2_4.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__xnor2_4 (
-    Y   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    Y,
+    A,
+    B
 );
 
-    output Y   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output Y;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.v b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.v
index 723a7aa..91c69c9 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_1.v
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_1.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__xnor3_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.v b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.v
index 7c62856..9c96392 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_2.v
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_2.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__xnor3_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.v b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.v
index e62aa8d..9cd7c82 100644
--- a/cells/xnor3/sky130_fd_sc_hs__xnor3_4.v
+++ b/cells/xnor3/sky130_fd_sc_hs__xnor3_4.v

@@ -69,20 +69,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__xnor3_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_1.v b/cells/xor2/sky130_fd_sc_hs__xor2_1.v
index 38bb512..3fa8b89 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_1.v
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_1.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__xor2_1 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_2.v b/cells/xor2/sky130_fd_sc_hs__xor2_2.v
index 28cff31..ad44e6e 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_2.v
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_2.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__xor2_2 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xor2/sky130_fd_sc_hs__xor2_4.v b/cells/xor2/sky130_fd_sc_hs__xor2_4.v
index 97b9d82..6122a13 100644
--- a/cells/xor2/sky130_fd_sc_hs__xor2_4.v
+++ b/cells/xor2/sky130_fd_sc_hs__xor2_4.v

@@ -68,18 +68,14 @@
 
 `celldefine
 module sky130_fd_sc_hs__xor2_4 (
-    X   ,
-    A   ,
-    B   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_1.v b/cells/xor3/sky130_fd_sc_hs__xor3_1.v
index 164d141..b52b80a 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_1.v
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_1.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__xor3_1 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_2.v b/cells/xor3/sky130_fd_sc_hs__xor3_2.v
index e68b943..82e8264 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_2.v
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_2.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__xor3_2 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;

diff --git a/cells/xor3/sky130_fd_sc_hs__xor3_4.v b/cells/xor3/sky130_fd_sc_hs__xor3_4.v
index afcfcff..509a41e 100644
--- a/cells/xor3/sky130_fd_sc_hs__xor3_4.v
+++ b/cells/xor3/sky130_fd_sc_hs__xor3_4.v

@@ -71,20 +71,16 @@
 
 `celldefine
 module sky130_fd_sc_hs__xor3_4 (
-    X   ,
-    A   ,
-    B   ,
-    C   ,
-    VPWR,
-    VGND
+    X,
+    A,
+    B,
+    C
 );
 
-    output X   ;
-    input  A   ;
-    input  B   ;
-    input  C   ;
-    input  VPWR;
-    input  VGND;
+    output X;
+    input  A;
+    input  B;
+    input  C;
 
     // Voltage supply signals
     supply1 VPWR;
commit	2a82aa593da417e5b757736ef67ddd5d37a80ace	[log] [tgz]
author	Tim 'mithro' Ansell <me@mith.ro>	Wed Oct 28 20:05:43 2020 -0700
committer	Tim 'mithro' Ansell <tansell@google.com>	Wed Oct 28 20:05:43 2020 -0700
tree	565caf8648208a0ab399c244cb1fd6fd7425cf48
parent	d672c39737b5ca3963c3b9e64dd9d6bcbf929ec9 [diff]
parent	a145d4373b1449b5bee7521bea09c6e62db088f4 [diff]