blob: 721f0105d10f3097c9aaec1faaac259319ee3cdf [file] [log] [blame]
{
"area": 25.5744,
"cell_footprint": "sdlclkp",
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
"leakage_power": [
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"when": "!GATE&!SCE&!CLK"
},
{
"value": 0.14277,
"when": "!GATE&!SCE&CLK"
},
{
"value": 0.10525,
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},
{
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},
{
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},
{
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},
{
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},
{
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}
],
"pg_pin VGND": {
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
"pg_pin VPB": {
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"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"voltage_name": "VPWR"
},
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"clock": "true",
"clock_gate_clock_pin": "true",
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"related_ground_pin": "VGND",
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},
"pin GATE": {
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"clock": "false",
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0.52912
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0.75,
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0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
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0.076,
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0.06819,
0.06819,
0.06428
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]
},
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}
]
},
"pin GCLK": {
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"direction": "output",
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0.02602,
0.03903,
0.05855,
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0.03903,
0.05855,
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0.06472,
0.08853,
0.12411,
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0.259
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}
},
"max_capacitance": 0.21672,
"power_down_function": "(!VPWR + VGND)",
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"state_function": "(CLK*M0)",
"timing": {
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0.02602,
0.03903,
0.05855,
0.08782,
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0.6667,
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0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
"values": [
[
0.02131,
0.02912,
0.03303,
0.04084,
0.05256,
0.06037,
0.06428,
0.06819,
0.06819,
0.06428
],
[
0.0135,
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0.02522,
0.03303,
0.04084,
0.05256,
0.05647,
0.06037,
0.06037,
0.05647
],
[
0.00178,
0.00569,
0.0135,
0.02131,
0.02912,
0.04084,
0.04475,
0.04865,
0.04865,
0.04475
],
[
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0.02522,
0.02522,
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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-0.18963
]
]
},
"timing_type": "hold_rising"
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}