cells/clkdlyinv3sd1/definition.json

{
 "description": "Clock Delay Inverter 3-stage 0.15um length inner stage gate.",
 "file_prefix": "sky130_fd_sc_hs__clkdlyinv3sd1",
 "library": "sky130_fd_sc_hs",
 "name": "clkdlyinv3sd1",
 "parameters": [],
 "ports": [
  [
   "signal",
   "Y",
   "output",
   ""
  ],
  [
   "signal",
   "A",
   "input",
   ""
  ],
  [
   "power",
   "VPWR",
   "input",
   "supply1"
  ],
  [
   "power",
   "VGND",
   "input",
   "supply0"
  ]
 ],
 "type": "cell",
 "verilog_name": "sky130_fd_sc_hs__clkdlyinv3sd1"
}