| { |
| "area": 25.024, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.003951072, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 0.0042251, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.0040194, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0044458, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0045069, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0042352, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0054759, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.0045383, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0026732, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0027372, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.004291, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0024671, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0037978, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.00427, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
| 0.0208008, |
| 0.0207967, |
| 0.0207871, |
| 0.0208473, |
| 0.0209859, |
| 0.0213056, |
| 0.0220423 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0077941, |
| 0.0075689, |
| 0.0075666, |
| 0.0075612, |
| 0.0075488, |
| 0.0075203 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| "timing": { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| 0.2333956, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001774, |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0255242, |
| 0.0256298, |
| 0.0258735, |
| 0.026435, |
| 0.0277294 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0158794, |
| 0.0157999, |
| 0.0157737, |
| 0.0157133, |
| 0.0155741, |
| 0.0152533 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002136, |
| "timing": [ |
| { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| [ |
| 0.2082988, |
| 0.3598125, |
| 0.6381328 |
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| [ |
| 0.1251445, |
| 0.2778789, |
| 0.5549785 |
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| [ |
| 0.0702129, |
| 0.2229473, |
| 0.4963848 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
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| [ |
| 0.0750957, |
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| [ |
| 0.1104961, |
| 0.2082988, |
| 0.2876445 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.1811055, |
| -0.3326191, |
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| ], |
| [ |
| -0.1138203, |
| -0.2677754, |
| -0.5375508 |
| ], |
| [ |
| -0.0625508, |
| -0.2140645, |
| -0.4850606 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
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| -0.055373, |
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| [ |
| -0.0112812, |
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| [ |
| -0.0027363, |
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| -0.1615742 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
| "fall_power,power_outputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.03999859, |
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| 0.0244416, |
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| "related_pin": "CLK", |
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| 0.6021403 |
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| }, |
| { |
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| "related_pin": "CLK", |
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| "when": "(GATE&!SCE)" |
| }, |
| { |
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| "related_pin": "CLK", |
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| }, |
| { |
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| "internal_node": "M0", |
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| "related_power_pin": "VPWR", |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
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| }, |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
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| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
