| { |
| "area": 25.024, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
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| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
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| { |
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| { |
| "value": 7.67978, |
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| }, |
| { |
| "value": 8.69101, |
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| }, |
| { |
| "value": 8.72432, |
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| { |
| "value": 8.28585, |
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| { |
| "value": 10.2199, |
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| }, |
| { |
| "value": 8.41208, |
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| }, |
| { |
| "value": 5.5468, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
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| { |
| "value": 5.58012, |
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| }, |
| { |
| "value": 8.11828, |
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| }, |
| { |
| "value": 5.14161, |
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| }, |
| { |
| "value": 7.16147, |
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| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
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| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock_gate_clock_pin": "true", |
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| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.627, |
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| "clock_gate_enable_pin": "true", |
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| 0.0123033 |
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| { |
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| }, |
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| "related_pin": "CLK", |
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| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
