| { |
| "area": 25.024, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.003065856, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 0.0031363, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.0031325, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0039205, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0029612, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.003921, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0024196, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.0029957, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0033811, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0024199, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0022113, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0033782, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0029129, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004127, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003854, |
| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
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| 0.0169832, |
| 0.0168715, |
| 0.0169004, |
| 0.0169669, |
| 0.0171203, |
| 0.0174738 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0065002, |
| 0.0064651, |
| 0.0064344, |
| 0.0063635, |
| 0.0062002, |
| 0.0058238 |
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| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| 0.2150869, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001727, |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0210594, |
| 0.0213805 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.0128085, |
| 0.0127336, |
| 0.0125611, |
| 0.0121635 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00212, |
| "timing": [ |
| { |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| 0.01, |
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| 1.5 |
| ], |
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| [ |
| 0.1948711, |
| 0.3585918, |
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| [ |
| 0.1263652, |
| 0.293748, |
| 0.6074687 |
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| [ |
| 0.0909648, |
| 0.2559063, |
| 0.5708476 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
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| "index_2": [ |
| 0.01, |
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| 0.0665508, |
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| [ |
| 0.1324687, |
| 0.2229473, |
| 0.2876445 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.1713398, |
| -0.3375019, |
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| [ |
| -0.1199238, |
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| [ |
| -0.0845234, |
| -0.2494649, |
| -0.5619648 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
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| "index_2": [ |
| 0.01, |
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| -0.0419453, |
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| [ |
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| [ |
| -0.0137227, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
| "fall_power,power_outputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.1165535, |
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| 0.01864, |
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| "related_pin": "CLK", |
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| { |
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| "related_pin": "CLK", |
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| }, |
| { |
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| }, |
| { |
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| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
