| { |
| "area": 25.024, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 8.210733, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
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| { |
| "value": 9.0214, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 5.97124, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 6.0033, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 8.76485, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 5.52097, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 8.73279, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 8.28253, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 9.32194, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 9.354, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 8.87172, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 11.0232, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 7.66086, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004146, |
| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
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| 0.0176638, |
| 0.0173869, |
| 0.017559, |
| 0.0179558, |
| 0.0188703, |
| 0.0209782 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0069643, |
| 0.0072489, |
| 0.007905, |
| 0.0094174 |
| ] |
| } |
| }, |
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| "related_power_pin": "VPWR", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| 0.1845724, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.0231508, |
| 0.0235965, |
| 0.0246239, |
| 0.0269921 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
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| 0.122474, |
| 0.282311, |
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| 0.013296, |
| 0.0134109, |
| 0.0136757, |
| 0.0142859, |
| 0.0156927 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
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| "related_power_pin": "VPWR", |
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| { |
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| 0.01, |
| 0.5, |
| 1.5 |
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| 0.01, |
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| ], |
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| [ |
| 0.1606914, |
| 0.2914531, |
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| [ |
| 0.1031719, |
| 0.236375, |
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| [ |
| 0.0775371, |
| 0.2095195, |
| 0.4158184 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.1301738, |
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| [ |
| 0.0970684, |
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| [ |
| 0.1947246, |
| 0.2717754, |
| 0.3083965 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.1359394, |
| -0.2667012, |
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| [ |
| -0.0930684, |
| -0.2250508, |
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| [ |
| -0.0710957, |
| -0.2030781, |
| -0.4069355 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| 0.01, |
| 0.5, |
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| [ |
| -0.0198262, |
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| [ |
| -0.0271504, |
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| ] |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
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| "fall_power,power_outputs_1": { |
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| 0.01, |
| 0.0230506, |
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| { |
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| { |
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| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
