| { |
| "area": 21.2704, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.00282, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.00272, |
| "internal_power": { |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
| 4.9999998 |
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| 0.0050647, |
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| 0.0064017, |
| 0.0091817 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
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| } |
| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002947, |
| "timing": { |
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| 0.01, |
| 2.5, |
| 5.0 |
| ], |
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| 3.169399, |
| 6.2519998 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
| "pin,GATE": { |
| "capacitance": 0.001567, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001456, |
| "internal_power": { |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
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| 0.0024415, |
| 0.0032417, |
| 0.0054959, |
| 0.0118468 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
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| 0.0045372, |
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| 0.0040805, |
| 0.0043385, |
| 0.0050656, |
| 0.007114 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001677, |
| "timing": [ |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
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| 5.0 |
| ], |
| "values": [ |
| [ |
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| ], |
| [ |
| 1.2964091, |
| 2.4537823, |
| 3.7037822 |
| ], |
| [ |
| 0.375999, |
| 1.5223857, |
| 2.7577372 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
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| ], |
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| ], |
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| ], |
| [ |
| -1.0668721, |
| -0.0211934, |
| 0.90471 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
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| 5.0 |
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| "values": [ |
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| -2.3747091, |
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| [ |
| -1.2136738, |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
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| 0.01, |
| 0.0281727, |
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| 0.629961, |
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| 0.01852223, |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
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| 0.223607, |
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| ] |
| }, |
| "when": "(!GATE&SCE)" |
| }, |
| { |
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| "related_pin": "CLK", |
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| }, |
| "when": "(GATE&!SCE)" |
| }, |
| { |
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| "related_pin": "CLK", |
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| "when": "(GATE&SCE)" |
| }, |
| { |
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| "related_pin": "CLK", |
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| 0.0 |
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| }, |
| "when": "(!GATE&!SCE)" |
| } |
| ], |
| "max_capacitance": 0.112734, |
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| { |
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| "related_pin": "CLK", |
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| "timing_sense": "positive_unate", |
| "timing_type": "combinational_fall", |
| "when": "(!GATE&!SCE)" |
| } |
| ] |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,SCE": { |
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| "clock": "false", |
| "clock_gate_test_pin": "true", |
| "direction": "input", |
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| "internal_power": { |
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| } |
| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001571, |
| "timing": [ |
| { |
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| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 2.5, |
| 5.0 |
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| [ |
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| [ |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
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| 0.01, |
| 2.5, |
| 5.0 |
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| 0.01, |
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| 5.0 |
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| [ |
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| [ |
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| [ |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_3_3_1": { |
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| 0.01, |
| 2.5, |
| 5.0 |
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| "index_2": [ |
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| [ |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
