| { |
| "area": 21.2704, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 6.643146, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
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| { |
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| }, |
| { |
| "value": 5.40273, |
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| }, |
| { |
| "value": 5.41489, |
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| }, |
| { |
| "value": 5.39099, |
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| }, |
| { |
| "value": 4.96804, |
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| }, |
| { |
| "value": 7.1071, |
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| }, |
| { |
| "value": 5.37883, |
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| }, |
| { |
| "value": 4.94413, |
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| }, |
| { |
| "value": 8.59734, |
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| }, |
| { |
| "value": 8.60949, |
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| }, |
| { |
| "value": 8.16267, |
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| }, |
| { |
| "value": 7.4684, |
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| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
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| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0156756, |
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| 0.0156833, |
| 0.0156958 |
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| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.0070758, |
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| 0.0070975 |
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| 0.627, |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| 0.0199813 |
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| 0.0119956, |
| 0.0117709 |
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| [ |
| 0.1007305, |
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| ] |
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| 0.5, |
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| ] |
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| "sim_opt": "runlvl=5 accurate=1", |
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| { |
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| 0.5, |
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| "index_2": [ |
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| -0.4191426, |
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| -0.2676289, |
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| -0.0857441, |
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| ] |
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| 0.0888164, |
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| ] |
| }, |
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| "internal_node": "M0", |
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| "sim_opt": "runlvl=5 accurate=1", |
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| }, |
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| "related_pin": "CLK", |
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| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
