| { |
| "area": 21.2704, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 10.88159, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 13.1318, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 8.84286, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 8.81117, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 9.50167, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 7.96748, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 11.1208, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 9.53336, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 8.65799, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 13.7004, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 13.6687, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 12.8251, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 12.8178, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.003971, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003803, |
| "internal_power": { |
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| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
| 0.0237815, |
| 0.0237368, |
| 0.0236338, |
| 0.0242783, |
| 0.0257639, |
| 0.0291882, |
| 0.0370816 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0103962, |
| 0.010097, |
| 0.0107661, |
| 0.0123084, |
| 0.0158635, |
| 0.0240583 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
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| "related_power_pin": "VPWR", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| 0.1345286, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| "fall_capacitance": 0.001917, |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0329939, |
| 0.0327658, |
| 0.0333887, |
| 0.0348247, |
| 0.0381347, |
| 0.0457643 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.017925, |
| 0.0179375, |
| 0.0179664, |
| 0.0185507, |
| 0.0198975, |
| 0.0230021, |
| 0.0301582 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002216, |
| "timing": [ |
| { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| [ |
| 0.113084, |
| 0.2316387, |
| 0.4123027 |
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| [ |
| 0.0836406, |
| 0.2046367, |
| 0.3865215 |
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| [ |
| 0.0982891, |
| 0.2168438, |
| 0.3999492 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
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| ], |
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| 0.0911113, |
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| [ |
| 0.0885234, |
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| [ |
| 0.197166, |
| 0.2412578, |
| 0.2217266 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.096877, |
| -0.2117695, |
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| ], |
| [ |
| -0.0759785, |
| -0.1945332, |
| -0.3727559 |
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| [ |
| -0.090627, |
| -0.2079609, |
| -0.3898457 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
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| "index_2": [ |
| 0.01, |
| 0.5, |
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| ], |
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| -0.0370625, |
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| [ |
| -0.0295918, |
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| [ |
| -0.0686543, |
| -0.109084, |
| -0.0895527 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
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| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
| "fall_power,power_outputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.0005, |
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| 0.03353735, |
| 0.09597727, |
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| 0.0181145, |
| 0.0160954, |
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| [ |
| 0.0177434, |
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| -0.0442851, |
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| [ |
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| [ |
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| [ |
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| "related_pin": "CLK", |
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| { |
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| "related_pin": "CLK", |
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| { |
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| { |
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| }, |
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| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
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| "clock_gate_test_pin": "true", |
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| "related_power_pin": "VPWR", |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
