| { |
| "area": 20.0192, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.003438836, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 0.0045489, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0027529, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0028044, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0026825, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0025287, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0037743, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0026304, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.002405, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0044874, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0045408, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0042647, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0038462, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.003642, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003466, |
| "internal_power": { |
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| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
| 0.0196805, |
| 0.0195744, |
| 0.0193298, |
| 0.019314, |
| 0.0192777, |
| 0.019194, |
| 0.0190011 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| ], |
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| 0.0083412, |
| 0.0082917, |
| 0.0081776, |
| 0.0082086, |
| 0.0082801, |
| 0.0084447, |
| 0.0088242 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.003866, |
| "timing": { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| 0.223631, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
| "pin,GATE": { |
| "capacitance": 0.001922, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001756, |
| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| ], |
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| 0.0245932, |
| 0.0243915, |
| 0.0239268, |
| 0.0240203, |
| 0.0242358, |
| 0.0247326, |
| 0.0258778 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| ], |
| "values": [ |
| 0.015257, |
| 0.0152144, |
| 0.015116, |
| 0.0150935, |
| 0.0150417, |
| 0.0149222, |
| 0.0146469 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002087, |
| "timing": [ |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| 0.2009746, |
| 0.353709, |
| 0.6271465 |
| ], |
| [ |
| 0.1214824, |
| 0.2742168, |
| 0.5464336 |
| ], |
| [ |
| 0.0714336, |
| 0.2229473, |
| 0.4927226 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
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| [ |
| 0.1069805, |
| 0.2072246, |
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| [ |
| 0.0457988, |
| 0.1423809, |
| 0.2205059 |
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| [ |
| 0.0677715, |
| 0.1619121, |
| 0.2375957 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.1945332, |
| -0.3472676, |
| -0.6121602 |
| ], |
| [ |
| -0.1174824, |
| -0.2702168, |
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| ], |
| [ |
| -0.0662129, |
| -0.2177266, |
| -0.4875019 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.0529316, |
| -0.1495137, |
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| [ |
| -0.0112812, |
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| [ |
| -0.0051777, |
| -0.096877, |
| -0.1615742 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
| "fall_power,power_outputs_1": { |
| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| ], |
| "index_2": [ |
| 0.0005, |
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| 0.007248, |
| 0.01767262, |
| 0.04309071, |
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| 0.0081825, |
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| 0.0052896, |
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| [ |
| 0.0081932, |
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| [ |
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| [ |
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| [ |
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| [ |
| 0.0072345, |
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| [ |
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| ] |
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| "related_pin": "CLK", |
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| 0.0230506, |
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| 0.0098975, |
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| [ |
| 0.0101607, |
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| 0.0211849, |
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| 0.0785551, |
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| ] |
| }, |
| "when": "(!GATE&SCE)" |
| }, |
| { |
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| 0.01, |
| 0.0230506, |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.0230506, |
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| ] |
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| "when": "(GATE&!SCE)" |
| }, |
| { |
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| 0.01, |
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| "related_pin": "CLK", |
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| }, |
| { |
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| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
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| "clock_gate_test_pin": "true", |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
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| }, |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
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| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
