| { |
| "area": 20.0192, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002661, |
| "internal_power": { |
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| 0.01, |
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| 0.629961, |
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| }, |
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| "related_power_pin": "VPWR", |
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| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| "fall_capacitance": 0.001378, |
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| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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| 5.0 |
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| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
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| "timing_type": "hold_rising", |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
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| { |
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| { |
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| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "sdf_cond": "GATE==1'b1&&SCE==1'b1", |
| "timing_sense": "positive_unate", |
| "timing_type": "combinational", |
| "when": "(GATE&SCE)" |
| }, |
| { |
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| ] |
| }, |
| "fall_transition,del_1_7_7": { |
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| 0.01, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "sdf_cond": "GATE==1'b0&&SCE==1'b0", |
| "timing_sense": "positive_unate", |
| "timing_type": "combinational_fall", |
| "when": "(!GATE&!SCE)" |
| } |
| ] |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,SCE": { |
| "capacitance": 0.001496, |
| "clock": "false", |
| "clock_gate_test_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001423, |
| "internal_power": { |
| "fall_power,power_inputs_1": { |
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| 0.01, |
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| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0281727, |
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| 0.629961, |
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| 4.9999998 |
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| 0.004404, |
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| 0.0075995 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001569, |
| "timing": [ |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "values": [ |
| [ |
| 2.5215313, |
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| ], |
| [ |
| 1.3604961, |
| 2.581956, |
| 3.8063213 |
| ], |
| [ |
| 0.4455791, |
| 1.6560528, |
| 2.8730938 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "values": [ |
| [ |
| 0.47075, |
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| 2.4954326 |
| ], |
| [ |
| -0.3881611, |
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| ], |
| [ |
| -0.9771504, |
| 0.0813457, |
| 1.0127422 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "values": [ |
| [ |
| -2.5083759, |
| -3.7316672, |
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| ], |
| [ |
| -1.3619893, |
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| ], |
| [ |
| -0.437917, |
| -1.6502217, |
| -2.8672626 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
| 0.01, |
| 2.5, |
| 5.0 |
| ], |
| "values": [ |
| [ |
| -0.2635029, |
| -1.3311543, |
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| ], |
| [ |
| 0.4800518, |
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| ], |
| [ |
| 1.0653789, |
| 0.014207, |
| -0.8988789 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
