| { |
| "area": 20.0192, |
| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.005236554, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "leakage_power": [ |
| { |
| "value": 0.0020809, |
| "when": "CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0024621, |
| "when": "!CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0015087, |
| "when": "!CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0030453, |
| "when": "CLK&!GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0024576, |
| "when": "!CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0319662, |
| "when": "!CLK&!GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0039983, |
| "when": "CLK&GATE&GCLK&!SCE" |
| }, |
| { |
| "value": 0.0039978, |
| "when": "CLK&GATE&GCLK&SCE" |
| }, |
| { |
| "value": 0.0030072, |
| "when": "CLK&GATE&!GCLK&!SCE" |
| }, |
| { |
| "value": 0.0020531, |
| "when": "CLK&!GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.003005, |
| "when": "CLK&GATE&!GCLK&SCE" |
| }, |
| { |
| "value": 0.0032565, |
| "when": "CLK&!GATE&GCLK&!SCE" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.003558, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003355, |
| "internal_power": { |
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| "index_1": [ |
| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
| 1.5 |
| ], |
| "values": [ |
| 0.0159581, |
| 0.0159075, |
| 0.0157909, |
| 0.0158048, |
| 0.0158366, |
| 0.0159101, |
| 0.0160795 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| "values": [ |
| 0.0070792, |
| 0.0070139, |
| 0.0068633, |
| 0.0068489, |
| 0.0068158, |
| 0.0067395, |
| 0.0065635 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.003816, |
| "timing": { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| 0.2053223, |
| 0.627, |
| 1.877 |
| ] |
| }, |
| "related_pin": "CLK", |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| }, |
| "pin,GATE": { |
| "capacitance": 0.001889, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001713, |
| "internal_power": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0195013, |
| 0.0195423, |
| 0.0196368, |
| 0.0198547, |
| 0.0203569 |
| ] |
| }, |
| "rise_power,power_inputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0123974, |
| 0.0123838, |
| 0.0123525, |
| 0.0123186, |
| 0.0122404, |
| 0.01206, |
| 0.0116444 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002066, |
| "timing": [ |
| { |
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| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| 0.1875469, |
| 0.3549297, |
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| [ |
| 0.1227031, |
| 0.2888652, |
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| ], |
| [ |
| 0.0897441, |
| 0.2559063, |
| 0.5671856 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
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| ], |
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| 0.0850078, |
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| [ |
| 0.0323711, |
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| [ |
| 0.0677715, |
| 0.1545879, |
| 0.2119609 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
| "index_1": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "values": [ |
| [ |
| -0.1811055, |
| -0.3448262, |
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| ], |
| [ |
| -0.1187031, |
| -0.2860859, |
| -0.5985859 |
| ], |
| [ |
| -0.0857441, |
| -0.2519063, |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.5, |
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| "values": [ |
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| -0.0395039, |
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| [ |
| -0.0076191, |
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| [ |
| -0.0173848, |
| -0.0993184, |
| -0.1493672 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": [ |
| { |
| "fall_power,power_outputs_1": { |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
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| 0.01751821, |
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| 0.0063619, |
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| 0.003969, |
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| [ |
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| [ |
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| [ |
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| [ |
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| "related_pin": "CLK", |
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| "when": "(!GATE&SCE)" |
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| { |
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| "related_pin": "CLK", |
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| }, |
| { |
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| "related_pin": "CLK", |
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| }, |
| { |
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| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
