|  | { | 
|  | "description": "2-input AND into both inputs of 2-input OR.", | 
|  | "equation": "X = ((A1 & A2) | (B1 & B2))", | 
|  | "file_prefix": "sky130_fd_sc_hdll__a22o", | 
|  | "library": "sky130_fd_sc_hdll", | 
|  | "name": "a22o", | 
|  | "parameters": [], | 
|  | "ports": [ | 
|  | [ | 
|  | "signal", | 
|  | "X", | 
|  | "output", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "A1", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "A2", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "B1", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "B2", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VPWR", | 
|  | "input", | 
|  | "supply1" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VGND", | 
|  | "input", | 
|  | "supply0" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VPB", | 
|  | "input", | 
|  | "supply1" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VNB", | 
|  | "input", | 
|  | "supply0" | 
|  | ] | 
|  | ], | 
|  | "type": "cell", | 
|  | "verilog_name": "sky130_fd_sc_hdll__a22o" | 
|  | } |