| { |
| "description": "D-latch, gated clear direct / gate active high (Q output UDP)", |
| "file_prefix": "sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n", |
| "library": "sky130_fd_sc_hdll", |
| "name": "udp_dlatch$PR_pp$PG$N", |
| "parameters": [], |
| "ports": [ |
| [ |
| "signal", |
| "Q", |
| "output", |
| "" |
| ], |
| [ |
| "signal", |
| "D", |
| "input", |
| "" |
| ], |
| [ |
| "signal", |
| "GATE", |
| "input", |
| "" |
| ], |
| [ |
| "signal", |
| "RESET", |
| "input", |
| "" |
| ], |
| [ |
| "signal", |
| "NOTIFIER", |
| "input", |
| "" |
| ], |
| [ |
| "power", |
| "VPWR", |
| "input", |
| "supply1" |
| ], |
| [ |
| "power", |
| "VGND", |
| "input", |
| "supply0" |
| ] |
| ], |
| "type": "primitive", |
| "verilog_name": "sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N" |
| } |