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| "cell_footprint": "inv", |
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| { |
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| } |
| ], |
| "pg_pin VGND": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
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| }, |
| "pg_pin VPWR": { |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VPWR" |
| }, |
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| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004229 |
| }, |
| "pin Y": { |
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