| { | |
| "area": 12.512, | |
| "cell_footprint": "and4", | |
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| "value": 0.0104574, | |
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| }, | |
| { | |
| "value": 0.0104584, | |
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| }, | |
| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| }, | |
| { | |
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| }, | |
| { | |
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| }, | |
| { | |
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| }, | |
| { | |
| "value": 0.0105955, | |
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| }, | |
| { | |
| "value": 0.0104981, | |
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| } | |
| ], | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "pwell", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "nwell", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VPWR" | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
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| "pin C": { | |
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| "rise_power power_inputs_1": { | |
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| "pin D": { | |
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| "fall_capacitance": 0.002213, | |
| "internal_power": { | |
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| "rise_power power_inputs_1": { | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
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| }, | |
| "pin X": { | |
| "direction": "output", | |
| "function": "(A&B&C&D)", | |
| "internal_power": [ | |
| { | |
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| }, | |
| "related_pin": "A", | |
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| "when": "(B&C&D)" | |
| }, | |
| { | |
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| "related_pin": "B", | |
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| "when": "(A&C&D)" | |
| }, | |
| { | |
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| "related_pin": "C", | |
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