{ | |
"area": 12.512, | |
"cell_footprint": "and3", | |
"cell_leakage_power": 0.01046814, | |
"leakage_power": [ | |
{ | |
"value": 0.0104546, | |
"when": "!A&!B&C" | |
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{ | |
"value": 0.0104541, | |
"when": "!A&!B&!C" | |
}, | |
{ | |
"value": 0.0104761, | |
"when": "!A&B&C" | |
}, | |
{ | |
"value": 0.0127249, | |
"when": "!A&B&!C" | |
}, | |
{ | |
"value": 0.0107108, | |
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{ | |
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{ | |
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}, | |
{ | |
"value": 0.0104869, | |
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], | |
"pg_pin VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin VNB": { | |
"pg_type": "pwell", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin VPB": { | |
"pg_type": "nwell", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VPWR" | |
}, | |
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"capacitance": 0.002505, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.002379, | |
"internal_power": { | |
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0.0230506, | |
0.0531329, | |
0.122474, | |
0.282311, | |
0.650743, | |
1.5 | |
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0.0062164, | |
0.006043, | |
0.0060519, | |
0.0060723, | |
0.0061194, | |
0.006228 | |
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0.0230506, | |
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"pin B": { | |
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"clock": "false", | |
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"pin C": { | |
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"clock": "false", | |
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0.0230506, | |
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0.0051296, | |
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0.0051546, | |
0.0051947 | |
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0.0230506, | |
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"rise_capacitance": 0.002643 | |
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"pin X": { | |
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"function": "(A&B&C)", | |
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0.01561294, | |
0.04916504, | |
0.1548203, | |
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0.0125286, | |
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[ | |
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[ | |
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0.9448962 | |
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[ | |
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[ | |
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[ | |
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0.3300277, | |
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[ | |
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[ | |
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0.0230506, | |
0.0531329, | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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"power_down_function": "(!VPWR + VGND)", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"timing": [ | |
{ | |
"ccsn_first_stage": { | |
"dc_current ccsn_dc": { | |
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