| { | |
| "area": 22.5216, | |
| "cell_footprint": "a211oi", | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| }, | |
| { | |
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| { | |
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| { | |
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| ], | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "pwell", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "nwell", | |
| "voltage_name": "VPB" | |
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| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
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| "voltage_name": "VPWR" | |
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| "rise_power power_inputs_1": { | |
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| "related_power_pin": "VPWR", | |
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| "pin C1": { | |
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| "fall_capacitance": 0.007534, | |
| "internal_power": { | |
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| 0.0531329, | |
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| "rise_power power_inputs_1": { | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.009082 | |
| }, | |
| "pin Y": { | |
| "direction": "output", | |
| "function": "(!A1&!B1&!C1) | (!A2&!B1&!C1)", | |
| "internal_power": [ | |
| { | |
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| "related_pin": "A1", | |
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| "when": "(A2&!B1&!C1)" | |
| }, | |
| { | |
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| "related_pin": "A2", | |
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| }, | |
| "when": "(A1&!B1&!C1)" | |
| }, | |
| { | |
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| "related_pin": "B1", | |
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