cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_2__ff_n40C_1v56.lib.json

{
  "area": 40.0384,
  "cell_footprint": "sdfrbp",
  "cell_leakage_power": 0.0,
  "ff IQ,IQ_N": {
    "clear": "!RESET_B",
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002377,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002051,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
          0.01,
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002423,
    "timing": {
      "fall_constraint constraint_3_0_1": {
        "index_1": [
          0.01,
          0.5,
          1.5
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        "values": [
          0.347516,
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      "related_pin": "CLK",
      "rise_constraint constraint_3_0_1": {
        "index_1": [
          0.01,
          0.5,
          1.5
        ],
        "values": [
          0.1212228,
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      },
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
    }
  },
  "pin D": {
    "capacitance": 0.001616,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001533,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
          0.01,
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          0.282311,
          0.650743,
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        "values": [
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      "rise_power power_inputs_1": {
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    },
    "max_transition": 1.5,
    "nextstate_type": "data",
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    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001698,
    "timing": [
      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
            0.01,
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          "index_2": [
            0.01,
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          "values": [
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              0.4011699,
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              0.3143535,
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        "related_pin": "CLK",
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          "index_1": [
            0.01,
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          "index_2": [
            0.01,
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              0.1228496,
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              0.0763164,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10.0
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      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
            0.01,
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              -0.1896504,
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              -0.1650898,
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              -0.1394551,
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        "related_pin": "CLK",
        "rise_constraint vio_3_3_1": {
          "index_1": [
            0.01,
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          "index_2": [
            0.01,
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          "values": [
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              -0.0688008,
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
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      {
        "fall_power power_outputs_1": {
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          ]
        },
        "related_pin": "RESET_B",
        "rise_power scalar": {
          "values": [
            0.0
          ]
        },
        "when": "(!CLK&!D&!SCD&!SCE)"
      },
      {
        "fall_power power_outputs_1": {
          "index_1": [
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        "related_pin": "RESET_B",
        "rise_power scalar": {
          "values": [
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        "when": "(!CLK&!D&!SCD&SCE)"
      },
      {
        "fall_power power_outputs_1": {
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        "related_pin": "RESET_B",
        "rise_power scalar": {
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        "when": "(!CLK&!D&SCD&!SCE)"
      },
      {
        "fall_power power_outputs_1": {
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        "related_pin": "RESET_B",
        "rise_power scalar": {
          "values": [
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        "when": "(CLK&D&SCD&!SCE)"
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      {
        "fall_power power_outputs_1": {
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        "related_pin": "RESET_B",
        "rise_power scalar": {
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        "when": "(CLK&D&SCD&SCE)"
      },
      {
        "fall_power scalar": {
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        "related_pin": "CLK",
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      {
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        "related_pin": "CLK",
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      {
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        "related_pin": "CLK",
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        "rise_power scalar": {
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        "when": "(CLK&D&!SCD&SCE)"
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            0.0531329,
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        "sdf_cond": "D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0",
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