| { | |
| "area": 18.768, | |
| "cell_footprint": "a22o", | |
| "cell_leakage_power": 0.0, | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "pwell", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "nwell", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin A1": { | |
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| "clock": "false", | |
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| "fall_capacitance": 0.004011, | |
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| "rise_power power_inputs_1": { | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.004426 | |
| }, | |
| "pin A2": { | |
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| "rise_power power_inputs_1": { | |
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| "rise_power power_inputs_1": { | |
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| }, | |
| "pin B2": { | |
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| "fall_capacitance": 0.004395, | |
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| "rise_power power_inputs_1": { | |
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| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.005094 | |
| }, | |
| "pin X": { | |
| "direction": "output", | |
| "function": "(B1&B2) | (A1&A2)", | |
| "internal_power": [ | |
| { | |
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| "related_pin": "A1", | |
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| "when": "(A2&!B1&!B2)" | |
| }, | |
| { | |
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| { | |
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