verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
tree: e3d5d3b4a8718051e3352a2ff9333a7aae290d1d
  1. .gitignore
  2. LICENSE
  3. README.rst
  4. cells/
  5. models/
  6. tech/
  7. timing/