| commit | 1dc32e3940b584a6ef4356aa7c4131920d991bf3 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | e3d5d3b4a8718051e3352a2ff9333a7aae290d1d | |
| parent | 75bfa306ef943736f52bb1c2be997517fe110068 [diff] | |
| parent | 0934c6ec44836066ab74669eac995ff803ddb819 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>