tree e3d5d3b4a8718051e3352a2ff9333a7aae290d1d
parent 75bfa306ef943736f52bb1c2be997517fe110068
parent 0934c6ec44836066ab74669eac995ff803ddb819
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>