commit | 0934c6ec44836066ab74669eac995ff803ddb819 | [log] [tgz] |
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author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | eced853281cfcf6ba28d1d3f1eba7013a9b4bd8f | |
parent | dba9671a44909083f9a5eabed74d20e5e6d7f5f5 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>