tree eced853281cfcf6ba28d1d3f1eba7013a9b4bd8f
parent dba9671a44909083f9a5eabed74d20e5e6d7f5f5
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>