| commit | 05d4cd52b636938bf1f2b6db61e995e3b71bb073 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | c2e2e8dbd6f0e35687b770039fb55776aded35d7 | |
| parent | 0934c6ec44836066ab74669eac995ff803ddb819 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>