)]}'
{
  "commit": "05d4cd52b636938bf1f2b6db61e995e3b71bb073",
  "tree": "c2e2e8dbd6f0e35687b770039fb55776aded35d7",
  "parents": [
    "0934c6ec44836066ab74669eac995ff803ddb819"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
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