| { | 
 |  "description": "2-input AND into first input of 2-input OR, 2nd input inverted.", | 
 |  "equation": "X = ((A1 & A2) | (!B1_N))", | 
 |  "file_prefix": "sky130_fd_sc_hdll__a21bo", | 
 |  "library": "sky130_fd_sc_hdll", | 
 |  "name": "a21bo", | 
 |  "parameters": [], | 
 |  "ports": [ | 
 |   [ | 
 |    "signal", | 
 |    "X", | 
 |    "output", | 
 |    "" | 
 |   ], | 
 |   [ | 
 |    "signal", | 
 |    "A1", | 
 |    "input", | 
 |    "" | 
 |   ], | 
 |   [ | 
 |    "signal", | 
 |    "A2", | 
 |    "input", | 
 |    "" | 
 |   ], | 
 |   [ | 
 |    "signal", | 
 |    "B1_N", | 
 |    "input", | 
 |    "" | 
 |   ], | 
 |   [ | 
 |    "power", | 
 |    "VPWR", | 
 |    "input", | 
 |    "supply1" | 
 |   ], | 
 |   [ | 
 |    "power", | 
 |    "VGND", | 
 |    "input", | 
 |    "supply0" | 
 |   ], | 
 |   [ | 
 |    "power", | 
 |    "VPB", | 
 |    "input", | 
 |    "supply1" | 
 |   ], | 
 |   [ | 
 |    "power", | 
 |    "VNB", | 
 |    "input", | 
 |    "supply0" | 
 |   ] | 
 |  ], | 
 |  "type": "cell", | 
 |  "verilog_name": "sky130_fd_sc_hdll__a21bo" | 
 | } |