| { |
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| "cell_footprint": "and3", |
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| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
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| { |
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| }, |
| { |
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| { |
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| { |
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| { |
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| { |
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| { |
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| { |
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| ], |
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| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
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| "voltage_name": "VPB" |
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| 0.0281727, |
| 0.0793701, |
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| }, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin X": { |
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| { |
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| }, |
| "related_pin": "A", |
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| { |
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| { |
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| "related_pin": "C", |
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| ], |
| "max_capacitance": 0.099192, |
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| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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