verilog: Fixing ordering of ports in primitives.
Verilog requires the first signal in a primitive's pin list must be the output.
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/README.rst b/README.rst
index 8d0e1b9..a7c2546 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,5 @@
:lib:`sky130_fd_sc_hd` - SKY130 High Density Digital Standard Cells (SkyWater Provided)
=======================================================================================
-Initial release of version (0, 0, 1).
+Initial release of version (0, 0, 2).
diff --git a/cells/diode/sky130_fd_sc_hd__diode_1.lef b/cells/diode/sky130_fd_sc_hd__diode_1.lef
deleted file mode 100644
index d9a9f88..0000000
--- a/cells/diode/sky130_fd_sc_hd__diode_1.lef
+++ /dev/null
@@ -1,64 +0,0 @@
-# Copyright 2020 The SkyWater PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-VERSION 5.5 ;
-NAMESCASESENSITIVE ON ;
-BUSBITCHARS "[]" ;
-DIVIDERCHAR "/" ;
-MACRO sky130_fd_sc_hd__diode_1
- CLASS CORE ;
- SOURCE USER ;
- ORIGIN 0.000000 0.000000 ;
- SIZE 1.380000 BY 2.720000 ;
- SYMMETRY X Y R90 ;
- SITE unit ;
- PIN DIODE
- ANTENNADIFFAREA 0.745200 ;
- DIRECTION INPUT ;
- USE SIGNAL ;
- PORT
- LAYER li1 ;
- RECT 0.085000 0.255000 1.295000 2.465000 ;
- END
- END DIODE
- PIN VGND
- SHAPE ABUTMENT ;
- USE GROUND ;
- PORT
- LAYER li1 ;
- RECT 0.000000 -0.085000 1.380000 0.085000 ;
- END
- PORT
- LAYER met1 ;
- RECT 0.000000 -0.240000 1.380000 0.240000 ;
- END
- END VGND
- PIN VPWR
- SHAPE ABUTMENT ;
- USE POWER ;
- PORT
- LAYER li1 ;
- RECT 0.000000 2.635000 1.380000 2.805000 ;
- END
- PORT
- LAYER met1 ;
- RECT 0.000000 2.480000 1.380000 2.960000 ;
- END
- END VPWR
- OBS
- END
-END sky130_fd_sc_hd__diode_1
-END LIBRARY
diff --git a/cells/diode/sky130_fd_sc_hd__diode_2.lef b/cells/diode/sky130_fd_sc_hd__diode_2.lef
index 0eca7f2..1ba2aee 100644
--- a/cells/diode/sky130_fd_sc_hd__diode_2.lef
+++ b/cells/diode/sky130_fd_sc_hd__diode_2.lef
@@ -26,7 +26,7 @@
SYMMETRY X Y R90 ;
SITE unithd ;
PIN DIODE
- ANTENNADIFFAREA 0.434700 ;
+ ANTENNAGATEAREA 0.000000 ;
DIRECTION INPUT ;
USE SIGNAL ;
PORT
