| commit | 01fde9a432bc54094b017239f87c9f0aeae82947 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | d49d8b1f2be4d01d5ff80001cebbddb43ea856c1 | |
| parent | 23c9281bdb9d2bbcc75a2efa0b8077ec9f77fca6 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>