commit | 23c9281bdb9d2bbcc75a2efa0b8077ec9f77fca6 | [log] [tgz] |
---|---|---|
author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | d207515c51b63a8026a39da5b4bfbe1a82b19fc1 | |
parent | fa8d392b63c607ce42af14683782276623890130 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>