| commit | 836b7fa01a1f7870ab44f6b59220b0ad7f6f0ebc | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 65c282c590bce98221ea7015e5b9360532b7d3ba | |
| parent | 9b8d061bb2dcdeaf367aacf4b592f6ca05df77df [diff] | |
| parent | 01fde9a432bc54094b017239f87c9f0aeae82947 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>