verilog: Fixing spurious `wire 1'b0` definition in lpflow_inputisolatch.

Fixes https://github.com/google/skywater-pdk/issues/178.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
Signed-off-by: Tim Edwards <tim@opencircuitdesign.com>
1 file changed
tree: e7a05f0be935d8c70db26ed08603f817c7d7f6e9
  1. .gitignore
  2. LICENSE
  3. README.rst
  4. cells/
  5. models/
  6. tech/
  7. timing/