| { | |
| "area": 11.2608, | |
| "cell_footprint": "sky130_fd_sc_hd__a32o", | |
| "cell_leakage_power": 0.01182075, | |
| "driver_waveform_fall": "ramp", | |
| "driver_waveform_rise": "ramp", | |
| "leakage_power": [ | |
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| "value": 0.0124749, | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| }, | |
| { | |
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| }, | |
| { | |
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| "when": "!A1&!A2&A3&B1&!B2" | |
| }, | |
| { | |
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| "when": "!A1&A2&!A3&!B1&B2" | |
| }, | |
| { | |
| "value": 0.0124393, | |
| "when": "!A1&A2&!A3&!B1&!B2" | |
| }, | |
| { | |
| "value": 0.0124632, | |
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| }, | |
| { | |
| "value": 0.0124701, | |
| "when": "!A1&A2&!A3&B1&!B2" | |
| }, | |
| { | |
| "value": 0.0125102, | |
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| }, | |
| { | |
| "value": 0.0124742, | |
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| }, | |
| { | |
| "value": 0.0124632, | |
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| }, | |
| { | |
| "value": 0.012505, | |
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| }, | |
| { | |
| "value": 0.0124817, | |
| "when": "A1&!A2&!A3&!B1&B2" | |
| }, | |
| { | |
| "value": 0.0124457, | |
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| }, | |
| { | |
| "value": 0.0124632, | |
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| { | |
| "value": 0.0124765, | |
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| }, | |
| { | |
| "value": 0.0125025, | |
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| }, | |
| { | |
| "value": 0.0124665, | |
| "when": "A1&!A2&A3&!B1&!B2" | |
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| { | |
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| { | |
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| }, | |
| { | |
| "value": 0.0125004, | |
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| { | |
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| { | |
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| { | |
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| { | |
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| }, | |
| { | |
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| { | |
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| }, | |
| { | |
| "value": 0.0077818, | |
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| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
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| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
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| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
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| "clock": "false", | |
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| "fall_capacitance": 0.002234, | |
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| 0.01, | |
| 0.0230506, | |
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| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002392 | |
| }, | |
| "pin,A2": { | |
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| "input_voltage": "GENERAL", | |
| "internal_power": { | |
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| "rise_power,power_inputs_1": { | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002453 | |
| }, | |
| "pin,A3": { | |
| "capacitance": 0.002304, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.002192, | |
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| "pin,B1": { | |
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| "fall_capacitance": 0.002243, | |
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| "internal_power": { | |
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| 0.0230506, | |
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| 0.0051934, | |
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| "rise_power,power_inputs_1": { | |
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| "values": [ | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002481 | |
| }, | |
| "pin,B2": { | |
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| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.002373, | |
| "input_voltage": "GENERAL", | |
| "internal_power": { | |
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| 0.01, | |
| 0.0230506, | |
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| 0.0050019 | |
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| }, | |
| "rise_power,power_inputs_1": { | |
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| 0.01, | |
| 0.0230506, | |
| 0.0531329, | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002705 | |
| }, | |
| "pin,X": { | |
| "direction": "output", | |
| "function": "(A1&A2&A3) | (B1&B2)", | |
| "internal_power": [ | |
| { | |
| "fall_power,power_outputs_1": { | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "related_pin": "A1", | |
| "rise_power,power_outputs_1": { | |
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| 0.02305058, | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| } | |
| }, | |
| { | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "related_pin": "A2", | |
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| [ | |
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