Fixes ReRAM Verilog-A model naming convention.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.gds b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.gds
index 361affc..937cd45 100644
--- a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.gds
+++ b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.gds
Binary files differ
diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.magic.lef b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.magic.lef
index 8caa2be..66c5b6d 100644
--- a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.magic.lef
+++ b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.magic.lef
@@ -21,7 +21,21 @@
MACRO sky130_fd_pr_reram__reram_cell
CLASS BLOCK ;
FOREIGN sky130_fd_pr_reram__reram_cell ;
- ORIGIN 0.000000 0.000000 ;
- SIZE 0.005000 BY 0.005000 ;
+ ORIGIN 0.160000 0.160000 ;
+ SIZE 0.320000 BY 0.320000 ;
+ PIN BE
+ PORT
+ LAYER met2 ;
+ RECT -0.130000 -0.160000 0.130000 0.160000 ;
+ END
+ END BE
+ PIN TE
+ PORT
+ LAYER met1 ;
+ RECT -0.160000 -0.130000 0.160000 0.130000 ;
+ LAYER via ;
+ RECT -0.130000 -0.130000 0.130000 0.130000 ;
+ END
+ END TE
END sky130_fd_pr_reram__reram_cell
END LIBRARY
diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.spice b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.spice
index 1c14ba0..7732452 100644
--- a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.spice
+++ b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.spice
@@ -15,5 +15,6 @@
* SPDX-License-Identifier: Apache-2.0
-* Top level circuit sky130_fd_pr_reram__reram_cell
-.end
+.subckt sky130_fd_pr_reram__reram_cell BE TE
+R0 BE TE 0.000000
+.ends
diff --git a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.svg b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.svg
index 3b59353..c346974 100644
--- a/cells/reram_cell/sky130_fd_pr_reram__reram_cell.svg
+++ b/cells/reram_cell/sky130_fd_pr_reram__reram_cell.svg
@@ -5,13 +5,14 @@
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