cleaned history
diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md
new file mode 100644
index 0000000..3c52212
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE.md
@@ -0,0 +1,16 @@
+## Expected Behavior
+
+
+## Actual Behavior
+
+
+## Steps to Reproduce the Problem
+
+1.
+1.
+1.
+
+## Specifications
+
+- Version:
+- Platform:
\ No newline at end of file
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
new file mode 100644
index 0000000..0787bd9
--- /dev/null
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,6 @@
+Fixes #<issue_number_goes_here>
+
+> It's a good idea to open an issue first for discussion.
+
+- [ ] Tests pass
+- [ ] Appropriate changes to README are included in PR
\ No newline at end of file
diff --git a/.github/workflows/checks.yml b/.github/workflows/checks.yml
new file mode 100644
index 0000000..dc8ed4d
--- /dev/null
+++ b/.github/workflows/checks.yml
@@ -0,0 +1,36 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+name: Checks
+
+
+on:
+ push:
+ pull_request:
+
+
+jobs:
+ Run:
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v2
+
+ - uses: SymbiFlow/actions/checks@main
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..adc72b7
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,20 @@
+# Misc files
+*~
+workplace_setup/tutorial_files/*
+
+# Python files
+#
+*.pyc
+__pycache__
+
+# Virtuoso files
+*.cdslck
+*.cdslck.*
+
+# Pycharm related files
+.idea/workspace.xml
+.idea/usage.statistics.xml
+.idea/tasks.xml
+
+# Jupyter files
+.ipynb_checkpoints
diff --git a/.idea/inspectionProfiles/profiles_settings.xml b/.idea/inspectionProfiles/profiles_settings.xml
new file mode 100644
index 0000000..12512d6
--- /dev/null
+++ b/.idea/inspectionProfiles/profiles_settings.xml
@@ -0,0 +1,27 @@
+<!--
+Copyright 2019-2021 SkyWater PDK Authors
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ https://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+This code is *alternatively* available under a BSD-3-Clause license, see
+details in the README.md at the top level and the license text at
+https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+
+SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+-->
+<component name="InspectionProjectProfileManager">
+ <settings>
+ <option name="USE_PROJECT_PROFILE" value="false" />
+ <version value="1.0" />
+ </settings>
+</component>
diff --git a/.idea/misc.xml b/.idea/misc.xml
new file mode 100644
index 0000000..a6af5f0
--- /dev/null
+++ b/.idea/misc.xml
@@ -0,0 +1,28 @@
+<!--
+Copyright 2019-2021 SkyWater PDK Authors
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ https://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+This code is *alternatively* available under a BSD-3-Clause license, see
+details in the README.md at the top level and the license text at
+https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+
+SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+-->
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+ <component name="PreferredVcsStorage">
+ <preferredVcsName>ApexVCS</preferredVcsName>
+ </component>
+ <component name="ProjectRootManager" version="2" project-jdk-name="Python 3.7" project-jdk-type="Python SDK" />
+</project>
diff --git a/.idea/modules.xml b/.idea/modules.xml
new file mode 100644
index 0000000..62d06a9
--- /dev/null
+++ b/.idea/modules.xml
@@ -0,0 +1,29 @@
+<!--
+Copyright 2019-2021 SkyWater PDK Authors
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ https://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+This code is *alternatively* available under a BSD-3-Clause license, see
+details in the README.md at the top level and the license text at
+https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+
+SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+-->
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+ <component name="ProjectModuleManager">
+ <modules>
+ <module fileurl="file://$PROJECT_DIR$/.idea/skywater130.iml" filepath="$PROJECT_DIR$/.idea/skywater130.iml" />
+ </modules>
+ </component>
+</project>
diff --git a/.idea/skywater130.iml b/.idea/skywater130.iml
new file mode 100644
index 0000000..d01cb2b
--- /dev/null
+++ b/.idea/skywater130.iml
@@ -0,0 +1,34 @@
+<!--
+Copyright 2019-2021 SkyWater PDK Authors
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ https://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+This code is *alternatively* available under a BSD-3-Clause license, see
+details in the README.md at the top level and the license text at
+https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+
+SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+-->
+<?xml version="1.0" encoding="UTF-8"?>
+<module type="PYTHON_MODULE" version="4">
+ <component name="NewModuleRootManager">
+ <content url="file://$MODULE_DIR$">
+ <sourceFolder url="file://$MODULE_DIR$/src" isTestSource="false" />
+ <excludeFolder url="file://$MODULE_DIR$/OA" />
+ </content>
+ <orderEntry type="inheritedJdk" />
+ <orderEntry type="sourceFolder" forTests="false" />
+ <orderEntry type="module" module-name="BAG_framework" />
+ <orderEntry type="module" module-name="xbase" />
+ </component>
+</module>
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
new file mode 100644
index 0000000..ecacb98
--- /dev/null
+++ b/.idea/vcs.xml
@@ -0,0 +1,27 @@
+<!--
+Copyright 2019-2021 SkyWater PDK Authors
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ https://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+This code is *alternatively* available under a BSD-3-Clause license, see
+details in the README.md at the top level and the license text at
+https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+
+SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+-->
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+ <component name="VcsDirectoryMappings">
+ <mapping directory="$PROJECT_DIR$" vcs="Git" />
+ </component>
+</project>
\ No newline at end of file
diff --git a/AUTHORS b/AUTHORS
new file mode 100644
index 0000000..23dbfa3
--- /dev/null
+++ b/AUTHORS
@@ -0,0 +1,23 @@
+# This is the list of significant contributors.
+#
+# This does **not** necessarily list everyone who has contributed code,
+# especially since many employees of one corporation may be contributing.
+# To see the full list of contributors, see the revision history in
+# source control.
+
+# Companies
+Google LLC (google.com)
+BlueCheetah Analog (bcanalog.com)
+SkyWater Technology Foundry (skywatertechnology.com)
+efabless corporation (efabless.com)
+
+# Individuals
+tansell@google.com, me@mith.ro (Tim 'mithro' Ansell)
+pgron@google.com (Per Grön)
+ethanmoon@google.com (Per Grön)
+kevin.kelley@skywatertechnology.com, kevin.kelly@skywater.tools (Kevin Kelley)
+ayan@bcanalog.com (Ayan Biswas)
+elad@bcanalog.com (Elad Alon)
+eric@bcanalog.com, pkerichang@gmail.com (Eric Chang)
+krishna@bcanalog.com (Krishna Settaluri)
+nathan@bcanalog.com (Nathan Narevsky)
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..d645695
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,202 @@
+
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
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+ "Licensor" shall mean the copyright owner or entity authorized by
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+ "Legal Entity" shall mean the union of the acting entity and all
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+ "Work" shall mean the work of authorship, whether in Source or
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+ "Derivative Works" shall mean any work, whether in Source or Object
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+ "Contribution" shall mean any work of authorship, including
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+ "Contributor" shall mean Licensor and any individual or Legal Entity
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+ 2. Grant of Copyright License. Subject to the terms and conditions of
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+ for use, reproduction, or distribution of Your modifications, or
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+ reproduction, and distribution of the Work otherwise complies with
+ the conditions stated in this License.
+
+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
+ by You to the Licensor shall be under the terms and conditions of
+ this License, without any additional terms or conditions.
+ Notwithstanding the above, nothing herein shall supersede or modify
+ the terms of any separate license agreement you may have executed
+ with Licensor regarding such Contributions.
+
+ 6. Trademarks. This License does not grant permission to use the trade
+ names, trademarks, service marks, or product names of the Licensor,
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+
+ 7. Disclaimer of Warranty. Unless required by applicable law or
+ agreed to in writing, Licensor provides the Work (and each
+ Contributor provides its Contributions) on an "AS IS" BASIS,
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+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
+ unless required by applicable law (such as deliberate and grossly
+ negligent acts) or agreed to in writing, shall any Contributor be
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+ 9. Accepting Warranty or Additional Liability. While redistributing
+ the Work or Derivative Works thereof, You may choose to offer,
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+ on Your own behalf and on Your sole responsibility, not on behalf
+ of any other Contributor, and only if You agree to indemnify,
+ defend, and hold each Contributor harmless for any liability
+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
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+ END OF TERMS AND CONDITIONS
+
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
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+ same "printed page" as the copyright notice for easier
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+
+ Copyright [yyyy] [name of copyright owner]
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/LICENSE.alternative b/LICENSE.alternative
new file mode 100644
index 0000000..fdddfd1
--- /dev/null
+++ b/LICENSE.alternative
@@ -0,0 +1,27 @@
+Copyright 2020-2021 Google LLC
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+ * Neither the name of Google LLC nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/OA/BAG_prim/.oalib b/OA/BAG_prim/.oalib
new file mode 100644
index 0000000..21ffef8
--- /dev/null
+++ b/OA/BAG_prim/.oalib
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+
+<Library DMSystem="oaDMFileSys">
+ <oaDMFileSys libReadOnly="No"
+ origFileSystem="Unix"/>
+</Library>
diff --git a/OA/BAG_prim/cdsinfo.tag b/OA/BAG_prim/cdsinfo.tag
new file mode 100644
index 0000000..b75aa95
--- /dev/null
+++ b/OA/BAG_prim/cdsinfo.tag
@@ -0,0 +1,41 @@
+#
+# This is a cdsinfo.tag file.
+#
+# See the "Cadence Application Infrastructure Reference Manual" for
+# details on the format of this file, its semantics, and its use.
+#
+# The `#' character denotes a comment. Removing the leading `#'
+# character from any of the entries below will activate them.
+#
+# CDSLIBRARY entry - add this entry if the directory containing
+# this cdsinfo.tag file is the root of a Cadence library.
+# CDSLIBRARY
+#
+# CDSLIBCHECK - set this entry to require that libraries have
+# a cdsinfo.tag file with a CDSLIBRARY entry. Legal values are
+# ON and OFF. By default (OFF), directories named in a cds.lib file
+# do not have to have a cdsinfo.tag file with a CDSLIBRARY entry.
+# CDSLIBCHECK ON
+#
+# DMTYPE - set this entry to define the DM system for Cadence's
+# Generic DM facility. Values will be shifted to lower case.
+# DMTYPE none
+# DMTYPE crcs
+# DMTYPE tdm
+# DMTYPE sync
+#
+# NAMESPACE - set this entry to define the library namespace according
+# to the type of machine on which the data is stored. Legal values are
+# `LibraryNT' and
+# `LibraryUnix'.
+# NAMESPACE LibraryUnix
+#
+# Other entries may be added for use by specific applications as
+# name-value pairs. Application documentation will describe the
+# use and behaviour of these entries when appropriate.
+#
+# Current Settings:
+#
+CDSLIBRARY
+DMTYPE none
+NAMESPACE LibraryUnix
diff --git a/OA/BAG_prim/data.dm b/OA/BAG_prim/data.dm
new file mode 100644
index 0000000..a066651
--- /dev/null
+++ b/OA/BAG_prim/data.dm
Binary files differ
diff --git a/OA/BAG_prim/mim_34/data.dm b/OA/BAG_prim/mim_34/data.dm
new file mode 100644
index 0000000..8c3f4b4
--- /dev/null
+++ b/OA/BAG_prim/mim_34/data.dm
Binary files differ
diff --git a/OA/BAG_prim/mim_34/schematic/data.dm b/OA/BAG_prim/mim_34/schematic/data.dm
new file mode 100644
index 0000000..33100b8
--- /dev/null
+++ b/OA/BAG_prim/mim_34/schematic/data.dm
Binary files differ
diff --git a/OA/BAG_prim/mim_34/schematic/master.tag b/OA/BAG_prim/mim_34/schematic/master.tag
new file mode 100644
index 0000000..26be1be
--- /dev/null
+++ b/OA/BAG_prim/mim_34/schematic/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0
+sch.oa
diff --git a/OA/BAG_prim/mim_34/schematic/sch.oa b/OA/BAG_prim/mim_34/schematic/sch.oa
new file mode 100644
index 0000000..01c74a5
--- /dev/null
+++ b/OA/BAG_prim/mim_34/schematic/sch.oa
Binary files differ
diff --git a/OA/BAG_prim/mim_34/schematic/thumbnail_128x128.png b/OA/BAG_prim/mim_34/schematic/thumbnail_128x128.png
new file mode 100644
index 0000000..8383fce
--- /dev/null
+++ b/OA/BAG_prim/mim_34/schematic/thumbnail_128x128.png
Binary files differ
diff --git a/OA/BAG_prim/mim_34/symbol/data.dm b/OA/BAG_prim/mim_34/symbol/data.dm
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/OA/BAG_prim/mim_34/symbol/data.dm
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+++ b/OA/BAG_prim/res_metal_4/schematic/sch.oa
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diff --git a/OA/BAG_prim/res_metal_4/schematic/thumbnail_128x128.png b/OA/BAG_prim/res_metal_4/schematic/thumbnail_128x128.png
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+++ b/OA/BAG_prim/res_metal_4/schematic/thumbnail_128x128.png
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diff --git a/OA/BAG_prim/res_metal_4/symbol/data.dm b/OA/BAG_prim/res_metal_4/symbol/data.dm
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/OA/BAG_prim/res_metal_4/symbol/data.dm
diff --git a/OA/BAG_prim/res_metal_4/symbol/master.tag b/OA/BAG_prim/res_metal_4/symbol/master.tag
new file mode 100644
index 0000000..e1024da
--- /dev/null
+++ b/OA/BAG_prim/res_metal_4/symbol/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0
+symbol.oa
diff --git a/OA/BAG_prim/res_metal_4/symbol/symbol.oa b/OA/BAG_prim/res_metal_4/symbol/symbol.oa
new file mode 100644
index 0000000..a07d714
--- /dev/null
+++ b/OA/BAG_prim/res_metal_4/symbol/symbol.oa
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diff --git a/OA/BAG_prim/res_metal_4/symbol/thumbnail_128x128.png b/OA/BAG_prim/res_metal_4/symbol/thumbnail_128x128.png
new file mode 100644
index 0000000..adc228c
--- /dev/null
+++ b/OA/BAG_prim/res_metal_4/symbol/thumbnail_128x128.png
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diff --git a/OA/BAG_prim/res_metal_5/data.dm b/OA/BAG_prim/res_metal_5/data.dm
new file mode 100644
index 0000000..15812be
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/data.dm
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diff --git a/OA/BAG_prim/res_metal_5/schematic/data.dm b/OA/BAG_prim/res_metal_5/schematic/data.dm
new file mode 100644
index 0000000..b131bb5
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/schematic/data.dm
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diff --git a/OA/BAG_prim/res_metal_5/schematic/master.tag b/OA/BAG_prim/res_metal_5/schematic/master.tag
new file mode 100644
index 0000000..26be1be
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/schematic/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0
+sch.oa
diff --git a/OA/BAG_prim/res_metal_5/schematic/sch.oa b/OA/BAG_prim/res_metal_5/schematic/sch.oa
new file mode 100644
index 0000000..49578ff
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/schematic/sch.oa
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diff --git a/OA/BAG_prim/res_metal_5/schematic/thumbnail_128x128.png b/OA/BAG_prim/res_metal_5/schematic/thumbnail_128x128.png
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--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/schematic/thumbnail_128x128.png
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diff --git a/OA/BAG_prim/res_metal_5/symbol/data.dm b/OA/BAG_prim/res_metal_5/symbol/data.dm
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/symbol/data.dm
diff --git a/OA/BAG_prim/res_metal_5/symbol/master.tag b/OA/BAG_prim/res_metal_5/symbol/master.tag
new file mode 100644
index 0000000..e1024da
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/symbol/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0
+symbol.oa
diff --git a/OA/BAG_prim/res_metal_5/symbol/symbol.oa b/OA/BAG_prim/res_metal_5/symbol/symbol.oa
new file mode 100644
index 0000000..02f3711
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/symbol/symbol.oa
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diff --git a/OA/BAG_prim/res_metal_5/symbol/thumbnail_128x128.png b/OA/BAG_prim/res_metal_5/symbol/thumbnail_128x128.png
new file mode 100644
index 0000000..adc228c
--- /dev/null
+++ b/OA/BAG_prim/res_metal_5/symbol/thumbnail_128x128.png
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diff --git a/OA/BAG_prim/res_standard/data.dm b/OA/BAG_prim/res_standard/data.dm
new file mode 100644
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--- /dev/null
+++ b/OA/BAG_prim/res_standard/data.dm
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diff --git a/OA/BAG_prim/res_standard/schematic/data.dm b/OA/BAG_prim/res_standard/schematic/data.dm
new file mode 100644
index 0000000..9c7fdb9
--- /dev/null
+++ b/OA/BAG_prim/res_standard/schematic/data.dm
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diff --git a/OA/BAG_prim/res_standard/schematic/master.tag b/OA/BAG_prim/res_standard/schematic/master.tag
new file mode 100644
index 0000000..26be1be
--- /dev/null
+++ b/OA/BAG_prim/res_standard/schematic/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0
+sch.oa
diff --git a/OA/BAG_prim/res_standard/schematic/sch.oa b/OA/BAG_prim/res_standard/schematic/sch.oa
new file mode 100644
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--- /dev/null
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--- /dev/null
+++ b/OA/BAG_prim/res_standard/schematic/thumbnail_128x128.png
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diff --git a/OA/BAG_prim/res_standard/symbol/data.dm b/OA/BAG_prim/res_standard/symbol/data.dm
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/OA/BAG_prim/res_standard/symbol/data.dm
diff --git a/OA/BAG_prim/res_standard/symbol/master.tag b/OA/BAG_prim/res_standard/symbol/master.tag
new file mode 100644
index 0000000..e1024da
--- /dev/null
+++ b/OA/BAG_prim/res_standard/symbol/master.tag
@@ -0,0 +1,2 @@
+-- Master.tag File, Rev:1.0
+symbol.oa
diff --git a/OA/BAG_prim/res_standard/symbol/symbol.oa b/OA/BAG_prim/res_standard/symbol/symbol.oa
new file mode 100644
index 0000000..40c5f01
--- /dev/null
+++ b/OA/BAG_prim/res_standard/symbol/symbol.oa
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diff --git a/OA/BAG_prim/res_standard/symbol/thumbnail_128x128.png b/OA/BAG_prim/res_standard/symbol/thumbnail_128x128.png
new file mode 100644
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--- /dev/null
+++ b/OA/BAG_prim/res_standard/symbol/thumbnail_128x128.png
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diff --git a/README.md b/README.md
new file mode 100644
index 0000000..f5c88a8
--- /dev/null
+++ b/README.md
@@ -0,0 +1,66 @@
+# skywater130
+
+Skywater130 primitives for [BAG](https://github.com/ucb-art/bag).
+
+These primitives are updated for V2.0.0 of the PDK. It currently support layout generation and LVS using Virtuoso pcells, which was previously not supported. Simulations using BAG is also supported.
+
+This workspace and tech plugin are primarily maintained by Ayan Biswas, Felicia Guo, Sean Huang, and Bob Zhou.
+
+## Technology features and hints
+
+- Layout resolution is in 5nm.
+- Min channel length is 150nm, so min channel units is 30.
+- This tech has standard, lvt, and hvt devices. pch hvt and lvt have min channel length of 350um,
+ so they cannot be used for logic-style MOS with nch.
+- Min nch width is 420nm (84 units). Min pch width is 550nm (110 units).
+- Widths are quantized in irregular intervals. See the pcells for examples.
+ - Nch has 840nm. Pch has 1120nm.
+- This tech has 5 metal layers and an "M0" (LI) layer.
+- This tech has pcell MOM caps. M1-M2 caps provide ~0.4 fF / um^2. M1-M4 caps provide ~0.74 fF /
+ um^2.
+- This tech has pcell MIM caps, between M3-M4 and M4-M5. Both provide ~2.2 fF / um^2.
+
+SD pitch: 0.430 um ~ 86 units. BAG quantizes vertical metal pitches to match the SD pitch ~ li, met2, met4
+
+Metal min width and space (um):
+li : 0.170, 0.170
+met1: 0.140, 0.140
+met2: 0.140, 0.140
+met3: 0.300, 0.300
+met4: 0.300, 0.300
+met5: 1.600, 1.600
+
+Track manager hints:
+- m4 needs to be at least w=5 to connect to m5
+
+### Resistors
+- This tech has two flavors of "precisions" poly resistors: hrpoly (300 ohm / sq) and uhrpoly (2K ohm / sq). Min width is 0.33 um / 66 units, min resistor length is 0.5 um / 100 units. The contacts have a 2.16um length, required by DRC, so the min overall length is 4.82um.
+- `res_type: standard` ~ hrpoly
+
+Width selection
+- For nice compatibility with the routing grid, make the unit cell width quantized to the sd pitch ~ 430 nm / 86 units. (not a hard requirement)
+- LR edges account for up to an additional 780nm / 156 unit
+- Some good values: 102, 360, 532
+
+Length selection
+- To minimize unused area, quantize unit height to sd pitch ~ 86 for working with the routing grid. (not a hard requirement)
+ - Otherwise, unit height will round up to the next pitch of 86
+- TB edges, including taps, account for up to 5.530 um / 1106 units
+- Some good values: 270, 614
+
+
+## Abstract Generation
+
+Abstract generation in this technology does not work out of the box. More details in [this README.](abstract_setup/README.md)
+
+## Extraction
+
+- This tech uses Calibre xRC for extraction. See $PDK_HOME/PEX/xRC and the manual for details.
+- The xRC SVRF is set up to produce SPF files, to match other PEX tools. It can produce Spectre-format
+PEX netlists, but this has not been tested rigorously.
+- xRC automatically capitalizes cell names, so top level cell names need to be full capitalized.
+
+## Licensing
+
+This library is licensed under the Apache-2.0 license. See [here](LICENSE) for full text of the
+Apache license.
diff --git a/abstract_setup/README.md b/abstract_setup/README.md
new file mode 100644
index 0000000..9b3e7a2
--- /dev/null
+++ b/abstract_setup/README.md
@@ -0,0 +1,100 @@
+# Skywater 130 Abstract Generation
+
+The `s8phirs_10r` tech library is somewhat broken when it comes to abstract generation as the techfile is missing some necessary fields. If you would like to generate abstract views (LEF) in sky130 through BAG or manually you have two options, one fast and one slow.
+
+## Fast Option ⬅ (use this one)
+
+Instead of adding `s8phirs_10r` and attaching this to your design and/or BAG output library, add and attach to the library in:
+
+``` unix
+/tools/commercial/skywater/swtech130/local/skywater-src-nda-techfile-fix/s8/V2.0.1/V2.0.1/VirtuosoOA/libs/s8phirs_10r
+```
+
+This library has a fixed techfile and tech.db such that you can now run `gen_cell.py` with the `-lef` option or just load your library into the Cadence abstract tool.
+
+## Slow Option
+
+The issue with the foundry techfiles is twofold:
+
+1. The techfiles are missing the `LEFDefaultRouteSpec` constraint group
+2. The mask numbers are undefined in the `layerRules` section of the techfile.
+
+Both of these issues have to be corrected before abstract will load libraries, and if BAG’s lefgen is run without these fixes, the LEF generation completes but the resulting file is empty.
+
+### Modifying the techfile
+
+You will need write access to the modified library. This may involve copying the s8phirs_10r library from the original PDK location to one where you have write access.
+
+Open Virtuoso and either make a new library and attach it to `s8phirs_10r` or pick a library that is already attached to said technology. Open the Technology File Manager from the CIW through Tools > Technology File Manager.
+
+
+
+From here, either make a copy of the techfile in the PDK or have the Technology File Manger do it by opening the TechDB Checker, selecting `s8phirs_10r` and clicking View Techfile. This will create a new copy of the techfile in your local directory. Make the following changes to this file.
+
+#### LEFDefaultRouteSpec
+
+Add the correct definition of this constraint group under the `constraintGroups(` section as follows:
+
+``` SKILL
+ ;( group [override] [definition] [operator] )
+ ;( ----- ---------- ------------ ---------- )
+ ( "LEFDefaultRouteSpec" nil "LEFDefaultRouteSpec"
+
+ interconnect(
+ (validLayers (poly li1 met1 met2 met3 met4 met5))
+ (validVias (TPL1_C PYL1_C L1M1_C M1M2_C M2M3_C M3M4_C M4M5_C))
+ ) ;interconnect
+ ) ;LEFDefaultRouteSpec
+```
+
+Note that the `validVias` are defined as per the via definitions earlier in the techfile and not the via layer names.
+
+#### layerRules
+
+For the layer rules, we just need to add mask numbers. These don’t appear to need to correspond to any other layer maps so we can just add numbers in order as follows:
+
+``` SKILL
+layerRules(
+
+ functions(
+ ;( layer function [maskNumber])
+ ;( ----- -------- ------------)
+ ( pwell "pwell" 1 )
+ ( nwell "nwell" 2 )
+ ( diff "ndiff" 3 )
+ ( tap "ndiff" 4 )
+ ( poly "poly" 5 )
+ ( licon1 "cut" 6 )
+ ( li1 "metal" 7 )
+ ( mcon "cut" 8 )
+ ( met1 "metal" 9 )
+ ( via "cut" 10 )
+ ( met2 "metal" 11 )
+ ( via2 "cut" 12 )
+ ( met3 "metal" 13 )
+ ( via3 "cut" 14 )
+ ( met4 "metal" 15 )
+ ( via4 "cut" 16 )
+ ( met5 "metal" 17 )
+ ( pad "cut" 18 )
+ ( rdl "metal" 19 )
+ ) ;functions
+
+) ;layerRules
+```
+
+### Saving the Changes
+
+In order for the changes to take effect, the techfile must be merged back into the library and saved to the tech database. From the Technology File Manager, select Load…
+
+
+
+Add your locally modified techfile to the ASCII Technology File field, and select the layerRules and constraintGroups Classes. At the bottom, select the technology library that you have write access to. Either Merge or Replace will work here, but after confirming your settings, run the load and check the CIW for any warnings/errors.
+
+***Alternatively, if you are editing the techfile in the library directly, you can skip the steps up to this point.***
+
+Once you have loaded the techfile and merged with the tech library you will need to save it into the tech database. From the Technology File Manager, select Save… and point to the library we merged our techfile into previously.
+
+
+
+Just hit OK here and watch the CIW for any errors/warnings. If all goes well the CIW should report that the tech library was successfully saved. Once this happens, you are all ready to use abstract generation in sky130! (Told you you should have used the fast option.)
diff --git a/abstract_setup/bag_abstract.options b/abstract_setup/bag_abstract.options
new file mode 100644
index 0000000..9cfad3d
--- /dev/null
+++ b/abstract_setup/bag_abstract.options
@@ -0,0 +1,845 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Abstract Options File
+;; Abstract_Generator version sub-version ICADVM18.1-64b.83 on Jul 11 16:33:23 2019
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+absSetOption( "DateTimeLog" "false")
+absSetOption( "UseOldExtract" "true")
+absSetOption( "QuickAbstract" "false")
+absSetOption( "OptimizeBigDesignMemory" "false")
+absSetOption( "AnnotateBusInAbstract" "true")
+absSetOption( "UseConstraintGroup" "")
+absSetOption( "SortMethod" "Name")
+absSetOption( "SortView" "Abstract")
+absSetOption( "SortOrder" "Ascending")
+absSetOption( "NewLibraryName" "")
+absSetOption( "NewLibraryPath" ".")
+absSetOption( "ImportGDSIIFiles" "")
+absSetOption( "ImportGDSIITemplateFile" "")
+absSetOption( "ImportGDSIILayerMapFile" "")
+absSetOption( "GdsIIImportTechRefLib" "")
+absSetOption( "ImportGDSIICaseMap" "No Mapping")
+absSetOption( "ImportOasisFiles" "")
+absSetOption( "ImportOasisTemplateFile" "")
+absSetOption( "ImportOasisLayerMapFile" "")
+absSetOption( "OasisImportTechRefLib" "")
+absSetOption( "ImportOasisCaseMap" "No Mapping")
+absSetOption( "ImportOasisEnableColoring" "true")
+absSetOption( "ImportLefFiles" "")
+absSetOption( "ImportLefView" "abstract")
+absSetOption( "LefImportTechRefLib" "")
+absSetOption( "ImportTechLef" "false")
+absSetOption( "ImportGDSIIEnableColoring" "true")
+absSetOption( "runAbstractHookPostOat" "false")
+absSetOption( "ImportDefFiles" "")
+absSetOption( "ImportLogicalType" "Verilog")
+absSetOption( "ImportOptionsFile" "")
+absSetOption( "ImportLIBFiles" "")
+absSetOption( "ExportGeometryLefData" "true")
+absSetOption( "ExportLEFCellListFile" "")
+absSetOption( "ExportTechLefData" "false")
+absSetOption( "ExportLEFUnits" "1000")
+absSetOption( "ExportLEFVersion" "5.6")
+absSetOption( "ExportBusChars" "[ ]")
+absSetOption( "ExportDividerChar" "/")
+absSetOption( "CellStatsFile" "cellSummary.report")
+absSetOption( "ExportReportFile" "abstract.report")
+absSetOption( "ExportOptionsFile" "abstract.options")
+absSetOption( "SelectName" "")
+absSetOption( "SelectView" "All")
+absSetOption( "SelectHeightFrom" "")
+absSetOption( "SelectHeightTo" "")
+absSetOption( "SelectPropertyName" "")
+absSetOption( "SelectPropertyVal" "")
+absSetOption( "SelectValid" "false")
+absSetOption( "SelectInvalid" "false")
+absSetOption( "ViewLayout" "layout")
+absSetOption( "ViewLogical" "logical")
+absSetOption( "ViewAbstract" "abstract")
+absSetOption( "ExtractedPurpose" "net")
+absSetOption( "InterpType" "Skill")
+absSetOption( "SelectByMsg" "")
+absSetOption( "DefaultBin" "Block")
+absSetOption( "ExportLEFBin" "All")
+absSetOption( "DistributeBinAboveTop" "Block")
+absSetOption( "DistributeBinAboveMiddle" "IO")
+absSetOption( "DistributeBinAboveBottom" "Core")
+absSetOption( "DistributeBinBelowBottom" "Ignore")
+absSetOption( "DistributeBinMatch1" "Block")
+absSetOption( "DistributeBinMatch2" "IO")
+absSetOption( "DistributeBinMatch3" "Core")
+absSetOption( "DistributeBinMatchOther" "Ignore")
+absSetOption( "DistributeBinCoreType" "Core")
+absSetOption( "DistributeBinIOType" "IO")
+absSetOption( "DistributeBinCornerType" "Corner")
+absSetOption( "DistributeBinBlockType" "Block")
+absSetOption( "DistributeBinOtherType" "Ignore")
+absSetOption( "DistributeMethod" "height")
+absSetOption( "DistributeCells" "all")
+absSetOption( "DistributeHeightTop" "1000")
+absSetOption( "DistributeHeightMiddle" "180")
+absSetOption( "DistributeHeightBottom" "100")
+absSetOption( "DistributeMatch1" "block")
+absSetOption( "DistributeMatch2" "io")
+absSetOption( "DistributeMatch3" "core")
+absSetOption( "ExcludePurposeList" "boundary")
+absSetOption( "ShowBubbleHelp" "true")
+absSetOption( "GridCellsPrbFactorX" "1000")
+absSetOption( "GridCellsPrbFactorY" "1000")
+absSetOption( "GridCellsTermsOnGridFactor" "1000")
+absSetOption( "GridCellsTermsValidFactor" "1000")
+absSetOption( "GridCellsBlockagesOnGridFactor" "1000")
+absSetOption( "GridTermsOnGridFactor" "10")
+absSetOption( "GridPinsOnGridFactor" "10")
+absSetOption( "GridBlockagesOnGridFactor" "10")
+absSetOption( "GridDiagonalViasFactor" "10000")
+absSetOption( "ExtractShapeLimit" "30000")
+absSetOption( "suppressMessage" "0")
+absSetOption( "RecordFile" "abstract.record")
+absSetOption( "RecordMode" "Append")
+absSetOption( "ReplayFiles" "")
+absSetOption( "IgnoreCellsForExtraction" "")
+absSetOption( "AnnotateLayoutDualView" "false")
+absSetOption( "ReadVoltageAndPurposeRules" "false")
+absSetOption( "CopyMSRoutingConstraints" "false")
+absSetOption( "ReadOnlyTechnology" "true")
+absSetOption( "numOfPointsInEllipseOrDonut" "64")
+
+
+absDeselectBin("Core" )
+absSetBinOption( "Core" "PinsTextPinMap" "")
+absSetBinOption( "Core" "PinsPowerNames" "^((V(DD|CC).*)|(v(dd|cc)))(!)?$")
+absSetBinOption( "Core" "PinsGroundNames" "^((VSS|GND)|(vss|gnd))(!)?$")
+absSetBinOption( "Core" "PinsClockNames" "")
+absSetBinOption( "Core" "PinsAnalogNames" "")
+absSetBinOption( "Core" "PinsOutputNames" "")
+absSetBinOption( "Core" "ExcludeExistingTerminals" "")
+absSetBinOption( "Core" "PinsExcludeExistingPinssOnLayers" "")
+absSetBinOption( "Core" "PinsFromTextForExistingPins" "false")
+absSetBinOption( "Core" "PinsTextPromoteLevel" "0")
+absSetBinOption( "Core" "PinsGeomSearchLevel" "20")
+absSetBinOption( "Core" "PinsTextManipulation" "{\\\\.extra.*} {} :.* {} {\\(([0-9]+)\\)} {<\\1>} {\\[([0-9]+)\\]} {<\\1>}")
+absSetBinOption( "Core" "PinsTextManipulationTable" "")
+absSetBinOption( "Core" "PinsTextPreserveLabels" "true")
+absSetBinOption( "Core" "PinsRestrictToPRBndry" "false")
+absSetBinOption( "Core" "PinsBoundaryCreate" "as needed")
+absSetBinOption( "Core" "PinsBoundaryLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 poly diff nwell ")
+absSetBinOption( "Core" "PinsBoundarySizeLeft" "")
+absSetBinOption( "Core" "PinsBoundarySizeRight" "")
+absSetBinOption( "Core" "PinsBoundarySizeTop" "")
+absSetBinOption( "Core" "PinsBoundarySizeBottom" "")
+absSetBinOption( "Core" "PinsBoundaryFixedLeft" "")
+absSetBinOption( "Core" "PinsBoundaryFixedRight" "")
+absSetBinOption( "Core" "PinsBoundaryFixedTop" "")
+absSetBinOption( "Core" "PinsBoundaryFixedBottom" "")
+absSetBinOption( "Core" "PinsPreserveRoutingBlockages" "false")
+absSetBinOption( "Core" "PinsCreatePwrPinsFromRouting" "false")
+absSetBinOption( "Core" "PinsPwrRoutingLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Core" "PinsCreatepolyPRB" "false")
+absSetBinOption( "Core" "ExtractSig" "true")
+absSetBinOption( "Core" "ExtractLayersSig" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Core" "ExtractLayersSigWeak" "")
+absSetBinOption( "Core" "ExtractPinLayersSig" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Core" "AbstractExtractGSpecTable" "")
+absSetBinOption( "Core" "ExtractNumLevelsSig" "32")
+absSetBinOption( "Core" "ExtractDistSig" "")
+absSetBinOption( "Core" "ExtractWidthSig" "")
+absSetBinOption( "Core" "ExtractMustJoinAlways" "false")
+absSetBinOption( "Core" "ExtractMustJoinTerminals" "")
+absSetBinOption( "Core" "ExtractPwr" "true")
+absSetBinOption( "Core" "ExtractLayersPwr" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Core" "ExtractPinLayersPwr" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Core" "AbstractExtractPwrGSpecTable" "")
+absSetBinOption( "Core" "ExtractNumLevelsPwr" "32")
+absSetBinOption( "Core" "ExtractDistPwr" "")
+absSetBinOption( "Core" "ExtractWidthPwr" "")
+absSetBinOption( "Core" "ExtractMustJoinAlwaysPwr" "false")
+absSetBinOption( "Core" "ExtractMustJoinTerminalsPwr" "")
+absSetBinOption( "Core" "ExtractAntennaHier" "false")
+absSetBinOption( "Core" "ExtractAntennaSizeInput" "false")
+absSetBinOption( "Core" "ExtractAntennaSizeOutput" "false")
+absSetBinOption( "Core" "ExtractAntennaSizeInout" "false")
+absSetBinOption( "Core" "ExtractAntennaMetalArea" "false")
+absSetBinOption( "Core" "ExtractAntennaMetalSideArea" "false")
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+absSetBinOption( "Core" "ExtractAntennaDrain" "(diff (diff andnot poly)) ")
+absSetBinOption( "Core" "ExtractAntennaOxide" "")
+absSetBinOption( "Core" "ExtractAntennaIncludepolyCAR" "false")
+absSetBinOption( "Core" "AbstractAntennaGSpecTable" "")
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+absSetBinOption( "Core" "ExtractAntennaGSpecTable" "")
+absSetBinOption( "Core" "ExtractAntennaExcludeNets" "")
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+absSetBinOption( "Core" "ExtractUseNetInfo" "false")
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+absSetBinOption( "Core" "AbstractAdjustAllowPin" "")
+absSetBinOption( "Core" "AbstractAdjustAvoidPin" "")
+absSetBinOption( "Core" "AbstractAdjustPinLPPsGTable" "")
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+absSetBinOption( "Core" "AbstractAdjustPowerRailOpTable" "")
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+absSetBinOption( "Core" "AbstractAdjustIncludeAllShapes" "false")
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+absSetBinOption( "Core" "AbstractBlockagePinCutWindow" "")
+absSetBinOption( "Core" "AbstractBlockageCutForAboveLayers" "")
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+absSetBinOption( "Core" "VerifyTargetIgnore" "EXCHANGEFORMATS-USER-525\nEXCHANGEFORMATS-USER-392\nEXCHANGEFORMATS-USER-34\nno clock net")
+
+absDeselectBin("IO" )
+absSetBinOption( "IO" "PinsTextPinMap" "")
+absSetBinOption( "IO" "PinsPowerNames" "^((V(DD|CC))|(v(dd|cc)))(!)?$")
+absSetBinOption( "IO" "PinsGroundNames" "^((VSS|GND)|(vss|gnd))(!)?$")
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+absSetBinOption( "IO" "PinsTextManipulationTable" "")
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+absSetBinOption( "IO" "PinsBoundarySizeLeft" "")
+absSetBinOption( "IO" "PinsBoundarySizeRight" "")
+absSetBinOption( "IO" "PinsBoundarySizeTop" "")
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+absSetBinOption( "IO" "PinsBoundaryFixedLeft" "")
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+absSetBinOption( "IO" "PinsBoundaryFixedTop" "")
+absSetBinOption( "IO" "PinsBoundaryFixedBottom" "")
+absSetBinOption( "IO" "PinsPreserveRoutingBlockages" "false")
+absSetBinOption( "IO" "PinsCreatePwrPinsFromRouting" "false")
+absSetBinOption( "IO" "PinsPwrRoutingLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "IO" "PinsCreatepolyPRB" "false")
+absSetBinOption( "IO" "ExtractSig" "false")
+absSetBinOption( "IO" "ExtractLayersSig" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "IO" "ExtractLayersSigWeak" "")
+absSetBinOption( "IO" "ExtractPinLayersSig" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
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+absSetBinOption( "IO" "ExtractWidthSig" "")
+absSetBinOption( "IO" "ExtractMustJoinAlways" "false")
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+absSetBinOption( "IO" "ExtractPwr" "false")
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+absSetBinOption( "IO" "ExtractPinLayersPwr" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "IO" "AbstractExtractPwrGSpecTable" "")
+absSetBinOption( "IO" "ExtractNumLevelsPwr" "32")
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+absSetBinOption( "IO" "ExtractWidthPwr" "")
+absSetBinOption( "IO" "ExtractMustJoinAlwaysPwr" "false")
+absSetBinOption( "IO" "ExtractMustJoinTerminalsPwr" "")
+absSetBinOption( "IO" "ExtractAntennaHier" "false")
+absSetBinOption( "IO" "ExtractAntennaSizeInput" "false")
+absSetBinOption( "IO" "ExtractAntennaSizeOutput" "false")
+absSetBinOption( "IO" "ExtractAntennaSizeInout" "false")
+absSetBinOption( "IO" "ExtractAntennaMetalArea" "false")
+absSetBinOption( "IO" "ExtractAntennaMetalSideArea" "false")
+absSetBinOption( "IO" "CalcAntennaMaxCutCARLowestCut" "false")
+absSetBinOption( "IO" "ExtractAntennaNoAdjust" "false")
+absSetBinOption( "IO" "ExtractAntennaGate" "(poly (poly and diff))")
+absSetBinOption( "IO" "ExtractAntennaDrain" "(diff (diff andnot poly)) ")
+absSetBinOption( "IO" "ExtractAntennaOxide" "")
+absSetBinOption( "IO" "ExtractAntennaIncludepolyCAR" "false")
+absSetBinOption( "IO" "AbstractAntennaGSpecTable" "")
+absSetBinOption( "IO" "ExtractDiffAntennaLayers" "false")
+absSetBinOption( "IO" "ExtractAntennaLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "IO" "ExtractAntennaGSpecTable" "")
+absSetBinOption( "IO" "ExtractAntennaExcludeNets" "")
+absSetBinOption( "IO" "ExtractCache" "false")
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+absSetBinOption( "IO" "ExtractUseNetInfo" "false")
+absSetBinOption( "IO" "ExtractConnectivity" "(met1 met2 via)(met2 met3 via2)(met3 met4 via3)(met4 met5 via4)")
+absSetBinOption( "IO" "AbstractAdjustAllowPin" "")
+absSetBinOption( "IO" "AbstractAdjustAvoidPin" "")
+absSetBinOption( "IO" "AbstractAdjustPinLPPsGTable" "")
+absSetBinOption( "IO" "AbstractAdjustBoundaryPinsSig" "false")
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+absSetBinOption( "IO" "AbstractAdjustRingPinsPwr" "false")
+absSetBinOption( "IO" "AbstractAdjustRingPinsDist" "")
+absSetBinOption( "IO" "AbstractAdjustFollowRingPin" "false")
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+absSetBinOption( "IO" "AbstractAdjustPowerRailOp" "")
+absSetBinOption( "IO" "AbstractAdjustPowerRailOpTable" "")
+absSetBinOption( "IO" "AbstractAdjustPowerRailWidth" "0")
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+absSetBinOption( "IO" "AbstractAdjustClassCoreNets" "^((V(DD|CC))|(v(dd|cc)))(!)?$")
+absSetBinOption( "IO" "AbstractAdjustIncludeAllShapes" "false")
+absSetBinOption( "IO" "AbstractAdjustCopyClassCorePort" "false")
+absSetBinOption( "IO" "AbstractAdjustPinsTouchBoundary" "false")
+absSetBinOption( "IO" "AbstractAdjustPinsTouchNonCoreEdge" "true")
+absSetBinOption( "IO" "AbstractAdjustCreateClassBumpPort" "false")
+absSetBinOption( "IO" "AbstractAdjustPreserveViasPwr" "false")
+absSetBinOption( "IO" "AbstractAdjustDuplicatePinShapes" "false")
+absSetBinOption( "IO" "AbstractBlockageLayerOrder" "false")
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+absSetBinOption( "IO" "AbstractBlockageCoverLayers" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "IO" "AbstractBlockageShrinkWrapLayers" "")
+absSetBinOption( "IO" "AbstractBlockageCoverLayersDist" "")
+absSetBinOption( "IO" "AbstractBlockageShrinkTracks" "")
+absSetBinOption( "IO" "AbstractBlockageShrinkAdjust" "")
+absSetBinOption( "IO" "AbstractBlockagePinCutWindow" "")
+absSetBinOption( "IO" "AbstractBlockageCutForAboveLayers" "")
+absSetBinOption( "IO" "AbstractBlockageDownPinCutWindow" "")
+absSetBinOption( "IO" "AbstractBlockageCutAroundPin" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "IO" "AbstractBlockageMaxRoutingSpace" "")
+absSetBinOption( "IO" "AbstractBlockageCorridorCut" "")
+absSetBinOption( "IO" "AbstractBlockageTable" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "IO" "BlockageCutVia" "true")
+absSetBinOption( "IO" "AbstractZeroSpacingBlockage" "false")
+absSetBinOption( "IO" "BlockageLargeShapePct" "10")
+absSetBinOption( "IO" "BlockageLargeShape" "true")
+absSetBinOption( "IO" "BlockageLargePurposeList" "boundary")
+absSetBinOption( "IO" "AbstractBlockageEXCEPTPGNET" "")
+absSetBinOption( "IO" "AbstractBlockageUserDefinedSpacing" "")
+absSetBinOption( "IO" "AbstractBlockageUserDefinedWidth" "")
+absSetBinOption( "IO" "AbstractBlockageUserDefinedDistanceForAddBack" "")
+absSetBinOption( "IO" "AbstractBlockageRoutingChannelOnLayers" "")
+absSetBinOption( "IO" "AbstractTopLayerCoverBlockage" "")
+absSetBinOption( "IO" "AbstractDensity" "false")
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+absSetBinOption( "IO" "AbstractDensityUseAntennaLayers" "false")
+absSetBinOption( "IO" "AbstractDensityUsePwrLayers" "false")
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+absSetBinOption( "IO" "AbstractDensityTable" "")
+absSetBinOption( "IO" "AbstractDensityWindowWidth" "")
+absSetBinOption( "IO" "AbstractDensityWindowHeight" "")
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+absSetBinOption( "IO" "AbstractOverlapLayerSmoothFactor" "0")
+absSetBinOption( "IO" "AbstractGridMode" "off")
+absSetBinOption( "IO" "AbstractUpdateTechFile" "false")
+absSetBinOption( "IO" "AbstractMetal1Pitch" "0.05")
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+absSetBinOption( "IO" "AbstractMetal3Pitch" "0.05")
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+absSetBinOption( "IO" "AbstractMetal3PitchPercent" "50")
+absSetBinOption( "IO" "AbstractPinAccessMode" "narrowPin")
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+absSetBinOption( "IO" "AbstractGridDistanceMetric" "euclidean")
+absSetBinOption( "IO" "AbstractRetainLayout" "false")
+absSetBinOption( "IO" "AbstractPinStretchOutPrb" "false")
+absSetBinOption( "IO" "VerifyTerminals" "true")
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+absSetBinOption( "IO" "VerifyGrid" "true")
+absSetBinOption( "IO" "VerifyTarget" "true")
+absSetBinOption( "IO" "VerifyTargetSelection" "Silicon Ensemble")
+absSetBinOption( "IO" "TargetSystemCMD" "sedsm -m=96 -gd=ansi")
+absSetBinOption( "IO" "VerifyEncounterPromptRegEx" "encounter$")
+absSetBinOption( "IO" "VerifyTargetRowDirection" "horizontal")
+absSetBinOption( "IO" "VerifyTechFile" "")
+absSetBinOption( "IO" "VerifyTargetMultiple" "false")
+absSetBinOption( "IO" "VerifyTargetMultipleRows" "false")
+absSetBinOption( "IO" "VerifyTargetPower" "false")
+absSetBinOption( "IO" "VerifySrouteConfigFile" "")
+absSetBinOption( "IO" "VerifyTargetRouter" "Nanoroute")
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+absSetBinOption( "IO" "VerifyConfigFile" "")
+absSetBinOption( "IO" "VerifyTargetGeom" "")
+absSetBinOption( "IO" "VerifyTargetIgnore" "EXCHANGEFORMATS-USER-525\nEXCHANGEFORMATS-USER-392\nEXCHANGEFORMATS-USER-34\nno clock net")
+
+absDeselectBin("Corner" )
+absSetBinOption( "Corner" "PinsTextPinMap" "")
+absSetBinOption( "Corner" "PinsPowerNames" "^((V(DD|CC))|(v(dd|cc)))(!)?$")
+absSetBinOption( "Corner" "PinsGroundNames" "^((VSS|GND)|(vss|gnd))(!)?$")
+absSetBinOption( "Corner" "PinsClockNames" "")
+absSetBinOption( "Corner" "PinsAnalogNames" "")
+absSetBinOption( "Corner" "PinsOutputNames" "")
+absSetBinOption( "Corner" "ExcludeExistingTerminals" "")
+absSetBinOption( "Corner" "PinsExcludeExistingPinssOnLayers" "")
+absSetBinOption( "Corner" "PinsFromTextForExistingPins" "false")
+absSetBinOption( "Corner" "PinsTextPromoteLevel" "0")
+absSetBinOption( "Corner" "PinsGeomSearchLevel" "20")
+absSetBinOption( "Corner" "PinsTextManipulation" "{\\\\.extra.*} {} :.* {} {\\(([0-9]+)\\)} {<\\1>} {\\[([0-9]+)\\]} {<\\1>}")
+absSetBinOption( "Corner" "PinsTextManipulationTable" "")
+absSetBinOption( "Corner" "PinsTextPreserveLabels" "true")
+absSetBinOption( "Corner" "PinsRestrictToPRBndry" "false")
+absSetBinOption( "Corner" "PinsBoundaryCreate" "as needed")
+absSetBinOption( "Corner" "PinsBoundaryLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 poly diff nwell ")
+absSetBinOption( "Corner" "PinsBoundarySizeLeft" "")
+absSetBinOption( "Corner" "PinsBoundarySizeRight" "")
+absSetBinOption( "Corner" "PinsBoundarySizeTop" "")
+absSetBinOption( "Corner" "PinsBoundarySizeBottom" "")
+absSetBinOption( "Corner" "PinsBoundaryFixedLeft" "")
+absSetBinOption( "Corner" "PinsBoundaryFixedRight" "")
+absSetBinOption( "Corner" "PinsBoundaryFixedTop" "")
+absSetBinOption( "Corner" "PinsBoundaryFixedBottom" "")
+absSetBinOption( "Corner" "PinsPreserveRoutingBlockages" "false")
+absSetBinOption( "Corner" "PinsCreatePwrPinsFromRouting" "false")
+absSetBinOption( "Corner" "PinsPwrRoutingLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Corner" "PinsCreatepolyPRB" "false")
+absSetBinOption( "Corner" "ExtractSig" "false")
+absSetBinOption( "Corner" "ExtractLayersSig" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Corner" "ExtractLayersSigWeak" "")
+absSetBinOption( "Corner" "ExtractPinLayersSig" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Corner" "AbstractExtractGSpecTable" "")
+absSetBinOption( "Corner" "ExtractNumLevelsSig" "32")
+absSetBinOption( "Corner" "ExtractDistSig" "")
+absSetBinOption( "Corner" "ExtractWidthSig" "")
+absSetBinOption( "Corner" "ExtractMustJoinAlways" "false")
+absSetBinOption( "Corner" "ExtractMustJoinTerminals" "")
+absSetBinOption( "Corner" "ExtractPwr" "false")
+absSetBinOption( "Corner" "ExtractLayersPwr" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Corner" "ExtractPinLayersPwr" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Corner" "AbstractExtractPwrGSpecTable" "")
+absSetBinOption( "Corner" "ExtractNumLevelsPwr" "32")
+absSetBinOption( "Corner" "ExtractDistPwr" "")
+absSetBinOption( "Corner" "ExtractWidthPwr" "")
+absSetBinOption( "Corner" "ExtractMustJoinAlwaysPwr" "false")
+absSetBinOption( "Corner" "ExtractMustJoinTerminalsPwr" "")
+absSetBinOption( "Corner" "ExtractAntennaHier" "false")
+absSetBinOption( "Corner" "ExtractAntennaSizeInput" "false")
+absSetBinOption( "Corner" "ExtractAntennaSizeOutput" "false")
+absSetBinOption( "Corner" "ExtractAntennaSizeInout" "false")
+absSetBinOption( "Corner" "ExtractAntennaMetalArea" "false")
+absSetBinOption( "Corner" "ExtractAntennaMetalSideArea" "false")
+absSetBinOption( "Corner" "CalcAntennaMaxCutCARLowestCut" "false")
+absSetBinOption( "Corner" "ExtractAntennaNoAdjust" "false")
+absSetBinOption( "Corner" "ExtractAntennaGate" "(poly (poly and diff))")
+absSetBinOption( "Corner" "ExtractAntennaDrain" "(diff (diff andnot poly)) ")
+absSetBinOption( "Corner" "ExtractAntennaOxide" "")
+absSetBinOption( "Corner" "ExtractAntennaIncludepolyCAR" "false")
+absSetBinOption( "Corner" "AbstractAntennaGSpecTable" "")
+absSetBinOption( "Corner" "ExtractDiffAntennaLayers" "false")
+absSetBinOption( "Corner" "ExtractAntennaLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Corner" "ExtractAntennaGSpecTable" "")
+absSetBinOption( "Corner" "ExtractAntennaExcludeNets" "")
+absSetBinOption( "Corner" "ExtractCache" "false")
+absSetBinOption( "Corner" "ExtractCacheGrid" "5")
+absSetBinOption( "Corner" "ExtractCacheNumGrid" "50")
+absSetBinOption( "Corner" "ExtractCacheUtil" "0")
+absSetBinOption( "Corner" "ExtractCacheUtilPct" "30")
+absSetBinOption( "Corner" "ExtractAdjustInitialPinShapes" "false")
+absSetBinOption( "Corner" "ExtractUseNetInfo" "false")
+absSetBinOption( "Corner" "ExtractConnectivity" "(met1 met2 via)(met2 met3 via2)(met3 met4 via3)(met4 met5 via4)")
+absSetBinOption( "Corner" "AbstractAdjustAllowPin" "")
+absSetBinOption( "Corner" "AbstractAdjustAvoidPin" "")
+absSetBinOption( "Corner" "AbstractAdjustPinLPPsGTable" "")
+absSetBinOption( "Corner" "AbstractAdjustBoundaryPinsSig" "false")
+absSetBinOption( "Corner" "AbstractAdjustBoundaryPinsSigDist" "")
+absSetBinOption( "Corner" "AbstractAdjustSignalGeometryGroups" "single")
+absSetBinOption( "Corner" "AbstractAdjustSignalGeometryGroupsEastWest" "none")
+absSetBinOption( "Corner" "AbstractAdjustBoundaryPinsPwr" "false")
+absSetBinOption( "Corner" "AbstractAdjustBoundaryPinsPwrDist" "")
+absSetBinOption( "Corner" "AbstractAdjustRingPinsPwr" "false")
+absSetBinOption( "Corner" "AbstractAdjustRingPinsDist" "")
+absSetBinOption( "Corner" "AbstractAdjustFollowRingPin" "false")
+absSetBinOption( "Corner" "AbstractAdjustPowerGeometryGroups" "single")
+absSetBinOption( "Corner" "AbstractAdjustPowerGeometryGroupsEastWest" "none")
+absSetBinOption( "Corner" "AbstractAdjustPowerRailOp" "")
+absSetBinOption( "Corner" "AbstractAdjustPowerRailOpTable" "")
+absSetBinOption( "Corner" "AbstractAdjustPowerRailWidth" "0")
+absSetBinOption( "Corner" "AbstractAdjustEdgeTowardsCore" "north")
+absSetBinOption( "Corner" "AbstractAdjustClassCoreNets" "^((V(DD|CC))|(v(dd|cc)))(!)?$")
+absSetBinOption( "Corner" "AbstractAdjustIncludeAllShapes" "false")
+absSetBinOption( "Corner" "AbstractAdjustCopyClassCorePort" "false")
+absSetBinOption( "Corner" "AbstractAdjustPinsTouchBoundary" "false")
+absSetBinOption( "Corner" "AbstractAdjustPinsTouchNonCoreEdge" "true")
+absSetBinOption( "Corner" "AbstractAdjustCreateClassBumpPort" "false")
+absSetBinOption( "Corner" "AbstractAdjustPreserveViasPwr" "false")
+absSetBinOption( "Corner" "AbstractAdjustDuplicatePinShapes" "false")
+absSetBinOption( "Corner" "AbstractBlockageLayerOrder" "false")
+absSetBinOption( "Corner" "AbstractBlockageDetailedLayers" "")
+absSetBinOption( "Corner" "AbstractBlockageCoverLayers" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Corner" "AbstractBlockageShrinkWrapLayers" "")
+absSetBinOption( "Corner" "AbstractBlockageCoverLayersDist" "")
+absSetBinOption( "Corner" "AbstractBlockageShrinkTracks" "")
+absSetBinOption( "Corner" "AbstractBlockageShrinkAdjust" "")
+absSetBinOption( "Corner" "AbstractBlockagePinCutWindow" "")
+absSetBinOption( "Corner" "AbstractBlockageCutForAboveLayers" "")
+absSetBinOption( "Corner" "AbstractBlockageDownPinCutWindow" "")
+absSetBinOption( "Corner" "AbstractBlockageCutAroundPin" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Corner" "AbstractBlockageMaxRoutingSpace" "")
+absSetBinOption( "Corner" "AbstractBlockageCorridorCut" "")
+absSetBinOption( "Corner" "AbstractBlockageTable" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Corner" "BlockageCutVia" "true")
+absSetBinOption( "Corner" "AbstractZeroSpacingBlockage" "false")
+absSetBinOption( "Corner" "BlockageLargeShapePct" "10")
+absSetBinOption( "Corner" "BlockageLargeShape" "true")
+absSetBinOption( "Corner" "BlockageLargePurposeList" "boundary")
+absSetBinOption( "Corner" "AbstractBlockageEXCEPTPGNET" "")
+absSetBinOption( "Corner" "AbstractBlockageUserDefinedSpacing" "")
+absSetBinOption( "Corner" "AbstractBlockageUserDefinedWidth" "")
+absSetBinOption( "Corner" "AbstractBlockageUserDefinedDistanceForAddBack" "")
+absSetBinOption( "Corner" "AbstractBlockageRoutingChannelOnLayers" "")
+absSetBinOption( "Corner" "AbstractTopLayerCoverBlockage" "")
+absSetBinOption( "Corner" "AbstractDensity" "false")
+absSetBinOption( "Corner" "AbstractDensityUseSignalLayers" "false")
+absSetBinOption( "Corner" "AbstractDensityUseAntennaLayers" "false")
+absSetBinOption( "Corner" "AbstractDensityUsePwrLayers" "false")
+absSetBinOption( "Corner" "AbstractDensityLayers" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Corner" "AbstractDensityTable" "")
+absSetBinOption( "Corner" "AbstractDensityWindowWidth" "")
+absSetBinOption( "Corner" "AbstractDensityWindowHeight" "")
+absSetBinOption( "Corner" "AbstractDensityDefaultWindowWidth" "20")
+absSetBinOption( "Corner" "AbstractDensityDefaultWindowHeight" "20")
+absSetBinOption( "Corner" "AbstractPinFracture" "true")
+absSetBinOption( "Corner" "AbstractBlockageFracture" "true")
+absSetBinOption( "Corner" "AbstractAdjustStairStepCover" "partial")
+absSetBinOption( "Corner" "AbstractAdjustStairStepWidth" "0.024")
+absSetBinOption( "Corner" "AbstractSiteName" "")
+absSetBinOption( "Corner" "AbstractSiteNameDefine" "")
+absSetBinOption( "Corner" "AbstractSiteArrayPattern" "false")
+absSetBinOption( "Corner" "AbstractSiteArrayCells" "")
+absSetBinOption( "Corner" "AbstractSiteArrayCellsTable" "")
+absSetBinOption( "Corner" "AbstractOverlapLayerAction" "off")
+absSetBinOption( "Corner" "AbstractOverlapLayers" "")
+absSetBinOption( "Corner" "AbstractOverlapLayerSize" "0")
+absSetBinOption( "Corner" "AbstractOverlapLayerSmoothFactor" "0")
+absSetBinOption( "Corner" "AbstractGridMode" "off")
+absSetBinOption( "Corner" "AbstractUpdateTechFile" "false")
+absSetBinOption( "Corner" "AbstractMetal1Pitch" "0.05")
+absSetBinOption( "Corner" "AbstractMetal1Offset" "0")
+absSetBinOption( "Corner" "AbstractMetal2Pitch" "0.05")
+absSetBinOption( "Corner" "AbstractMetal2Offset" "0")
+absSetBinOption( "Corner" "AbstractMetal3Pitch" "0.05")
+absSetBinOption( "Corner" "AbstractMetal3Offset" "0")
+absSetBinOption( "Corner" "AbstractMetal1PitchPercent" "50")
+absSetBinOption( "Corner" "AbstractMetal2PitchPercent" "50")
+absSetBinOption( "Corner" "AbstractMetal3PitchPercent" "50")
+absSetBinOption( "Corner" "AbstractPinAccessMode" "narrowPin")
+absSetBinOption( "Corner" "AbstractDiagonalVias" "false")
+absSetBinOption( "Corner" "AbstractGridDistanceMetric" "euclidean")
+absSetBinOption( "Corner" "AbstractRetainLayout" "false")
+absSetBinOption( "Corner" "AbstractPinStretchOutPrb" "false")
+absSetBinOption( "Corner" "VerifyTerminals" "true")
+absSetBinOption( "Corner" "VerifyRowSpacing" "0")
+absSetBinOption( "Corner" "VerifyGrid" "true")
+absSetBinOption( "Corner" "VerifyTarget" "true")
+absSetBinOption( "Corner" "VerifyTargetSelection" "Silicon Ensemble")
+absSetBinOption( "Corner" "TargetSystemCMD" "sedsm -m=96 -gd=ansi")
+absSetBinOption( "Corner" "VerifyEncounterPromptRegEx" "encounter$")
+absSetBinOption( "Corner" "VerifyTargetRowDirection" "horizontal")
+absSetBinOption( "Corner" "VerifyTechFile" "")
+absSetBinOption( "Corner" "VerifyTargetMultiple" "false")
+absSetBinOption( "Corner" "VerifyTargetMultipleRows" "false")
+absSetBinOption( "Corner" "VerifyTargetPower" "false")
+absSetBinOption( "Corner" "VerifySrouteConfigFile" "")
+absSetBinOption( "Corner" "VerifyTargetRouter" "Nanoroute")
+absSetBinOption( "Corner" "VerifyTargetMaxRouteTime" "1")
+absSetBinOption( "Corner" "VerifyConfigFile" "")
+absSetBinOption( "Corner" "VerifyTargetGeom" "")
+absSetBinOption( "Corner" "VerifyTargetIgnore" "EXCHANGEFORMATS-USER-525\nEXCHANGEFORMATS-USER-392\nEXCHANGEFORMATS-USER-34\nno clock net")
+
+absSelectBin("Block" )
+absSetBinOption( "Block" "PinsTextPinMap" "(met5 met5) (met4 met4) (met3 met3) (met2 met2) (met1 met1)")
+absSetBinOption( "Block" "PinsPowerNames" "^((V(DD|CC))|(v(dd|cc)))(!)?$")
+absSetBinOption( "Block" "PinsGroundNames" "^((VSS|GND)|(vss|gnd))(!)?$")
+absSetBinOption( "Block" "PinsClockNames" "clk")
+absSetBinOption( "Block" "PinsAnalogNames" "")
+absSetBinOption( "Block" "PinsOutputNames" "out")
+absSetBinOption( "Block" "ExcludeExistingTerminals" ".*")
+absSetBinOption( "Block" "PinsExcludeExistingPinssOnLayers" "")
+absSetBinOption( "Block" "PinsFromTextForExistingPins" "false")
+absSetBinOption( "Block" "PinsTextPromoteLevel" "0")
+absSetBinOption( "Block" "PinsGeomSearchLevel" "20")
+absSetBinOption( "Block" "PinsTextManipulation" "{\\\\.extra.*} {} :.* {} {\\(([0-9]+)\\)} {<\\1>} {\\[([0-9]+)\\]} {<\\1>}")
+absSetBinOption( "Block" "PinsTextManipulationTable" "")
+absSetBinOption( "Block" "PinsTextPreserveLabels" "true")
+absSetBinOption( "Block" "PinsRestrictToPRBndry" "false")
+absSetBinOption( "Block" "PinsBoundaryCreate" "as needed")
+absSetBinOption( "Block" "PinsBoundaryLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 poly diff nwell ")
+absSetBinOption( "Block" "PinsBoundarySizeLeft" "")
+absSetBinOption( "Block" "PinsBoundarySizeRight" "")
+absSetBinOption( "Block" "PinsBoundarySizeTop" "")
+absSetBinOption( "Block" "PinsBoundarySizeBottom" "")
+absSetBinOption( "Block" "PinsBoundaryFixedLeft" "")
+absSetBinOption( "Block" "PinsBoundaryFixedRight" "")
+absSetBinOption( "Block" "PinsBoundaryFixedTop" "")
+absSetBinOption( "Block" "PinsBoundaryFixedBottom" "")
+absSetBinOption( "Block" "PinsPreserveRoutingBlockages" "false")
+absSetBinOption( "Block" "PinsCreatePwrPinsFromRouting" "false")
+absSetBinOption( "Block" "PinsPwrRoutingLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Block" "PinsCreatepolyPRB" "false")
+absSetBinOption( "Block" "ExtractSig" "true")
+absSetBinOption( "Block" "ExtractLayersSig" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "ExtractLayersSigWeak" "")
+absSetBinOption( "Block" "ExtractPinLayersSig" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "AbstractExtractGSpecTable" "")
+absSetBinOption( "Block" "ExtractNumLevelsSig" "32")
+absSetBinOption( "Block" "ExtractDistSig" "")
+absSetBinOption( "Block" "ExtractWidthSig" "")
+absSetBinOption( "Block" "ExtractMustJoinAlways" "false")
+absSetBinOption( "Block" "ExtractMustJoinTerminals" "")
+absSetBinOption( "Block" "ExtractPwr" "true")
+absSetBinOption( "Block" "ExtractLayersPwr" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "ExtractPinLayersPwr" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "AbstractExtractPwrGSpecTable" "")
+absSetBinOption( "Block" "ExtractNumLevelsPwr" "32")
+absSetBinOption( "Block" "ExtractDistPwr" "")
+absSetBinOption( "Block" "ExtractWidthPwr" "")
+absSetBinOption( "Block" "ExtractMustJoinAlwaysPwr" "false")
+absSetBinOption( "Block" "ExtractMustJoinTerminalsPwr" "")
+absSetBinOption( "Block" "ExtractAntennaHier" "false")
+absSetBinOption( "Block" "ExtractAntennaSizeInput" "false")
+absSetBinOption( "Block" "ExtractAntennaSizeOutput" "false")
+absSetBinOption( "Block" "ExtractAntennaSizeInout" "false")
+absSetBinOption( "Block" "ExtractAntennaMetalArea" "false")
+absSetBinOption( "Block" "ExtractAntennaMetalSideArea" "false")
+absSetBinOption( "Block" "CalcAntennaMaxCutCARLowestCut" "false")
+absSetBinOption( "Block" "ExtractAntennaNoAdjust" "false")
+absSetBinOption( "Block" "ExtractAntennaGate" "(poly (poly and diff)) ")
+absSetBinOption( "Block" "ExtractAntennaDrain" "(diff (diff andnot poly)) ")
+absSetBinOption( "Block" "ExtractAntennaOxide" "")
+absSetBinOption( "Block" "ExtractAntennaIncludepolyCAR" "false")
+absSetBinOption( "Block" "AbstractAntennaGSpecTable" "")
+absSetBinOption( "Block" "ExtractDiffAntennaLayers" "false")
+absSetBinOption( "Block" "ExtractAntennaLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 ")
+absSetBinOption( "Block" "ExtractAntennaGSpecTable" "")
+absSetBinOption( "Block" "ExtractAntennaExcludeNets" "")
+absSetBinOption( "Block" "ExtractCache" "false")
+absSetBinOption( "Block" "ExtractCacheGrid" "5")
+absSetBinOption( "Block" "ExtractCacheNumGrid" "50")
+absSetBinOption( "Block" "ExtractCacheUtil" "0")
+absSetBinOption( "Block" "ExtractCacheUtilPct" "30")
+absSetBinOption( "Block" "ExtractAdjustInitialPinShapes" "false")
+absSetBinOption( "Block" "ExtractUseNetInfo" "false")
+absSetBinOption( "Block" "ExtractConnectivity" "(met1 met2 via)(met2 met3 via2)(met3 met4 via3)(met4 met5 via4)")
+absSetBinOption( "Block" "AbstractAdjustAllowPin" "")
+absSetBinOption( "Block" "AbstractAdjustAvoidPin" "")
+absSetBinOption( "Block" "AbstractAdjustPinLPPsGTable" "")
+absSetBinOption( "Block" "AbstractAdjustBoundaryPinsSig" "true")
+absSetBinOption( "Block" "AbstractAdjustBoundaryPinsSigDist" "")
+absSetBinOption( "Block" "AbstractAdjustSignalGeometryGroups" "overlap")
+absSetBinOption( "Block" "AbstractAdjustSignalGeometryGroupsEastWest" "overlap")
+absSetBinOption( "Block" "AbstractAdjustBoundaryPinsPwr" "false")
+absSetBinOption( "Block" "AbstractAdjustBoundaryPinsPwrDist" "")
+absSetBinOption( "Block" "AbstractAdjustRingPinsPwr" "false")
+absSetBinOption( "Block" "AbstractAdjustRingPinsDist" "")
+absSetBinOption( "Block" "AbstractAdjustFollowRingPin" "false")
+absSetBinOption( "Block" "AbstractAdjustPowerGeometryGroups" "single")
+absSetBinOption( "Block" "AbstractAdjustPowerGeometryGroupsEastWest" "overlap")
+absSetBinOption( "Block" "AbstractAdjustPowerRailOp" "")
+absSetBinOption( "Block" "AbstractAdjustPowerRailOpTable" "")
+absSetBinOption( "Block" "AbstractAdjustPowerRailWidth" "0")
+absSetBinOption( "Block" "AbstractAdjustEdgeTowardsCore" "north")
+absSetBinOption( "Block" "AbstractAdjustClassCoreNets" "^((V(DD|CC))|(v(dd|cc)))(!)?$")
+absSetBinOption( "Block" "AbstractAdjustIncludeAllShapes" "false")
+absSetBinOption( "Block" "AbstractAdjustCopyClassCorePort" "false")
+absSetBinOption( "Block" "AbstractAdjustPinsTouchBoundary" "false")
+absSetBinOption( "Block" "AbstractAdjustPinsTouchNonCoreEdge" "true")
+absSetBinOption( "Block" "AbstractAdjustCreateClassBumpPort" "false")
+absSetBinOption( "Block" "AbstractAdjustPreserveViasPwr" "false")
+absSetBinOption( "Block" "AbstractAdjustDuplicatePinShapes" "false")
+absSetBinOption( "Block" "AbstractBlockageLayerOrder" "false")
+absSetBinOption( "Block" "AbstractBlockageDetailedLayers" "")
+absSetBinOption( "Block" "AbstractBlockageCoverLayers" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "AbstractBlockageShrinkWrapLayers" "")
+absSetBinOption( "Block" "AbstractBlockageCoverLayersDist" "")
+absSetBinOption( "Block" "AbstractBlockageShrinkTracks" "")
+absSetBinOption( "Block" "AbstractBlockageShrinkAdjust" "")
+absSetBinOption( "Block" "AbstractBlockagePinCutWindow" "")
+absSetBinOption( "Block" "AbstractBlockageCutForAboveLayers" "")
+absSetBinOption( "Block" "AbstractBlockageDownPinCutWindow" "")
+absSetBinOption( "Block" "AbstractBlockageCutAroundPin" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "AbstractBlockageMaxRoutingSpace" "")
+absSetBinOption( "Block" "AbstractBlockageCorridorCut" "")
+absSetBinOption( "Block" "AbstractBlockageTable" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "BlockageCutVia" "true")
+absSetBinOption( "Block" "AbstractZeroSpacingBlockage" "false")
+absSetBinOption( "Block" "BlockageLargeShapePct" "10")
+absSetBinOption( "Block" "BlockageLargeShape" "true")
+absSetBinOption( "Block" "BlockageLargePurposeList" "boundary")
+absSetBinOption( "Block" "AbstractBlockageEXCEPTPGNET" "")
+absSetBinOption( "Block" "AbstractBlockageUserDefinedSpacing" "")
+absSetBinOption( "Block" "AbstractBlockageUserDefinedWidth" "")
+absSetBinOption( "Block" "AbstractBlockageUserDefinedDistanceForAddBack" "")
+absSetBinOption( "Block" "AbstractBlockageRoutingChannelOnLayers" "")
+absSetBinOption( "Block" "AbstractTopLayerCoverBlockage" "")
+absSetBinOption( "Block" "AbstractDensity" "false")
+absSetBinOption( "Block" "AbstractDensityUseSignalLayers" "false")
+absSetBinOption( "Block" "AbstractDensityUseAntennaLayers" "false")
+absSetBinOption( "Block" "AbstractDensityUsePwrLayers" "false")
+absSetBinOption( "Block" "AbstractDensityLayers" "met1 met2 met3 met4 met5 ")
+absSetBinOption( "Block" "AbstractDensityTable" "")
+absSetBinOption( "Block" "AbstractDensityWindowWidth" "")
+absSetBinOption( "Block" "AbstractDensityWindowHeight" "")
+absSetBinOption( "Block" "AbstractDensityDefaultWindowWidth" "20")
+absSetBinOption( "Block" "AbstractDensityDefaultWindowHeight" "20")
+absSetBinOption( "Block" "AbstractPinFracture" "false")
+absSetBinOption( "Block" "AbstractBlockageFracture" "false")
+absSetBinOption( "Block" "AbstractAdjustStairStepCover" "partial")
+absSetBinOption( "Block" "AbstractAdjustStairStepWidth" "0.024")
+absSetBinOption( "Block" "AbstractSiteName" "")
+absSetBinOption( "Block" "AbstractSiteNameDefine" "")
+absSetBinOption( "Block" "AbstractSiteArrayPattern" "false")
+absSetBinOption( "Block" "AbstractSiteArrayCells" "")
+absSetBinOption( "Block" "AbstractSiteArrayCellsTable" "")
+absSetBinOption( "Block" "AbstractOverlapLayerAction" "off")
+absSetBinOption( "Block" "AbstractOverlapLayers" "met1 met2 met3 met4 met5 via via2 via3 via4 poly diff nwell ")
+absSetBinOption( "Block" "AbstractOverlapLayerSize" "0")
+absSetBinOption( "Block" "AbstractOverlapLayerSmoothFactor" "100")
+absSetBinOption( "Block" "AbstractGridMode" "off")
+absSetBinOption( "Block" "AbstractUpdateTechFile" "false")
+absSetBinOption( "Block" "AbstractMetal1Pitch" "0.05")
+absSetBinOption( "Block" "AbstractMetal1Offset" "0")
+absSetBinOption( "Block" "AbstractMetal2Pitch" "0.05")
+absSetBinOption( "Block" "AbstractMetal2Offset" "0")
+absSetBinOption( "Block" "AbstractMetal3Pitch" "0.05")
+absSetBinOption( "Block" "AbstractMetal3Offset" "0")
+absSetBinOption( "Block" "AbstractMetal1PitchPercent" "50")
+absSetBinOption( "Block" "AbstractMetal2PitchPercent" "50")
+absSetBinOption( "Block" "AbstractMetal3PitchPercent" "50")
+absSetBinOption( "Block" "AbstractPinAccessMode" "narrowPin")
+absSetBinOption( "Block" "AbstractDiagonalVias" "false")
+absSetBinOption( "Block" "AbstractGridDistanceMetric" "euclidean")
+absSetBinOption( "Block" "AbstractRetainLayout" "false")
+absSetBinOption( "Block" "AbstractPinStretchOutPrb" "false")
+absSetBinOption( "Block" "VerifyTerminals" "true")
+absSetBinOption( "Block" "VerifyRowSpacing" "0")
+absSetBinOption( "Block" "VerifyGrid" "true")
+absSetBinOption( "Block" "VerifyTarget" "true")
+absSetBinOption( "Block" "VerifyTargetSelection" "Silicon Ensemble")
+absSetBinOption( "Block" "TargetSystemCMD" "sedsm -m=96 -gd=ansi")
+absSetBinOption( "Block" "VerifyEncounterPromptRegEx" "encounter$")
+absSetBinOption( "Block" "VerifyTargetRowDirection" "horizontal")
+absSetBinOption( "Block" "VerifyTechFile" "")
+absSetBinOption( "Block" "VerifyTargetMultiple" "false")
+absSetBinOption( "Block" "VerifyTargetMultipleRows" "false")
+absSetBinOption( "Block" "VerifyTargetPower" "true")
+absSetBinOption( "Block" "VerifySrouteConfigFile" "")
+absSetBinOption( "Block" "VerifyTargetRouter" "Nanoroute")
+absSetBinOption( "Block" "VerifyTargetMaxRouteTime" "1")
+absSetBinOption( "Block" "VerifyConfigFile" "")
+absSetBinOption( "Block" "VerifyTargetGeom" "")
+absSetBinOption( "Block" "VerifyTargetIgnore" "EXCHANGEFORMATS-USER-525\nEXCHANGEFORMATS-USER-392\nEXCHANGEFORMATS-USER-34\nno clock net\nCannot determine standard cell height")
+
+absDeselectBin("Ignore" )
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; End Abstract Options File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
diff --git a/calibre_setup/.cgidrcdb b/calibre_setup/.cgidrcdb
new file mode 120000
index 0000000..eb1c2f4
--- /dev/null
+++ b/calibre_setup/.cgidrcdb
@@ -0,0 +1 @@
+drc.runset
\ No newline at end of file
diff --git a/calibre_setup/.cgilvsdb b/calibre_setup/.cgilvsdb
new file mode 120000
index 0000000..6762b6d
--- /dev/null
+++ b/calibre_setup/.cgilvsdb
@@ -0,0 +1 @@
+lvs.runset
\ No newline at end of file
diff --git a/calibre_setup/.cgipexdb b/calibre_setup/.cgipexdb
new file mode 120000
index 0000000..7351f05
--- /dev/null
+++ b/calibre_setup/.cgipexdb
@@ -0,0 +1 @@
+rcx.svrf
\ No newline at end of file
diff --git a/calibre_setup/drc.runset b/calibre_setup/drc.runset
new file mode 100644
index 0000000..7908bef
--- /dev/null
+++ b/calibre_setup/drc.runset
@@ -0,0 +1,28 @@
+*drcRulesFile: ${PDK_HOME}/DRC/Calibre/s8_drcRules
+*drcRunDir: ${BAG_WORK_DIR}/calibre_run/drc/myLib/myCell
+*drcLayoutPaths: myCell.calibre.db
+*drcLayoutPrimary: myCell
+*drcLayoutLibrary: myLib
+*drcLayoutView: layout
+*drcLayoutGetFromViewer: 1
+*drcResultsFile: myCell.drc.results
+*drcIncludeCmdsType: SVRF
+*drcSVRFCmds: {DRC KEEP EMPTY NO} {} {} {} {} {} {}
+*drcSummaryFile: myCell.drc.summary
+*drcViewSummary: 0
+*drcDFMDefaultsResultsFile: aib_mstr.dfmDefaults.db
+*cmnWarnLayoutOverwrite: 0
+*cmnPromptSaveRunset: 0
+*cmnShowOptions: 1
+*cmnSaveRunsetChanges: 0
+*cmnVConnectColon: 1
+*cmnDontWaitForLicense: 0
+*cmnRunMT: 1
+*cmnRunHyper: 1
+*cmnTemplate_RN: $BAG_WORK_DIR/calibre_run/drc/%L/%l
+*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
+*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnFDILayoutLibrary: myLib
+*cmnFDILayoutView: layout
+*cmnFDIDEFLayoutPath: myCell.def
diff --git a/calibre_setup/drc.svrf b/calibre_setup/drc.svrf
new file mode 100644
index 0000000..f65cdad
--- /dev/null
+++ b/calibre_setup/drc.svrf
@@ -0,0 +1,18 @@
+LAYOUT PATH "{{ layout_file }}"
+LAYOUT PRIMARY "{{ cell_name }}"
+LAYOUT SYSTEM {{layout_type}}
+
+DRC RESULTS DATABASE "{{ cell_name }}.drc.results" ASCII
+DRC MAXIMUM RESULTS 1000
+DRC MAXIMUM VERTEX 4096
+DRC KEEP EMPTY NO
+
+DRC CELL NAME YES CELL SPACE XFORM
+DRC SUMMARY REPORT "{{ cell_name }}.drc.summary" REPLACE HIER
+
+VIRTUAL CONNECT COLON YES
+VIRTUAL CONNECT REPORT NO
+
+DRC ICSTATION YES
+
+INCLUDE "$PDK_HOME/DRC/Calibre/s8_drcRules"
diff --git a/calibre_setup/lvs.runset b/calibre_setup/lvs.runset
new file mode 100644
index 0000000..c1a94bf
--- /dev/null
+++ b/calibre_setup/lvs.runset
@@ -0,0 +1,39 @@
+*lvsRulesFile: ${PDK_HOME}/LVS/Calibre/lvs_s8_opts
+*lvsRunDir: ${BAG_WORK_DIR}/calibre_run/lvs/myLib/top_cell
+*lvsLayoutPaths: top_cell.calibre.db
+*lvsLayoutPrimary: top_cell
+*lvsLayoutLibrary: myLib
+*lvsLayoutView: layout
+*lvsLayoutGetFromViewer: 1
+*lvsSourcePath: top_cell.src.net
+*lvsSourcePrimary: top_cell
+*lvsSourceLibrary: myLib
+*lvsSourceView: schematic
+*lvsSourceGetFromViewer: 1
+*lvsSpiceFile: top_cell.sp
+*lvsPowerNames: VDD
+*lvsGroundNames: VSS
+*lvsRecognizeGates: NONE
+*lvsConfigureSplitGates: 1
+*lvsReduceSplitGates: 0
+*lvsERCDatabase: top_cell.erc.results
+*lvsERCSummaryFile: top_cell.erc.summary
+*lvsReportFile: top_cell.lvs.report
+*lvsViewReport: 0
+*lvsSVDBcci: 1
+*lvsSVDBxcal: 1
+*lvsSVDBtxref: 1
+*lvsSVDBnopinloc: 1
+*cmnWarnLayoutOverwrite: 0
+*cmnWarnSourceOverwrite: 0
+*cmnPromptSaveRunset: 0
+*cmnShowOptions: 1
+*cmnSaveRunsetChanges: 0
+*cmnVConnectColon: 1
+*cmnTemplate_RN: $BAG_WORK_DIR/calibre_run/lvs/%L/%l
+*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
+*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnFDILayoutLibrary: myLib
+*cmnFDILayoutView: layout
+*cmnFDIDEFLayoutPath: top_cell.def
diff --git a/calibre_setup/lvs.svrf b/calibre_setup/lvs.svrf
new file mode 100644
index 0000000..4b22c1b
--- /dev/null
+++ b/calibre_setup/lvs.svrf
@@ -0,0 +1,51 @@
+LAYOUT PATH "{{ layout_file }}"
+LAYOUT PRIMARY "{{ cell_name }}"
+LAYOUT SYSTEM {{layout_type}}
+
+SOURCE PATH "{{ netlist_file }}"
+SOURCE PRIMARY "{{ cell_name }}"
+SOURCE SYSTEM SPICE
+
+MASK SVDB DIRECTORY "svdb" QUERY XRC
+
+LVS REPORT "{{ cell_name }}.lvs.report"
+
+LVS REPORT OPTION NONE
+LVS FILTER UNUSED OPTION NONE SOURCE
+LVS FILTER UNUSED OPTION NONE LAYOUT
+LVS FILTER R(SH) SHORT SOURCE
+LVS REPORT MAXIMUM 50
+LVS POWER NAME VDD
+LVS GROUND NAME VSS
+
+LVS RECOGNIZE GATES NONE
+
+LVS REDUCE SPLIT GATES NO
+LVS REDUCE PARALLEL MOS YES
+LVS SHORT EQUIVALENT NODES NO
+
+LVS ABORT ON SOFTCHK NO
+LVS ABORT ON SUPPLY ERROR YES
+LVS IGNORE PORTS NO
+LVS SHOW SEED PROMOTIONS NO
+LVS SHOW SEED PROMOTIONS MAXIMUM 50
+
+LVS ISOLATE SHORTS NO
+
+VIRTUAL CONNECT COLON YES
+VIRTUAL CONNECT REPORT NO
+
+LVS EXECUTE ERC YES
+ERC RESULTS DATABASE "{{ cell_name }}.erc.results"
+ERC SUMMARY REPORT "{{ cell_name }}.erc.summary" REPLACE HIER
+ERC CELL NAME YES CELL SPACE XFORM
+ERC MAXIMUM RESULTS 1000
+ERC MAXIMUM VERTEX 4096
+
+DRC ICSTATION YES
+
+PEX POWER LAYOUT VDD
+PEX GROUND LAYOUT VSS
+PEX REDUCE ANALOG NO
+
+INCLUDE "$PDK_HOME/LVS/Calibre/lvs_s8_opts"
diff --git a/calibre_setup/lvs_adc.runset b/calibre_setup/lvs_adc.runset
new file mode 100644
index 0000000..cdac099
--- /dev/null
+++ b/calibre_setup/lvs_adc.runset
@@ -0,0 +1,40 @@
+*lvsRulesFile: ${PDK_HOME}/LVS/Calibre/lvs_s8_opts
+*lvsRunDir: $BAG_WORK_DIR/calibre_run/lvs/AAA_SAR_lay/AAA_Slice
+*lvsLayoutPaths: /tools/B/felicia_guo/bag3-sky130-2/calibre_run/lvs/AAA_SAR_lay/AAA_Slice/layout.gds
+*lvsLayoutPrimary: AAA_Slice
+*lvsLayoutLibrary: AAA_SAR_lay
+*lvsLayoutView: layout
+*lvsSourcePath: /tools/B/felicia_guo/bag3-sky130-2/gen_outputs/bag_sar/AAA_Slice.cdl
+*lvsSourcePrimary: AAA_Slice
+*lvsSourceLibrary: AAA_SAR_lay
+*lvsSourceView: schematic
+*lvsSpiceFile: AAA_Slice.sp
+*lvsPowerNames: VDD
+*lvsGroundNames: VSS
+*lvsRecognizeGates: NONE
+*lvsConfigureSplitGates: 1
+*lvsReduceSplitGates: 0
+*lvsERCDatabase: AAA_Slice.erc.results
+*lvsERCSummaryFile: AAA_Slice.erc.summary
+*lvsIncludeSVRFCmds: 1
+*lvsSVRFCmds: {LVS FILTER R(SH) SHORT SOURCE} {}
+*lvsReportFile: AAA_Slice.lvs.report
+*lvsViewReport: 0
+*lvsSVDBxcal: 1
+*lvsSVDBcci: 1
+*lvsSVDBtxref: 1
+*lvsSVDBnopinloc: 1
+*lvsMaskDBFile: AAA_Slice.maskdb
+*cmnWarnLayoutOverwrite: 0
+*cmnWarnSourceOverwrite: 0
+*cmnPromptSaveRunset: 0
+*cmnShowOptions: 1
+*cmnSaveRunsetChanges: 0
+*cmnVConnectColon: 1
+*cmnTemplate_RN: $BAG_WORK_DIR/calibre_run/lvs/%L/%l
+*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
+*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
+*cmnFDILayoutLibrary: AAA_SAR_lay
+*cmnFDILayoutView: layout
+*cmnFDIDEFLayoutPath: AAA_Slice.def
diff --git a/calibre_setup/rcx.svrf b/calibre_setup/rcx.svrf
new file mode 100644
index 0000000..8a27455
--- /dev/null
+++ b/calibre_setup/rcx.svrf
@@ -0,0 +1,108 @@
+LAYOUT PATH "{{ layout_file }}"
+LAYOUT PRIMARY "{{ cell_name }}"
+LAYOUT SYSTEM {{layout_type}}
+
+SOURCE PATH "{{ netlist_file }}"
+SOURCE PRIMARY "{{ cell_name }}"
+SOURCE SYSTEM SPICE
+
+LAYOUT CASE YES
+SOURCE CASE YES
+LVS COMPARE CASE YES
+
+MASK SVDB DIRECTORY "svdb" QUERY XRC
+
+LVS REPORT "{{ cell_name }}.rcx.report"
+
+LVS REPORT OPTION NONE
+LVS FILTER UNUSED OPTION NONE SOURCE
+LVS FILTER UNUSED OPTION NONE LAYOUT
+LVS FILTER R(SH) SHORT SOURCE
+LVS FILTER R(SH) SHORT LAYOUT
+LVS REPORT MAXIMUM 50
+LVS POWER NAME VDD
+LVS GROUND NAME VSS
+
+LVS RECOGNIZE GATES NONE
+
+LVS REDUCE SPLIT GATES NO
+LVS REDUCE PARALLEL MOS YES
+LVS SHORT EQUIVALENT NODES NO
+
+LVS ABORT ON SOFTCHK NO
+LVS ABORT ON SUPPLY ERROR YES
+LVS IGNORE PORTS NO
+LVS SHOW SEED PROMOTIONS NO
+LVS SHOW SEED PROMOTIONS MAXIMUM 50
+
+LVS ISOLATE SHORTS NO
+
+VIRTUAL CONNECT COLON YES
+VIRTUAL CONNECT REPORT NO
+
+LVS EXECUTE ERC YES
+ERC RESULTS DATABASE "{{ cell_name }}.erc.results"
+ERC SUMMARY REPORT "{{ cell_name }}.erc.summary" REPLACE HIER
+ERC CELL NAME YES CELL SPACE XFORM
+ERC MAXIMUM RESULTS 1000
+ERC MAXIMUM VERTEX 4096
+
+DRC ICSTATION YES
+
+// S8 specific features
+
+UNIT CAPACITANCE ff
+
+// Filter Devices in include file to give LVS & xRC consistency
+
+LVS FILTER R(cds_thru) SHORT SOURCE
+LVS FILTER R(cds_thru) SHORT LAYOUT
+
+LVS FILTER Dpar OPEN SOURCE
+LVS FILTER Dpar OPEN LAYOUT
+LVS FILTER Dpar(DNWDIODE_PW) OPEN SOURCE
+LVS FILTER Dpar(DNWDIODE_PW) OPEN LAYOUT
+
+LVS FILTER Probe OPEN SOURCE
+LVS FILTER Probe OPEN LAYOUT
+
+LVS Filter icecap open source
+
+LVS Filter s8fmlt_iref_termx open source
+LVS Filter s8fmlt_neg_termx open source
+LVS Filter s8fmlt_termx open source
+LVS Filter s8fmlt_vdac_termx open source
+
+//# diff/tap devices
+
+LVS FILTER diff_dev OPEN SOURCE
+LVS FILTER diff_dev OPEN LAYOUT
+LVS FILTER tap_dev OPEN SOURCE
+LVS FILTER tap_dev OPEN LAYOUT
+
+//# dummy device to prevent empty cells from becoming subckt primitives
+
+LVS FILTER cad_dummy_open_device OPEN SOURCE
+LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+// Custom netlist settings
+PEX REDUCE MINRES SHORT 0.000001
+PEX POWER LAYOUT VDD
+PEX GROUND LAYOUT VSS
+
+// Include to filter out shorts from current summer
+PEX NETLIST FILTER R(SH) SOURCE SHORT
+PEX NETLIST FILTER R(SH) LAYOUT SHORT
+
+PEX NETLIST FILTER R(cds_thru) SOURCE SHORT
+PEX NETLIST FILTER R(cds_thru) LAYOUT SHORT
+
+// DSPF
+// Configure to use DPSF to match other BAG extraction methods
+PEX NETLIST {{ cell_name }}.spf DSPF SOURCEBASED
+
+// Spectre
+//PEX NETLIST {{ cell_name }}.pex.netlist SPECTRE SOURCEBASED
+
+INCLUDE "$PDK_HOME/PEX/xRC/cap_models"
+INCLUDE "$PDK_HOME/PEX/xRC/extLvsRules_s8_5lm"
diff --git a/calibre_setup/source.added b/calibre_setup/source.added
new file mode 120000
index 0000000..09f6adb
--- /dev/null
+++ b/calibre_setup/source.added
@@ -0,0 +1 @@
+../workspace_setup/PDK/LVS/Calibre/source.cdl
\ No newline at end of file
diff --git a/corners_setup.yaml b/corners_setup.yaml
new file mode 100644
index 0000000..d6ab6eb
--- /dev/null
+++ b/corners_setup.yaml
@@ -0,0 +1,46 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+tt:
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_fet']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_cell']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_parRC']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_rc']
+ff:
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'ff_fet']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'ff_cell']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_parRC']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_rc']
+ss:
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'ss_fet']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'ss_cell']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_parRC']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_rc']
+sf:
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'sf_fet']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'sf_cell']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_parRC']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_rc']
+fs:
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'fs_fet']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'fs_cell']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_parRC']
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'tt_rc']
+mc:
+ - !!python/tuple ['${BAG_TECH_CONFIG_DIR}/workspace_setup/PDK/MODELS/SPECTRE/s8phirs_10r/Models/design_wrapper.lib.scs', 'mc']
diff --git a/docs/code-of-conduct.rst b/docs/code-of-conduct.rst
new file mode 100644
index 0000000..3c58179
--- /dev/null
+++ b/docs/code-of-conduct.rst
@@ -0,0 +1,68 @@
+Google Open Source Community Guidelines
+---------------------------------------
+
+.. community_guidelines_text
+
+At Google, we recognize and celebrate the creativity and collaboration
+of open source contributors and the diversity of skills, experiences,
+cultures, and opinions they bring to the projects and communities they
+participate in.
+
+Every one of Google's open source projects and communities are inclusive
+environments, based on treating all individuals respectfully, regardless
+of gender identity and expression, sexual orientation, disabilities,
+neurodiversity, physical appearance, body size, ethnicity, nationality,
+race, age, religion, or similar personal characteristic.
+
+We value diverse opinions, but we value respectful behavior more.
+
+Respectful behavior includes:
+
+- Being considerate, kind, constructive, and helpful.
+- Not engaging in demeaning, discriminatory, harassing, hateful,
+ sexualized, or physically threatening behavior, speech, and imagery.
+- Not engaging in unwanted physical contact.
+
+Some Google open source projects
+`may adopt <https://opensource.google/docs/releasing/preparing/#conduct>`__
+an explicit project code of conduct, which may have additional detailed
+expectations for participants. Most of those projects will use our
+`modified Contributor Covenant <https://opensource.google/docs/releasing/template/CODE_OF_CONDUCT/>`__.
+
+Resolve peacefully
+~~~~~~~~~~~~~~~~~~
+
+We do not believe that all conflict is necessarily bad; healthy debate
+and disagreement often yields positive results. However, it is never
+okay to be disrespectful.
+
+If you see someone behaving disrespectfully, you are encouraged to
+address the behavior directly with those involved. Many issues can be
+resolved quickly and easily, and this gives people more control over the
+outcome of their dispute. If you are unable to resolve the matter for
+any reason, or if the behavior is threatening or harassing, report it.
+We are dedicated to providing an environment where participants feel
+welcome and safe.
+
+Reporting problems
+~~~~~~~~~~~~~~~~~~
+
+Some Google open source projects may adopt a project-specific code of
+conduct. In those cases, a Google employee will be identified as the
+Project Steward, who will receive and handle reports of code of conduct
+violations. In the event that a project hasn’t identified a Project
+Steward, you can report problems by emailing opensource@google.com.
+
+We will investigate every complaint, but you may not receive a direct
+response. We will use our discretion in determining when and how to
+follow up on reported incidents, which may range from not taking action
+to permanent expulsion from the project and project-sponsored spaces. We
+will notify the accused of the report and provide them an opportunity to
+discuss it before any action is taken. The identity of the reporter will
+be omitted from the details of the report supplied to the accused. In
+potentially harmful situations, such as ongoing harassment or threats to
+anyone's safety, we may take action without notice.
+
+*This document was adapted from the*
+`IndieWeb Code of Conduct <https://indieweb.org/code-of-conduct>`_
+*and can also be found at* <https://opensource.google/conduct/>.
diff --git a/docs/contributing.rst b/docs/contributing.rst
new file mode 100644
index 0000000..14f6b0f
--- /dev/null
+++ b/docs/contributing.rst
@@ -0,0 +1,36 @@
+How to Contribute
+=================
+
+We'd love to accept your patches and contributions to this project.
+There are just a few small guidelines you need to follow.
+
+Contributor License Agreement
+-----------------------------
+
+Contributions to this project must be accompanied by a Contributor
+License Agreement. You (or your employer) retain the copyright to your
+contribution; this simply gives us permission to use and redistribute
+your contributions as part of the project. Head over to
+https://cla.developers.google.com/ to see your current agreements on
+file or to sign a new one.
+
+You generally only need to submit a CLA once, so if you've already
+submitted one (even if it was for a different project), you probably
+don't need to do it again.
+
+Code reviews
+------------
+
+All submissions, including submissions by project members, require
+review. We use GitHub pull requests for this purpose. Consult `GitHub
+Help <https://help.github.com/articles/about-pull-requests/>`__ for more
+information on using pull requests.
+
+Community Guidelines
+--------------------
+
+This project follows `Google's Open Source Community
+Guidelines <https://opensource.google/conduct/>`__.
+
+.. include:: code-of-conduct.rst
+ :start-after: community_guidelines_text
diff --git a/docs/images/loadtech.png b/docs/images/loadtech.png
new file mode 100644
index 0000000..b58980b
--- /dev/null
+++ b/docs/images/loadtech.png
Binary files differ
diff --git a/docs/images/savetech.png b/docs/images/savetech.png
new file mode 100644
index 0000000..302bebe
--- /dev/null
+++ b/docs/images/savetech.png
Binary files differ
diff --git a/docs/images/techman.png b/docs/images/techman.png
new file mode 100644
index 0000000..ca9e063
--- /dev/null
+++ b/docs/images/techman.png
Binary files differ
diff --git a/docs/license_header.txt b/docs/license_header.txt
new file mode 100644
index 0000000..5c5e95e
--- /dev/null
+++ b/docs/license_header.txt
@@ -0,0 +1,19 @@
+Copyright 2019-2021 SkyWater PDK Authors
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ https://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+This code is *alternatively* available under a BSD-3-Clause license, see
+details in the README.md at the top level and the license text at
+https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+
+SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
diff --git a/gds_setup/gds.layermap b/gds_setup/gds.layermap
new file mode 120000
index 0000000..33813b1
--- /dev/null
+++ b/gds_setup/gds.layermap
@@ -0,0 +1 @@
+../workspace_setup/PDK/VirtuosoOA/libs/s8phirs_10r/s8phirs_10r.layermap
\ No newline at end of file
diff --git a/gds_setup/gds.objectmap b/gds_setup/gds.objectmap
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/gds_setup/gds.objectmap
diff --git a/install.sh b/install.sh
new file mode 100755
index 0000000..c08290e
--- /dev/null
+++ b/install.sh
@@ -0,0 +1,90 @@
+#!/bin/bash
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+#!/usr/bin/env bash
+
+export TECH_DIR="skywater130"
+export ROOT_DIR="${TECH_DIR}/workspace_setup"
+
+# files to copy from workspace_setup
+cp_files=( ".cdsenv.personal"
+ ".cdsinit.personal"
+ "bag_submodules.yaml" )
+
+# files to link from workspace_setup
+ln_files=( "bag_config.yaml"
+ ".cdsenv"
+ ".cdsinit"
+ ".simrc"
+ ".bashrc"
+ ".bashrc_bag"
+ "cds.lib.core"
+ "display.drf"
+ "models"
+ ".gitignore"
+ "leBindKeys.il" )
+
+# user configuration files; copy
+for f in "${cp_files[@]}"; do
+ cp ${ROOT_DIR}/${f} .
+ git add -f ${f}
+done
+
+# standard configuration files; symlink
+for f in "${ln_files[@]}"; do
+ ln -s ${ROOT_DIR}/${f} .
+ git add -f ${f}
+done
+
+# setup .ipython
+export CUR_DIR=".ipython/profile_default"
+mkdir -p ${CUR_DIR}
+ln -s "../../${ROOT_DIR}/ipython_config.py" "${CUR_DIR}/ipython_config.py"
+git add -f ${CUR_DIR}/ipython_config.py
+
+# setup gen_libs folder
+mkdir gen_libs
+touch gen_libs/.gitignore
+git add -f gen_libs/.gitignore
+
+# setup cds.lib
+echo 'INCLUDE $BAG_WORK_DIR/cds.lib.core' > cds.lib
+
+# link BAG run scripts
+ln -s BAG_framework/run_scripts/start_bag_ICADV12d3.il start_bag.il
+ln -s BAG_framework/run_scripts/start_bag.sh .
+ln -s BAG_framework/run_scripts/run_bag.sh .
+ln -s BAG_framework/run_scripts/gen_cell.sh .
+ln -s BAG_framework/run_scripts/sim_cell.sh .
+ln -s BAG_framework/run_scripts/meas_cell.sh .
+ln -s BAG_framework/run_scripts/run_em_cell.sh .
+ln -s BAG_framework/run_scripts/extract_cell.sh .
+ln -s BAG_framework/run_scripts/dsn_cell.sh .
+ln -s BAG_framework/run_scripts/virt_server.sh .
+ln -s BAG_framework/run_scripts/setup_submodules.py .
+git add start_bag.il
+git add start_bag.sh
+git add run_bag.sh
+git add virt_server.sh
+git add setup_submodules.py
+
+ln -s ${BAG_TEMP_DIR}/simulations/gen_outputs gen_outputs_scratch
+ln -s ${BAG_TEMP_DIR}/calibre_run calibre_run
diff --git a/netlist_setup/bag_prim.cdl b/netlist_setup/bag_prim.cdl
new file mode 100644
index 0000000..bce1250
--- /dev/null
+++ b/netlist_setup/bag_prim.cdl
@@ -0,0 +1,124 @@
+* Copyright 2019-2021 SkyWater PDK Authors
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* This code is *alternatively* available under a BSD-3-Clause license, see
+* details in the README.md at the top level and the license text at
+* https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+*
+* SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+.SUBCKT nmos4_hv B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B nhv l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT nmos4_hvesd B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B nhvesd l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT nmos4_svt B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B nshort l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT nmos4_lvt B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B nlowvt l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT nmos4_standard B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B nshort l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT pmos4_hv B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B phv l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT pmos4_hvesd B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B phvesd l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT pmos4_svt B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B pshort l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT pmos4_lvt B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B plowvt l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT pmos4_hvt B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B phighvt l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT pmos4_standard B D G S
+*.PININFO B:B D:B G:B S:B
+MM0 D G S B pshort l=l*1.0e6 w=w*1.0e6 m=nf mult=1
+.ENDS
+
+.SUBCKT res_metal_1 MINUS PLUS
+*.PININFO MINUS:B PLUS:B
+RR0 PLUS MINUS mrm1 m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT res_metal_2 MINUS PLUS
+*.PININFO MINUS:B PLUS:B
+RR0 PLUS MINUS mrm2 m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT res_metal_3 MINUS PLUS
+*.PININFO MINUS:B PLUS:B
+RR0 PLUS MINUS mrm3 m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT res_metal_4 MINUS PLUS
+*.PININFO MINUS:B PLUS:B
+RR0 PLUS MINUS mrm4 m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT res_metal_5 MINUS PLUS
+*.PININFO MINUS:B PLUS:B
+RR0 PLUS MINUS mrm5 m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT res_standard BULK MINUS PLUS
+*.PININFO BULK:B MINUS:B PLUS:B
+xR0 PLUS MINUS BULK xhrpoly m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT res_high_res BULK MINUS PLUS
+*.PININFO BULK:B MINUS:B PLUS:B
+xR0 PLUS MINUS BULK xuhrpoly m=1 w=w*1.0e6 l=l*1.0e6
+.ENDS
+
+.SUBCKT mim_standard BOT TOP
+*.PININFO BOT:B TOP:B
+CC0 TOP BOT xcmimc2 w=unit_width*1.0e6 l=unit_height*1.0e6 m=num_rows*num_cols
+.ENDS
+
+.SUBCKT mim_45 BOT TOP
+*.PININFO BOT:B TOP:B
+CC0 TOP BOT xcmimc2 w=unit_width*1.0e6 l=unit_height*1.0e6 m=num_rows*num_cols
+.ENDS
+
+.SUBCKT mim_34 BOT TOP
+*.PININFO BOT:B TOP:B
+CC0 TOP BOT xcmimc1 w=unit_width*1.0e6 l=unit_height*1.0e6 m=num_rows*num_cols
+.ENDS
diff --git a/netlist_setup/bag_prim.scs b/netlist_setup/bag_prim.scs
new file mode 100644
index 0000000..d757b78
--- /dev/null
+++ b/netlist_setup/bag_prim.scs
@@ -0,0 +1,110 @@
+
+subckt nmos4_hv B D G S
+parameters l w nf
+MM0 D G S B nhv l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends nmos4_hv
+
+subckt nmos4_hvesd B D G S
+parameters l w nf
+MM0 D G S B nhvesd l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends nmos4_hvesd
+
+subckt nmos4_svt B D G S
+parameters l w nf
+MM0 D G S B nshort l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends nmos4_svt
+
+subckt nmos4_lvt B D G S
+parameters l w nf
+MM0 D G S B nlowvt l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends nmos4_lvt
+
+subckt nmos4_standard B D G S
+parameters l w nf
+MM0 D G S B nshort l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends nmos4_standard
+
+subckt pmos4_hv B D G S
+parameters l w nf
+MM0 D G S B phv l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends pmos4_hv
+
+subckt pmos4_hvesd B D G S
+parameters l w nf
+MM0 D G S B phvesd l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends pmos4_hvesd
+
+subckt pmos4_svt B D G S
+parameters l w nf
+MM0 D G S B pshort l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends pmos4_svt
+
+subckt pmos4_lvt B D G S
+parameters l w nf
+MM0 D G S B plowvt l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends pmos4_lvt
+
+subckt pmos4_hvt B D G S
+parameters l w nf
+MM0 D G S B phighvt l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends pmos4_hvt
+
+subckt pmos4_standard B D G S
+parameters l w nf
+MM0 D G S B pshort l=l * 1.0e6 w=w * 1.0e6 m=nf mult=1
+ends pmos4_standard
+
+subckt res_metal_1 MINUS PLUS
+parameters l w
+RR0 PLUS MINUS mrm1 w=w * 1.0e6 l=l * 1.0e6 m=1
+ends res_metal_1
+
+subckt res_metal_2 MINUS PLUS
+parameters l w
+RR0 PLUS MINUS mrm2 w=w * 1.0e6 l=l * 1.0e6 m=1
+ends res_metal_2
+
+subckt res_metal_3 MINUS PLUS
+parameters l w
+RR0 PLUS MINUS mrm3 w=w * 1.0e6 l=l * 1.0e6 m=1
+ends res_metal_3
+
+subckt res_metal_4 MINUS PLUS
+parameters l w
+RR0 PLUS MINUS mrm4 w=w * 1.0e6 l=l * 1.0e6 m=1
+ends res_metal_4
+
+subckt res_metal_5 MINUS PLUS
+parameters l w
+RR0 PLUS MINUS mrm5 w=w * 1.0e6 l=l * 1.0e6 m=1
+ends res_metal_5
+
+subckt res_standard BULK MINUS PLUS
+parameters l w
+RR0 PLUS MINUS BULK xhrpoly w=w * 1.0e6 l=l * 1.0e6 m=1 mult=1
+ends res_standard
+
+subckt res_high_res BULK MINUS PLUS
+parameters l w
+RR0 PLUS MINUS BULK xuhrpoly w=w * 1.0e6 l=l * 1.0e6 m=1 mult=1
+ends res_high_res
+
+subckt mim_standard BOT TOP
+parameters unit_width unit_height num_rows num_cols
+CC0 TOP BOT xcmimc2 w=unit_width * 1.0e6 l=unit_height * 1.0e6 m=num_rows * num_cols
+ends mim_standard
+
+subckt mim_45 BOT TOP
+parameters unit_width unit_height num_rows num_cols
+CC0 TOP BOT xcmimc2 w=unit_width * 1.0e6 l=unit_height * 1.0e6 m=num_rows * num_cols
+ends mim_45
+
+subckt mim_34 BOT TOP
+parameters unit_width unit_height num_rows num_cols
+CC0 TOP BOT xcmimc1 w=unit_width * 1.0e6 l=unit_height * 1.0e6 m=num_rows * num_cols
+ends mim_34
+
+subckt ideal_balun d c p n
+ K0 d 0 p c transformer n1=2
+ K1 d 0 c n transformer n1=2
+ends ideal_balun
diff --git a/netlist_setup/gen_config.yaml b/netlist_setup/gen_config.yaml
new file mode 100644
index 0000000..63f5931
--- /dev/null
+++ b/netlist_setup/gen_config.yaml
@@ -0,0 +1,115 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+header:
+ CDL:
+ includes: ["${BAG_TECH_CONFIG_DIR}/calibre_setup/source.added"]
+ SPECTRE:
+ includes: []
+ VERILOG:
+ includes: []
+ SYSVERILOG:
+ includes: []
+
+mos:
+ CDL:
+ - [l, l*1.0e6]
+ - [w, w*1.0e6]
+ - [m, nf]
+ - [mult, 1]
+ SPECTRE:
+ - [l, l * 1.0e6]
+ - [w, w * 1.0e6]
+ - [m, nf]
+ - [mult, 1]
+ VERILOG: []
+ SYSVERILOG: []
+ types:
+ - [nmos4_hv, nhv]
+ - [nmos4_hvesd, nhvesd]
+ - [nmos4_svt, nshort]
+ - [nmos4_lvt, nlowvt]
+ - [nmos4_standard, nshort]
+ - [pmos4_hv, phv]
+ - [pmos4_hvesd, phvesd]
+ - [pmos4_svt, pshort]
+ - [pmos4_lvt, plowvt]
+ - [pmos4_hvt, phighvt]
+ - [pmos4_standard, pshort]
+
+diode:
+ CDL: []
+ SPECTRE: []
+ VERILOG: []
+ SYSVERILOG: []
+ static: False
+ types: []
+ port_order: {}
+
+res_metal:
+ CDL:
+ - [m, 1]
+ - [w, w*1.0e6]
+ - [l, l*1.0e6]
+ SPECTRE:
+ - [w, w * 1.0e6]
+ - [l, l * 1.0e6]
+ - [m, 1]
+ VERILOG: []
+ SYSVERILOG: []
+ types:
+ - [res_metal_1, mrm1]
+ - [res_metal_2, mrm2]
+ - [res_metal_3, mrm3]
+ - [res_metal_4, mrm4]
+ - [res_metal_5, mrm5]
+
+res:
+ CDL:
+ - [m, 1]
+ - [w, w*1.0e6]
+ - [l, l*1.0e6]
+ SPECTRE:
+ - [w, w * 1.0e6]
+ - [l, l * 1.0e6]
+ - [m, 1]
+ - [mult, 1]
+ VERILOG: []
+ SYSVERILOG: []
+ types:
+ - [res_standard, xhrpoly]
+ - [res_high_res, xuhrpoly]
+ prefix:
+ CDL: 'x'
+
+mim:
+ CDL:
+ - [w, unit_width*1.0e6]
+ - [l, unit_height*1.0e6]
+ - [m, num_rows*num_cols]
+ SPECTRE:
+ - [w, unit_width * 1.0e6]
+ - [l, unit_height * 1.0e6]
+ - [m, num_rows * num_cols]
+ VERILOG: []
+ SYSVERILOG: []
+ types:
+ - [mim_standard, xcmimc2]
+ - [mim_45, xcmimc2]
+ - [mim_34, xcmimc1]
diff --git a/netlist_setup/netlist_setup.yaml b/netlist_setup/netlist_setup.yaml
new file mode 100644
index 0000000..ebceabf
--- /dev/null
+++ b/netlist_setup/netlist_setup.yaml
@@ -0,0 +1,682 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+inc_list:
+ 4: ['${BAG_TECH_CONFIG_DIR}/calibre_setup/source.added']
+ 5: []
+ 6: []
+ 7: []
+netlist_map:
+ BAG_prim:
+ mim_34:
+ cell_name: mim_34
+ in_terms: []
+ io_terms: [BOT, TOP]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ num_cols: [3, '']
+ num_rows: [3, '']
+ unit_height: [3, '']
+ unit_width: [3, '']
+ mim_45:
+ cell_name: mim_45
+ in_terms: []
+ io_terms: [BOT, TOP]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ num_cols: [3, '']
+ num_rows: [3, '']
+ unit_height: [3, '']
+ unit_width: [3, '']
+ mim_standard:
+ cell_name: mim_standard
+ in_terms: []
+ io_terms: [BOT, TOP]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ num_cols: [3, '']
+ num_rows: [3, '']
+ unit_height: [3, '']
+ unit_width: [3, '']
+ nmos4_hv:
+ cell_name: nmos4_hv
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ nmos4_hvesd:
+ cell_name: nmos4_hvesd
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ nmos4_lvt:
+ cell_name: nmos4_lvt
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ nmos4_standard:
+ cell_name: nmos4_standard
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ nmos4_svt:
+ cell_name: nmos4_svt
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ pmos4_hv:
+ cell_name: pmos4_hv
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ pmos4_hvesd:
+ cell_name: pmos4_hvesd
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ pmos4_hvt:
+ cell_name: pmos4_hvt
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ pmos4_lvt:
+ cell_name: pmos4_lvt
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ pmos4_standard:
+ cell_name: pmos4_standard
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ pmos4_svt:
+ cell_name: pmos4_svt
+ in_terms: []
+ io_terms: [B, D, G, S]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ nf: [3, '']
+ w: [3, '']
+ res_high_res:
+ cell_name: res_high_res
+ in_terms: []
+ io_terms: [BULK, MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ res_metal_1:
+ cell_name: res_metal_1
+ in_terms: []
+ io_terms: [MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ res_metal_2:
+ cell_name: res_metal_2
+ in_terms: []
+ io_terms: [MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ res_metal_3:
+ cell_name: res_metal_3
+ in_terms: []
+ io_terms: [MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ res_metal_4:
+ cell_name: res_metal_4
+ in_terms: []
+ io_terms: [MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ res_metal_5:
+ cell_name: res_metal_5
+ in_terms: []
+ io_terms: [MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ res_standard:
+ cell_name: res_standard
+ in_terms: []
+ io_terms: [BULK, MINUS, PLUS]
+ is_prim: true
+ lib_name: BAG_prim
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ w: [3, '']
+ ahdlLib:
+ comparator:
+ cell_name: comparator
+ in_terms: [sigin, sigref]
+ io_terms: []
+ is_prim: true
+ lib_name: ahdlLib
+ nets: []
+ out_terms: [sigout]
+ props:
+ comp_slope: [3, '']
+ sigin_offset: [3, '']
+ sigout_high: [3, '']
+ sigout_low: [3, '']
+ va: ${CDSHOME}/tools/dfII/samples/artist/ahdlLib/comparator/veriloga/veriloga.va
+ analogLib:
+ cap:
+ cell_name: cap
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ c: [3, '']
+ l: [3, '']
+ m: [3, '']
+ w: [3, '']
+ cccs:
+ cell_name: cccs
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ fgain: [3, '1.0']
+ maxm: [3, '']
+ minm: [3, '']
+ vref: [3, '']
+ ccvs:
+ cell_name: ccvs
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ hgain: [3, '1.0']
+ maxm: [3, '']
+ minm: [3, '']
+ vref: [3, '']
+ dcblock:
+ cell_name: dcblock
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ c: [3, 1u]
+ dcfeed:
+ cell_name: dcfeed
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ l: [3, 1u]
+ gnd:
+ cell_name: gnd
+ ignore: true
+ in_terms: []
+ io_terms: [gnd!]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props: {}
+ idc:
+ cell_name: idc
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ acm: [3, '']
+ acp: [3, '']
+ idc: [3, '']
+ pacm: [3, '']
+ pacp: [3, '']
+ srcType: [3, dc]
+ xfm: [3, '']
+ ideal_balun:
+ cell_name: ideal_balun
+ in_terms: []
+ io_terms: [d, c, p, n]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props: {}
+ ind:
+ cell_name: ind
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ m: [3, '']
+ r: [3, '']
+ iprobe:
+ cell_name: iprobe
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props: {}
+ ipulse:
+ cell_name: ipulse
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ i1: [3, '']
+ i2: [3, '']
+ idc: [3, '']
+ per: [3, '']
+ pw: [3, '']
+ srcType: [3, pulse]
+ td: [3, '']
+ ipwlf:
+ cell_name: ipwlf
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ fileName: [3, '']
+ srcType: [3, pwl]
+ isin:
+ cell_name: isin
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ freq: [3, '']
+ ia: [3, '']
+ idc: [3, '']
+ srcType: [3, sine]
+ mind:
+ cell_name: mind
+ in_terms: []
+ io_terms: []
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ ind1: [3, '']
+ ind2: [3, '']
+ k: [3, '0']
+ n12port:
+ cell_name: n12port
+ in_terms: []
+ io_terms: [t1, b1, t2, b2, t3, b3, t4, b4, t5, b5, t6, b6, t7, b7, t8, b8, t9,
+ b9, t10, b10, t11, b11, t12, b12]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ n1port:
+ cell_name: n1port
+ in_terms: []
+ io_terms: [t1, b1]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ n2port:
+ cell_name: n2port
+ in_terms: []
+ io_terms: [t1, b1, t2, b2]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ n3port:
+ cell_name: n3port
+ in_terms: []
+ io_terms: [t1, b1, t2, b2, t3, b3]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ n4port:
+ cell_name: n4port
+ in_terms: []
+ io_terms: [t1, b1, t2, b2, t3, b3, t4, b4]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ n6port:
+ cell_name: n6port
+ in_terms: []
+ io_terms: [t1, b1, t2, b2, t3, b3, t4, b4, t5, b5, t6, b6]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ n8port:
+ cell_name: n8port
+ in_terms: []
+ io_terms: [t1, b1, t2, b2, t3, b3, t4, b4, t5, b5, t6, b6, t7, b7, t8, b8]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ dataFile: [3, '']
+ interp: [3, linear]
+ thermalnoise: [3, yes]
+ port:
+ cell_name: port
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ num: [3, '']
+ r: [3, '']
+ srcType: [3, sine]
+ res:
+ cell_name: res
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ l: [3, '']
+ m: [3, '']
+ r: [3, '']
+ w: [3, '']
+ switch:
+ cell_name: switch
+ in_terms: []
+ io_terms: [N+, N-, NC+, NC-]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ rc: [3, '']
+ ro: [3, '']
+ vt1: [3, '']
+ vt2: [3, '']
+ vccs:
+ cell_name: vccs
+ in_terms: []
+ io_terms: [PLUS, MINUS, NC+, NC-]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ ggain: [3, '1.0']
+ maxm: [3, '']
+ minm: [3, '']
+ vcvs:
+ cell_name: vcvs
+ in_terms: []
+ io_terms: [PLUS, MINUS, NC+, NC-]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ egain: [3, '1.0']
+ maxm: [3, '']
+ minm: [3, '']
+ vdc:
+ cell_name: vdc
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ acm: [3, '']
+ acp: [3, '']
+ pacm: [3, '']
+ pacp: [3, '']
+ srcType: [3, dc]
+ vdc: [3, '']
+ xfm: [3, '']
+ vpulse:
+ cell_name: vpulse
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ per: [3, '']
+ pw: [3, '']
+ srcType: [3, pulse]
+ td: [3, '']
+ v1: [3, '']
+ v2: [3, '']
+ vdc: [3, '']
+ vpwlf:
+ cell_name: vpwlf
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ fileName: [3, '']
+ srcType: [3, pwl]
+ vsin:
+ cell_name: vsin
+ in_terms: []
+ io_terms: [PLUS, MINUS]
+ is_prim: true
+ lib_name: analogLib
+ nets: []
+ out_terms: []
+ props:
+ freq: [3, '']
+ srcType: [3, sine]
+ va: [3, '']
+ vdc: [3, '']
+ basic:
+ cds_thru:
+ cell_name: cds_thru
+ ignore: false
+ in_terms: []
+ io_terms: [src, dst]
+ is_prim: true
+ lib_name: basic
+ nets: []
+ out_terms: []
+ props: {}
+ noConn:
+ cell_name: noConn
+ ignore: true
+ in_terms: []
+ io_terms: [noConn]
+ is_prim: true
+ lib_name: basic
+ nets: []
+ out_terms: []
+ props: {}
+prim_files: {4: skywater130/netlist_setup/bag_prim.cdl, 5: '', 6: '', 7: skywater130/netlist_setup/bag_prim.scs}
diff --git a/netlist_setup/spectre_prim.scs b/netlist_setup/spectre_prim.scs
new file mode 100644
index 0000000..f8bde6b
--- /dev/null
+++ b/netlist_setup/spectre_prim.scs
@@ -0,0 +1,6 @@
+simulator lang=spectre
+
+subckt ideal_balun d c p n
+ K0 d 0 p c transformer n1=2
+ K1 d 0 c n transformer n1=2
+ends ideal_balun
diff --git a/pcell_setup/gen_skill.py b/pcell_setup/gen_skill.py
new file mode 100644
index 0000000..27da1fa
--- /dev/null
+++ b/pcell_setup/gen_skill.py
@@ -0,0 +1,96 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from jinja2 import Template
+
+tech_lib = 's8phirs_10r'
+# mos_w_default = '420n'
+# mos_l_default = '150n'
+# res_w_default = '1u'
+# res_l_default = '2u'
+res_metal_w_default = '720n'
+res_metal_l_default = '290n'
+dio_w_default = '1u'
+dio_l_default = '1u'
+
+mos_list = [
+ ('nmos4', 'standard', 'nfet', 'nshort', '420n', '150n'),
+ ('nmos4', 'svt', 'nfet', 'nshort', '420n', '150n'),
+ ('nmos4', 'hv', 'nfet', 'nhv', '750n', '500n'),
+ ('nmos4', 'hvesd', 'nfet', 'nhvesd', '17500n', '550n'),
+ ('nmos4', 'lvt', 'nfet', 'nlowvt', '420n', '150n'),
+ ('pmos4', 'standard', 'pfet', 'pshort', '550n', '150n'),
+ ('pmos4', 'svt', 'pfet', 'pshort', '550n', '150n'),
+ ('pmos4', 'hvt', 'pfet', 'phighvt', '540n', '150n'),
+ ('pmos4', 'hv', 'pfet', 'phv', '420n', '500n'),
+ ('pmos4', 'hvesd', 'pfet', 'phvesd', '14500n', '550n'),
+ ('pmos4', 'lvt', 'pfet', 'plowvt', '550n', '350n'),
+]
+
+res_list = [
+ ('standard', 'hrpoly', '1000n', '2105n'),
+ ('high_res', 'uhrpoly', '350n', '17400n'),
+]
+
+res_metal_list = [
+ '1',
+ '2',
+ '3',
+ '4',
+ '5',
+]
+
+dio_list = [
+]
+
+
+def run_main() -> None:
+ in_fname = 'prim_pcell_jinja2.il'
+ out_fname = 'prim_pcell.il'
+
+ with open(in_fname, 'r') as f:
+ content = f.read()
+
+ result = Template(content).render(
+ tech_lib=tech_lib,
+ mos_list=mos_list,
+ # mos_w_default=mos_w_default,
+ # mos_l_default=mos_l_default,
+ res_list=res_list,
+ # res_w_default=res_w_default,
+ # res_l_default=res_l_default,
+ res_metal_list=res_metal_list,
+ res_metal_w_default=res_metal_w_default,
+ res_metal_l_default=res_metal_l_default,
+ dio_list=dio_list,
+ dio_w_default=dio_w_default,
+ dio_l_default=dio_l_default,
+ )
+
+ with open(out_fname, 'w') as f:
+ f.write(result)
+
+
+if __name__ == '__main__':
+ run_main()
diff --git a/pcell_setup/mim_pcell.il b/pcell_setup/mim_pcell.il
new file mode 100644
index 0000000..4b1d981
--- /dev/null
+++ b/pcell_setup/mim_pcell.il
@@ -0,0 +1,106 @@
+;; This skill file compiles schematic PCells for BAG primitives for MIM
+
+lib_obj = ddGetObj("BAG_prim")
+
+
+; mim_standard/xcmimc2
+pcDefinePCell(
+ list( lib_obj "mim_standard" "schematic" "schematic")
+ ((unit_width string "1u")
+ (unit_height string "1u")
+ (num_rows string "1")
+ (num_cols string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(unit_width) * 1e6
+ lval = cdfParseFloatString(unit_height) * 1e6
+ rval = atoi(num_rows)
+ cval = atoi(num_cols)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "cmimc" "symbol"
+ "C0" 0:0 "R0" 1
+ list(list("ctype" "string" "xcmimc2")
+ list("cw" "string" sprintf(nil "%0.2f" wval))
+ list("cl" "string" sprintf(nil "%0.2f" lval))
+ list("nrow" "string" num_rows)
+ list("ncol" "string" num_cols)
+ list("cm" "string" sprintf(nil "%d" rval * cval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "TOP")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "TOP" 0:0.5 "R0")
+ "TOP" dbCreateTerm(io_net "TOP" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "c0"))
+ io_net = dbCreateNet(pcCellView "BOT")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "BOT" 0:-0.75 "R0")
+ "BOT" dbCreateTerm(io_net "BOT" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "c1"))
+ )
+)
+
+; mim_45/xcmimc2
+pcDefinePCell(
+ list( lib_obj "mim_45" "schematic" "schematic")
+ ((unit_width string "1u")
+ (unit_height string "1u")
+ (num_rows string "1")
+ (num_cols string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(unit_width) * 1e6
+ lval = cdfParseFloatString(unit_height) * 1e6
+ rval = atoi(num_rows)
+ cval = atoi(num_cols)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "cmimc" "symbol"
+ "C0" 0:0 "R0" 1
+ list(list("ctype" "string" "xcmimc2")
+ list("cw" "string" sprintf(nil "%0.2f" wval))
+ list("cl" "string" sprintf(nil "%0.2f" lval))
+ list("nrow" "string" num_rows)
+ list("ncol" "string" num_cols)
+ list("cm" "string" sprintf(nil "%d" rval * cval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "TOP")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "TOP" 0:0.5 "R0")
+ "TOP" dbCreateTerm(io_net "TOP" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "c0"))
+ io_net = dbCreateNet(pcCellView "BOT")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "BOT" 0:-0.75 "R0")
+ "BOT" dbCreateTerm(io_net "BOT" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "c1"))
+ )
+)
+
+; mim_34/xcmimc1
+pcDefinePCell(
+ list( lib_obj "mim_34" "schematic" "schematic")
+ ((unit_width string "1u")
+ (unit_height string "1u")
+ (num_rows string "1")
+ (num_cols string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(unit_width) * 1e6
+ lval = cdfParseFloatString(unit_height) * 1e6
+ rval = atoi(num_rows)
+ cval = atoi(num_cols)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "cmimc" "symbol"
+ "C0" 0:0 "R0" 1
+ list(list("ctype" "string" "xcmimc1")
+ list("cw" "string" sprintf(nil "%0.2f" wval))
+ list("cl" "string" sprintf(nil "%0.2f" lval))
+ list("nrow" "string" num_rows)
+ list("ncol" "string" num_cols)
+ list("cm" "string" sprintf(nil "%d" rval * cval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "TOP")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "TOP" 0:0.5 "R0")
+ "TOP" dbCreateTerm(io_net "TOP" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "c0"))
+ io_net = dbCreateNet(pcCellView "BOT")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "BOT" 0:-0.75 "R0")
+ "BOT" dbCreateTerm(io_net "BOT" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "c1"))
+ )
+)
diff --git a/pcell_setup/prim_pcell.il b/pcell_setup/prim_pcell.il
new file mode 100644
index 0000000..e265086
--- /dev/null
+++ b/pcell_setup/prim_pcell.il
@@ -0,0 +1,705 @@
+;; This skill file compiles schematic PCells for BAG primitives
+
+lib_obj = ddGetObj("BAG_prim")
+
+
+; nmos4_standard/nshort
+pcDefinePCell(
+ list( lib_obj "nmos4_standard" "schematic" "schematic")
+ ((w string "420n")
+ (l string "150n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "nfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "nshort")
+ list("hspiceModelMenu" "string" "nshort")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("nshort_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("nshort_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; nmos4_svt/nshort
+pcDefinePCell(
+ list( lib_obj "nmos4_svt" "schematic" "schematic")
+ ((w string "420n")
+ (l string "150n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "nfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "nshort")
+ list("hspiceModelMenu" "string" "nshort")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("nshort_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("nshort_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; nmos4_hv/nhv
+pcDefinePCell(
+ list( lib_obj "nmos4_hv" "schematic" "schematic")
+ ((w string "750n")
+ (l string "500n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "nfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "nhv")
+ list("hspiceModelMenu" "string" "nhv")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("nhv_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("nhv_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; nmos4_hvesd/nhvesd
+pcDefinePCell(
+ list( lib_obj "nmos4_hvesd" "schematic" "schematic")
+ ((w string "17500n")
+ (l string "550n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "nfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "nhvesd")
+ list("hspiceModelMenu" "string" "nhvesd")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("nhvesd_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("nhvesd_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; nmos4_lvt/nlowvt
+pcDefinePCell(
+ list( lib_obj "nmos4_lvt" "schematic" "schematic")
+ ((w string "420n")
+ (l string "150n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "nfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "nlowvt")
+ list("hspiceModelMenu" "string" "nlowvt")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("nlowvt_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("nlowvt_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; pmos4_standard/pshort
+pcDefinePCell(
+ list( lib_obj "pmos4_standard" "schematic" "schematic")
+ ((w string "550n")
+ (l string "150n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "pfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "pshort")
+ list("hspiceModelMenu" "string" "pshort")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("pshort_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("pshort_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; pmos4_svt/pshort
+pcDefinePCell(
+ list( lib_obj "pmos4_svt" "schematic" "schematic")
+ ((w string "550n")
+ (l string "150n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "pfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "pshort")
+ list("hspiceModelMenu" "string" "pshort")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("pshort_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("pshort_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; pmos4_hvt/phighvt
+pcDefinePCell(
+ list( lib_obj "pmos4_hvt" "schematic" "schematic")
+ ((w string "540n")
+ (l string "150n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "pfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "phighvt")
+ list("hspiceModelMenu" "string" "phighvt")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("phighvt_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("phighvt_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; pmos4_hv/phv
+pcDefinePCell(
+ list( lib_obj "pmos4_hv" "schematic" "schematic")
+ ((w string "420n")
+ (l string "500n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "pfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "phv")
+ list("hspiceModelMenu" "string" "phv")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("phv_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("phv_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; pmos4_hvesd/phvesd
+pcDefinePCell(
+ list( lib_obj "pmos4_hvesd" "schematic" "schematic")
+ ((w string "14500n")
+ (l string "550n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "pfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "phvesd")
+ list("hspiceModelMenu" "string" "phvesd")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("phvesd_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("phvesd_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+; pmos4_lvt/plowvt
+pcDefinePCell(
+ list( lib_obj "pmos4_lvt" "schematic" "schematic")
+ ((w string "550n")
+ (l string "350n")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "pfet" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "plowvt")
+ list("hspiceModelMenu" "string" "plowvt")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("plowvt_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("plowvt_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+
+
+
+; res_standard/hrpoly
+pcDefinePCell(
+ list( lib_obj "res_standard" "schematic" "schematic")
+ ((w string "1000n")
+ (l string "2105n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "hrpoly" "symbol"
+ "R0" 0.5:0 "R270" 1
+ list(list("segW" "string" wstr)
+ list("w" "string" wstr)
+ list("segL" "string" lstr)
+ list("l" "string" lstr)
+ list("rCalcMethod" "string" "Segment Length")
+ )
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" 1:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "PLUS"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" -0.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "MINUS"))
+ io_net = dbCreateNet(pcCellView "BULK")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "BULK" -0.15:-0.4 "R0")
+ "BULK" dbCreateTerm(io_net "BULK" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "B"))
+ )
+)
+
+; res_high_res/uhrpoly
+pcDefinePCell(
+ list( lib_obj "res_high_res" "schematic" "schematic")
+ ((w string "350n")
+ (l string "17400n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "uhrpoly" "symbol"
+ "R0" 0.5:0 "R270" 1
+ list(list("segW" "string" wstr)
+ list("w" "string" wstr)
+ list("segL" "string" lstr)
+ list("l" "string" lstr)
+ list("rCalcMethod" "string" "Segment Length")
+ )
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" 1:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "PLUS"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" -0.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "MINUS"))
+ io_net = dbCreateNet(pcCellView "BULK")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "BULK" -0.15:-0.4 "R0")
+ "BULK" dbCreateTerm(io_net "BULK" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "B"))
+ )
+)
+
+
+
+; res_metal_1/mrm1
+pcDefinePCell(
+ list( lib_obj "res_metal_1" "schematic" "schematic")
+ ((w string "720n")
+ (l string "290n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "res" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("resistorTypr" "string" "met1")
+ list("rw" "string" wstr)
+ list("rl" "string" lstr)
+ list("model" "string" "mrm1")
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r0"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r1"))
+ )
+)
+
+; res_metal_2/mrm2
+pcDefinePCell(
+ list( lib_obj "res_metal_2" "schematic" "schematic")
+ ((w string "720n")
+ (l string "290n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "res" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("resistorTypr" "string" "met2")
+ list("rw" "string" wstr)
+ list("rl" "string" lstr)
+ list("model" "string" "mrm2")
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r0"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r1"))
+ )
+)
+
+; res_metal_3/mrm3
+pcDefinePCell(
+ list( lib_obj "res_metal_3" "schematic" "schematic")
+ ((w string "720n")
+ (l string "290n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "res" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("resistorTypr" "string" "met3")
+ list("rw" "string" wstr)
+ list("rl" "string" lstr)
+ list("model" "string" "mrm3")
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r0"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r1"))
+ )
+)
+
+; res_metal_4/mrm4
+pcDefinePCell(
+ list( lib_obj "res_metal_4" "schematic" "schematic")
+ ((w string "720n")
+ (l string "290n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "res" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("resistorTypr" "string" "met4")
+ list("rw" "string" wstr)
+ list("rl" "string" lstr)
+ list("model" "string" "mrm4")
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r0"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r1"))
+ )
+)
+
+; res_metal_5/mrm5
+pcDefinePCell(
+ list( lib_obj "res_metal_5" "schematic" "schematic")
+ ((w string "720n")
+ (l string "290n")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "s8phirs_10r" "res" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("resistorTypr" "string" "met5")
+ list("rw" "string" wstr)
+ list("rl" "string" lstr)
+ list("model" "string" "mrm5")
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r0"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r1"))
+ )
+)
+
+
+
diff --git a/pcell_setup/prim_pcell_jinja2.il b/pcell_setup/prim_pcell_jinja2.il
new file mode 100644
index 0000000..9ac3a4b
--- /dev/null
+++ b/pcell_setup/prim_pcell_jinja2.il
@@ -0,0 +1,158 @@
+;; This skill file compiles schematic PCells for BAG primitives
+
+lib_obj = ddGetObj("BAG_prim")
+
+{% for mtype, threshold, model, model_thres, w_def, l_def in mos_list %}
+; {{ mtype }}_{{ threshold }}/{{ model_thres }}
+pcDefinePCell(
+ list( lib_obj "{{ mtype }}_{{ threshold }}" "schematic" "schematic")
+ ((w string "{{ w_def }}")
+ (l string "{{ l_def }}")
+ (nf string "1")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ nval = atoi(nf)
+ inst = dbCreateParamInstByMasterName( pcCellView "{{ tech_lib }}" "{{ model }}" "symbol"
+ "N0" -0.375:0 "R0" 1
+ list(list("hspiceModel" "string" "{{ model_thres }}")
+ list("hspiceModelMenu" "string" "{{ model_thres }}")
+ list("w" "string" sprintf(nil "%0.2f" wval))
+ list("{{ model_thres }}_l0_w" "string" sprintf(nil "%0.2f" wval))
+ list("l" "string" sprintf(nil "%0.2f" lval))
+ list("{{ model_thres }}_l" "string" sprintf(nil "%0.2f" lval))
+ list("m" "string" nf)
+ list("totalW" "string" sprintf(nil "%0.2f" wval * nval)))
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "D")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "D" -0.5:0.5625 "R0")
+ "D" dbCreateTerm(io_net "D" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "d"))
+ io_net = dbCreateNet(pcCellView "G")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "G" -0.875:0 "R0")
+ "G" dbCreateTerm(io_net "G" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "g"))
+ io_net = dbCreateNet(pcCellView "S")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "S" -0.5:-0.5 "R0")
+ "S" dbCreateTerm(io_net "S" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "s"))
+ io_net = dbCreateNet(pcCellView "B")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "B" 0.125:0 "R0")
+ "B" dbCreateTerm(io_net "B" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "b"))
+ )
+)
+{% endfor %}
+
+{% for intent, model, w_def, l_def in res_list %}
+; res_{{ intent }}/{{ model }}
+pcDefinePCell(
+ list( lib_obj "res_{{ intent }}" "schematic" "schematic")
+ ((w string "{{ w_def }}")
+ (l string "{{ l_def }}")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "{{ tech_lib }}" "{{ model }}" "symbol"
+ "R0" 0.5:0 "R270" 1
+ list(list("segW" "string" wstr)
+ list("w" "string" wstr)
+ list("segL" "string" lstr)
+ list("l" "string" lstr)
+ list("rCalcMethod" "string" "Segment Length")
+ )
+ )
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" 1:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "PLUS"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" -0.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "MINUS"))
+ io_net = dbCreateNet(pcCellView "BULK")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "BULK" -0.15:-0.4 "R0")
+ "BULK" dbCreateTerm(io_net "BULK" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "B"))
+ )
+)
+{% endfor %}
+
+{% for layer in res_metal_list %}
+; res_metal_{{ layer }}/mrm{{ layer }}
+pcDefinePCell(
+ list( lib_obj "res_metal_{{ layer }}" "schematic" "schematic")
+ ((w string "{{ res_metal_w_default }}")
+ (l string "{{ res_metal_l_default }}")
+ )
+ let((inst iopin_master io_net io_pin)
+ wval = cdfParseFloatString(w) * 1e6
+ lval = cdfParseFloatString(l) * 1e6
+ wstr = sprintf(nil "%0.3f" wval)
+ lstr = sprintf(nil "%0.3f" lval)
+ inst = dbCreateParamInstByMasterName( pcCellView "{{ tech_lib }}" "res" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("resistorTypr" "string" "met{{ layer }}")
+ list("rw" "string" wstr)
+ list("rl" "string" lstr)
+ list("model" "string" "mrm{{ layer }}")
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r0"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "r1"))
+ )
+)
+{% endfor %}
+
+
+{% for dtype, intent, model in dio_list %}
+; {{ dtype }}_{{ intent }}/{{ model }}
+pcDefinePCell(
+ list( lib_obj "{{ dtype }}_{{ intent }}" "schematic" "schematic")
+ ((w string "{{ dio_w_default }}")
+ (l string "{{ dio_l_default }}")
+ )
+ let((inst iopin_master io_net io_pin wval lval dio_w dio_l)
+ wval = atoi(w)
+ lval = atoi(l)
+ dio_w = (wval - 1)*48 + 14
+ dio_l = (lval + 1)*86 - 18
+
+ inst = dbCreateParamInstByMasterName( pcCellView "{{ tech_lib }}" "{{ model }}" "symbol"
+ "R0" 0.1:0 "R90" 1
+ list(list("nfin" "string" w)
+ list("fw" "string" sprintf(nil "%dn" dio_w))
+ list("nf" "string" l)
+ list("dl" "string" sprintf(nil "%dn" dio_l))
+ list("m" "string" "1")
+ list("area" "float" dio_w*dio_l*1e-18)
+ list("pj" "float" 2*1e-9*(dio_w + dio_l))
+ )
+ )
+
+ iopin_master = dbOpenCellViewByType("basic" "iopin" "symbolr" nil "r")
+ io_net = dbCreateNet(pcCellView "PLUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "PLUS" -0.15:0 "R0")
+ "PLUS" dbCreateTerm(io_net "PLUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "PLUS"))
+ io_net = dbCreateNet(pcCellView "MINUS")
+ io_pin = dbCreatePin(io_net dbCreateInst(pcCellView iopin_master "MINUS" 1.15:0 "R0")
+ "MINUS" dbCreateTerm(io_net "MINUS" "inputOutput"))
+ dbCreateInstTerm(io_net inst dbFindTermByName(inst~>master "MINUS"))
+ )
+)
+{% endfor %}
diff --git a/src/BAG_prim/__init__.py b/src/BAG_prim/__init__.py
new file mode 100644
index 0000000..50fa21e
--- /dev/null
+++ b/src/BAG_prim/__init__.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
diff --git a/src/BAG_prim/schematic/__init__.py b/src/BAG_prim/schematic/__init__.py
new file mode 100644
index 0000000..50fa21e
--- /dev/null
+++ b/src/BAG_prim/schematic/__init__.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
diff --git a/src/BAG_prim/schematic/mim_34.py b/src/BAG_prim/schematic/mim_34.py
new file mode 100644
index 0000000..9186e8c
--- /dev/null
+++ b/src/BAG_prim/schematic/mim_34.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+# -*- coding: utf-8 -*-
+
+from typing import Any
+
+
+from bag.design.module import MIMModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__mim_34(MIMModuleBase):
+ """design module for BAG_prim__mim_34.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MIMModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/mim_45.py b/src/BAG_prim/schematic/mim_45.py
new file mode 100644
index 0000000..cfc2357
--- /dev/null
+++ b/src/BAG_prim/schematic/mim_45.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+# -*- coding: utf-8 -*-
+
+from typing import Any
+
+
+from bag.design.module import MIMModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__mim_45(MIMModuleBase):
+ """design module for BAG_prim__mim_45.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MIMModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/mim_standard.py b/src/BAG_prim/schematic/mim_standard.py
new file mode 100644
index 0000000..2fe6923
--- /dev/null
+++ b/src/BAG_prim/schematic/mim_standard.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+# -*- coding: utf-8 -*-
+
+from typing import Any
+
+
+from bag.design.module import MIMModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__mim_standard(MIMModuleBase):
+ """design module for BAG_prim__mim_standard.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MIMModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/nmos4_hv.py b/src/BAG_prim/schematic/nmos4_hv.py
new file mode 100644
index 0000000..ca8725c
--- /dev/null
+++ b/src/BAG_prim/schematic/nmos4_hv.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__nmos4_hv(MosModuleBase):
+ """design module for BAG_prim__nmos4_hv.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/nmos4_hvesd.py b/src/BAG_prim/schematic/nmos4_hvesd.py
new file mode 100644
index 0000000..b706045
--- /dev/null
+++ b/src/BAG_prim/schematic/nmos4_hvesd.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__nmos4_hvesd(MosModuleBase):
+ """design module for BAG_prim__nmos4_hvesd.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/nmos4_lvt.py b/src/BAG_prim/schematic/nmos4_lvt.py
new file mode 100644
index 0000000..33e42c3
--- /dev/null
+++ b/src/BAG_prim/schematic/nmos4_lvt.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__nmos4_lvt(MosModuleBase):
+ """design module for BAG_prim__nmos4_lvt.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/nmos4_standard.py b/src/BAG_prim/schematic/nmos4_standard.py
new file mode 100644
index 0000000..fea126d
--- /dev/null
+++ b/src/BAG_prim/schematic/nmos4_standard.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__nmos4_standard(MosModuleBase):
+ """design module for BAG_prim__nmos4_standard.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/nmos4_svt.py b/src/BAG_prim/schematic/nmos4_svt.py
new file mode 100644
index 0000000..7406495
--- /dev/null
+++ b/src/BAG_prim/schematic/nmos4_svt.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__nmos4_svt(MosModuleBase):
+ """design module for BAG_prim__nmos4_svt.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/pmos4_hv.py b/src/BAG_prim/schematic/pmos4_hv.py
new file mode 100644
index 0000000..cbb1d6f
--- /dev/null
+++ b/src/BAG_prim/schematic/pmos4_hv.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__pmos4_hv(MosModuleBase):
+ """design module for BAG_prim__pmos4_hv.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/pmos4_hvesd.py b/src/BAG_prim/schematic/pmos4_hvesd.py
new file mode 100644
index 0000000..fa771c0
--- /dev/null
+++ b/src/BAG_prim/schematic/pmos4_hvesd.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__pmos4_hvesd(MosModuleBase):
+ """design module for BAG_prim__pmos4_hvesd.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/pmos4_hvt.py b/src/BAG_prim/schematic/pmos4_hvt.py
new file mode 100644
index 0000000..229c2af
--- /dev/null
+++ b/src/BAG_prim/schematic/pmos4_hvt.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__pmos4_hvt(MosModuleBase):
+ """design module for BAG_prim__pmos4_hvt.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/pmos4_lvt.py b/src/BAG_prim/schematic/pmos4_lvt.py
new file mode 100644
index 0000000..a0b7b3a
--- /dev/null
+++ b/src/BAG_prim/schematic/pmos4_lvt.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__pmos4_lvt(MosModuleBase):
+ """design module for BAG_prim__pmos4_lvt.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/pmos4_standard.py b/src/BAG_prim/schematic/pmos4_standard.py
new file mode 100644
index 0000000..5c610f3
--- /dev/null
+++ b/src/BAG_prim/schematic/pmos4_standard.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__pmos4_standard(MosModuleBase):
+ """design module for BAG_prim__pmos4_standard.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/pmos4_svt.py b/src/BAG_prim/schematic/pmos4_svt.py
new file mode 100644
index 0000000..b8df7f7
--- /dev/null
+++ b/src/BAG_prim/schematic/pmos4_svt.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Any
+
+
+from bag.design.module import MosModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__pmos4_svt(MosModuleBase):
+ """design module for BAG_prim__pmos4_svt.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ MosModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/res_high_res.py b/src/BAG_prim/schematic/res_high_res.py
new file mode 100644
index 0000000..e962170
--- /dev/null
+++ b/src/BAG_prim/schematic/res_high_res.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+# -*- coding: utf-8 -*-
+
+from typing import Any
+
+
+from bag.design.module import ResPhysicalModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__res_high_res(ResPhysicalModuleBase):
+ """design module for BAG_prim__res_high_res.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ ResPhysicalModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/res_metal_1.py b/src/BAG_prim/schematic/res_metal_1.py
new file mode 100644
index 0000000..8e4078c
--- /dev/null
+++ b/src/BAG_prim/schematic/res_metal_1.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+# -*- coding: utf-8 -*-
+
+from typing import Any
+
+
+from bag.design.module import ResMetalModule
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__res_metal_1(ResMetalModule):
+ """design module for BAG_prim__res_metal_1.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ ResMetalModule.__init__(self, '', database, params, **kwargs)
diff --git a/src/BAG_prim/schematic/res_standard.py b/src/BAG_prim/schematic/res_standard.py
new file mode 100644
index 0000000..662fc4a
--- /dev/null
+++ b/src/BAG_prim/schematic/res_standard.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+# -*- coding: utf-8 -*-
+
+from typing import Any
+
+
+from bag.design.module import ResPhysicalModuleBase
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class BAG_prim__res_standard(ResPhysicalModuleBase):
+ """design module for BAG_prim__res_standard.
+ """
+
+ def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+ ResPhysicalModuleBase.__init__(self, '', database, params, **kwargs)
diff --git a/src/templates_skywater130/__init__.py b/src/templates_skywater130/__init__.py
new file mode 100644
index 0000000..0c445b7
--- /dev/null
+++ b/src/templates_skywater130/__init__.py
@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+import os
+import pkg_resources
+
+from bag.io import read_yaml
+
+config_fname = pkg_resources.resource_filename(__name__, os.path.join('data', 'tech_params.yaml'))
+
+config = read_yaml(config_fname)
diff --git a/src/templates_skywater130/data/tech_params.yaml b/src/templates_skywater130/data/tech_params.yaml
new file mode 100755
index 0000000..c5c4cd2
--- /dev/null
+++ b/src/templates_skywater130/data/tech_params.yaml
@@ -0,0 +1,779 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+# PDK library name.
+tech_lib: 'skywater130'
+# layout unit, in meters.
+layout_unit: 1.0e-6
+# layout resolution, in layout units.
+resolution: 0.005
+# GDS export layout resolution
+gds_resolution: 0.001
+# True if BAG needs to handle coloring metals.
+use_track_coloring: True
+# default purpose name
+default_purpose: drawing
+# pin purpose name
+pin_purpose: pin
+# True to create pin objects
+make_pin_obj: True
+
+imp_layers:
+ nch: !!python/tuple ['nsdm', 'drawing']
+ pch: !!python/tuple ['psdm', 'drawing']
+ ptap: !!python/tuple ['psdm', 'drawing']
+ ntap: !!python/tuple ['nsdm', 'drawing']
+
+mos_lay_table:
+ # poly
+ PO: !!python/tuple ['poly', 'drawing']
+ # active
+ OD:
+ active: !!python/tuple ['diff', 'drawing']
+ sub: !!python/tuple ['tap', 'drawing']
+ # gate connection metal
+ MP: !!python/tuple ['li1', 'drawing']
+ # OC connection metal
+ MD: !!python/tuple ['li1', 'drawing']
+
+# mapping from metal layer ID to layer/purpose pair that defines a metal resistor.
+res_metal_layer_table: {}
+# 1: [!!python/tuple ['met1', 'res']]
+# 2: [!!python/tuple ['met2', 'res']]
+# 3: [!!python/tuple ['met3', 'res']]
+# 4: [!!python/tuple ['met4', 'res']]
+# 5: [!!python/tuple ['met5', 'res']]
+
+# mapping from metal layer ID to layer/purpose pair that defines metal exclusion region.
+metal_exclude_table: {}
+# 1: !!python/tuple ['met1', 'drawing']
+# 2: !!python/tuple ['met2', 'drawing']
+# 3: !!python/tuple ['met3', 'drawing']
+# 4: !!python/tuple ['met4', 'drawing']
+# 5: !!python/tuple ['met5', 'drawing']
+
+exclude_is_blockage: true
+
+# mapping from metal layer ID to metal layer name. Assume purpose is 'drawing'.
+lay_purp_list: &lp_list
+ 0: [!!python/tuple ['li1', 'drawing']]
+ 1: [!!python/tuple ['met1', 'drawing']]
+ 2: [!!python/tuple ['met2', 'drawing']]
+ 3: [!!python/tuple ['met3', 'drawing']]
+ 4: [!!python/tuple ['met4', 'drawing']]
+ 5: [!!python/tuple ['met5', 'drawing']]
+# 6: [!!python/tuple ['capm', 'drawing']]
+
+dum_lay_purp_list: *lp_list
+
+width_intervals:
+ 0:
+ - [[28, 801]] # horizontal
+ - [[28, .inf]] # vertical
+ 1:
+ - [[28, .inf]] # horizontal
+ - [[28, 801]] # vertical
+ 2:
+ - [[28, 801]]
+ - [[28, .inf]]
+ 3:
+ - [[60, .inf]]
+ - [[60, 801]]
+ 4:
+ - [[60, 2001]]
+ - [[60, .inf]]
+ 5:
+ - [[320, .inf]]
+ - [[320, .inf]]
+
+# mapping from tuple of via layers to via ID.
+via_id:
+ [!!python/tuple ['tap', 'drawing'], !!python/tuple ['li1', 'drawing']]: TPL1_C
+ [!!python/tuple ['poly', 'drawing'], !!python/tuple ['li1', 'drawing']]: PYL1_C
+ [!!python/tuple ['li1', 'drawing'], !!python/tuple ['met1', 'drawing']]: L1M1_C
+ [!!python/tuple ['met1', 'drawing'], !!python/tuple ['met2', 'drawing']]: M1M2_C
+ [!!python/tuple ['met2', 'drawing'], !!python/tuple ['met3', 'drawing']]: M2M3_C
+ [!!python/tuple ['met3', 'drawing'], !!python/tuple ['met4', 'drawing']]: M3M4_C
+ [!!python/tuple ['met4', 'drawing'], !!python/tuple ['met5', 'drawing']]: M4M5_C
+
+# table of electromigration temperature scale factor
+idc_em_scale:
+ # scale factor for resistor
+ # scale[idx] is used if temperature is less than or equal to temp[idx]
+ res:
+ temp: [100, .inf]
+ scale: [1.0, 0.5]
+ # scale factor for this metal layer type
+ ['met1', 'drawing']: &x_em_scale
+ temp: [100, .inf]
+ scale: [1.0, 0.5]
+ ['met2', 'drawing']: *x_em_scale
+ ['met3', 'drawing']: *x_em_scale
+ ['met4', 'drawing']: *x_em_scale
+ ['met5', 'drawing']: *x_em_scale
+ # default scale vector
+ default:
+ temp: [100, .inf]
+ scale: [1.0, 0.5]
+
+# via enclosure/spacing rules
+flipped_vias: [TPL1_C, PYL1_C, L1M1_C, M1M2_C, M2M3_C, M3M4_C, M4M5_C]
+via_square_list: [square]
+via:
+ L1M1_C:
+ - name: square
+ dim: [34, 34]
+ sp: [38, 38]
+ bot_enc:
+ - [.inf, [[0, 0]]]
+ top_enc:
+ - [.inf, [[12, 12]]]
+ M1M2_C:
+ - name: square
+ dim: [30, 30]
+ sp: [34, 34]
+ bot_enc: &square_1x_enc
+ - [.inf, [[17, 11], [11, 17]]]
+ top_enc: *square_1x_enc
+ M2M3_C:
+ - name: square
+ dim: [40, 40]
+ sp: [40, 40]
+ bot_enc:
+ - [.inf, [[17, 8], [8, 17]]]
+ top_enc:
+ - [.inf, [[17, 13], [13, 17]]]
+ M3M4_C:
+ - name: square
+ dim: [40, 40]
+ sp: [40, 40]
+ bot_enc:
+ - [.inf, [[18, 11], [11, 18]]] #x, y enclosure
+ top_enc:
+ - [.inf, [[13, 13]]]
+ M4M5_C:
+ - name: square
+ dim: [160, 160]
+ sp: [160, 160]
+ bot_enc:
+ - [.inf, [[38, 38]]]
+ top_enc:
+ - [.inf, [[62, 62]]]
+
+# minimum wire spacing rule. Space is measured orthogonal to wire direction.
+# should be in resolution units
+sp_min:
+ [li1, drawing]:
+ - [.inf, 34]
+ [met1, drawing]: &sp_min_1x
+ - [.inf, 28]
+ [met2, drawing]: *sp_min_1x
+ [met3, drawing]: &sp_min_2x
+ - [.inf, 60]
+ [met4, drawing]: *sp_min_2x
+ [met5, drawing]:
+ - [.inf, 320]
+
+# minimum line-end spacing rule. Space is measured parallel to wire direction.
+sp_le_min:
+ [li1, drawing]:
+ - [.inf, 34]
+ [met1, drawing]: &sp_le_min_1x
+ - [.inf, 28]
+ [met2, drawing]: *sp_le_min_1x
+ [met3, drawing]: &sp_le_min_2x
+ - [.inf, 60]
+ [met4, drawing]: *sp_le_min_2x
+ [met5, drawing]:
+ - [.inf, 320]
+
+
+# minimum length/minimum area rules.
+len_min:
+ [li1, drawing]:
+ w_al_list:
+ - [.inf, 2244, 0]
+ md_al_list: []
+ [met1, drawing]:
+ w_al_list:
+ - [.inf, 3320, 0]
+ md_al_list: []
+ [met2, drawing]:
+ w_al_list:
+ - [.inf, 2704, 0]
+ md_al_list: []
+ [met3, drawing]:
+ w_al_list:
+ - [.inf, 9600, 0]
+ md_al_list: []
+ [met4, drawing]:
+ w_al_list:
+ - [.inf, 9600, 0]
+ md_al_list: []
+ [met5, drawing]:
+ w_al_list:
+ - [.inf, 160000, 0]
+ md_al_list: []
+
+margins:
+ well: [40, 40]
+
+# transistor DRC rules.
+mos:
+ # MOSBase vertical connection layer
+ conn_layer: 0
+ # min/max transistor width.
+ mos_w_range: [84, 1400]
+ # transistor width resolution
+ mos_w_resolution: 1
+ # source/drain pitch related constants.
+ # source/drain pitch is computed as val[0] + val[1] * lch_unit
+ sd_pitch_constants:
+ lch: [30, .inf]
+ val: [[86, 0]]
+ # drain connection info
+ d_wire_info:
+ bot_layer: 0
+ # wire_w, is_horiz, v_w, v_h, v_sp, v_bot_enc, v_top_enc
+ info_list:
+ - [34, False, 34, 34, 34, 8, 16]
+ # gate connection info
+ g_wire_info:
+ bot_layer: 0
+ # wire_w, is_horiz, v_w, v_h, v_sp, v_bot_enc, v_top_enc
+ info_list:
+ - [34, False, 34, 34, 34, 10, 16]
+ # horizontal margin for abutting with another ResTech or MosTech
+ edge_margin: 86 # TODO: currently sekt to 1 pitch
+ # vertical margin for abutting with another ResTech or MosTech
+ end_margin: 86 # TODO: currently set to 1 pitch
+ # minimum horizontal space between OD, in resolution units
+ od_spx: 54
+ # minimum vertical space between OD, in resolution units
+ od_spy: 54
+ # guard ring vertical space
+ od_spy_gr: 4000
+ # maximum vertical space between OD, in resolution units
+ od_spy_max: 4000
+ # set by via enclosure, licon.5
+ # od_po_extx: 54 #96
+ od_po_extx: 76
+ # set by via enclosure for tap, licon.7
+ # This is in absolute resolution units of enclosure of licon, directly corresponds to licon.7 value
+ od_tap_extx: 24
+
+ # M1 pitch
+ blk_h_pitch: 86
+
+ # poly.2
+ po_spy: 42
+ # cannot find constrant, set to od_w_min
+ po_h_min: 84
+ # poly.10
+ po_od_exty: 26
+ # from RF transistor
+ po_h_gate: 70
+
+ # licon.9
+ mg_imp_spy: 22
+
+ npc_w: 74
+ # licon1 height + licon1 enclosure
+ npc_h: 74
+
+ md_area_min: 2244
+ md_spy: 34
+
+ # n/psdm.3, minimum spacing in x direction between same type OD implants in res units
+ imp_same_sp: 76
+ # n/psdm.7, minimum spacing in y direction between opposite OD implants in res units
+ imp_diff_sp: 26
+ # nsdm.7
+ imp_od_encx: 26
+ # nsdm.7
+ imp_od_ency: 26
+ # nsdm.1
+ imp_h_min: 86
+
+ # might be redundant, well margin from edge to implant
+ nwell_imp: 40
+
+ latchup: # rules relating to MOS latchup
+ # maximum distance from tap >=50u from signal diffusion in res units
+ max_distance_from_tap__far: 3000
+ # maximum distance from tap near signal diffusion in res units
+ max_distance_from_tap__near: 1200
+
+ grid_info: # [layer, width, track width]
+ - [0, 34, 52, 1]
+ - [2, 56, 30, 1]
+ - [4, 66, 106, 1]
+
+fill: {}
+
+res_metal: {}
+
+res_lay_table:
+ PO: !!python/tuple ['poly', 'drawing']
+ ID: !!python/tuple ['poly', 'res']
+ CUT: !!python/tuple ['poly', 'cut']
+ NPC: !!python/tuple ['npc', 'drawing']
+ IMP: !!python/tuple ['psdm', 'drawing']
+ OD_sub: !!python/tuple ['tap', 'drawing']
+
+# resistor DRC rules
+res:
+ # ArrayBase vertical connection layer
+ conn_layer: 0
+ # Default mos conn type (unused)
+ mos_type_default: 'pch'
+ # Default threshold (unused)
+ threshold_default: 'lvt'
+ # Has substrate port
+ has_substrate_port: True
+ # Default sub type
+ sub_type_default: 'ptap'
+ # minimum width of unit resistor
+ w_min: 66
+ # minimum length of unit resistor
+ l_min: 100
+ # w / h of minimum resistor unit
+ min_size: !!python/tuple [172, 1376]
+ # block x / y pitch
+ blk_pitch: !!python/tuple [86, 86]
+ # grid info of vertical metals
+ grid_info:
+ - [0, 34, 52]
+ - [2, 56, 30]
+ - [4, 66, 106]
+ # horizontal margin for abutting with another ResTech or MosTech
+ edge_margin: 86 # TODO: currently set to 1 pitch
+ # vertical margin for abutting with another ResTech or MosTech
+ end_margin: 86 # TODO: currently set to 1 pitch
+ # poly vertical extension beyond resID layer
+ po_id_exty: 416
+ # npc enclosure of poly in any direction
+ npc_po_enc: 19
+ # psdm enclosure of npc
+ imp_npc_enc: [3, 51]
+ # tap implant height
+ tap_imp_h: 134
+ # tap height
+ tap_h: 82
+ # resistor layer enclosure of npc in any direction
+ rlay_npc_enc: 21
+ # space between adjacent npc layers
+ npc_sp: 54
+ # resistor layer based on type
+ rlay:
+ standard: !!python/tuple ['rpm', 'drawing']
+ high_res: !!python/tuple ['urpm', 'drawing']
+ # specs for via from PO to conn_layer (li1)
+ po_via_specs:
+ name: PYL1_C
+ dim: [38, 400]
+ bot_enc: [11, 16]
+ top_enc: [16, 16]
+ spx: 102
+ # specs for via from tap to conn_layer (li1)
+ tap_via_specs:
+ name: TPL1_C
+ dim: [34, 34]
+ bot_enc: [24, 24]
+ top_enc: [16, 16]
+ spx: 45
+
+# mim cap DRC rules
+mim:
+ # capm.1 minimum width
+ min_width: 400
+ # capm.2b min bottom plate to bottom plate split
+ bot_bot_sp: 200
+ # capm.3 enclosure of top metal around capm
+ top_to_cap_sp: 28
+ # capm.4 space between via and capm edge
+ capvia_cap: 40
+ # capm.5 space between non-cap via & capm layer when connected by layer
+ cap_via2_sp: 254
+ # capm.6 width to length or length to width
+ max_ratio: 20
+ # capm.8 Minimum space between non-cap via and capm layer when no overlap
+ via_cap_sp: 28
+ # capm.11 Min space between capm to metal2
+ capm_met_sp: 100
+
+ cap_info: # top_layer: [(layer, purpose), width, spacing]
+ 4: [!!python/tuple ['capm', 'drawing'], 400, 168]
+ 5: [!!python/tuple ['cap2m', 'drawing'], 400, 168]
+ via_info: # bot layer: type, dimension, space, bot_enc, top_enc]
+ 3: ['M3M4_C', 40, 40, 18, 13]
+ 4: ['M4M5_C', 160, 160, 38, 62]
+
+layer:
+ nwell: 0
+ pwell: 1
+ diff: 2
+ tap: 3
+ poly: 4
+ mcon: 5
+ met1: 6
+ via: 7
+ met2: 8
+ via2: 9
+ met3: 10
+ pad: 11
+ via3: 12
+ met4: 13
+ via4: 14
+ met5: 15
+ prune: 21
+ li1: 22
+ dnwell: 23
+ inductor: 24
+ lvtn: 25
+ nsdm: 30
+ psdm: 31
+ hvntm: 36
+ cnsm: 37
+ r1v: 39
+ r1c: 40
+ tunm: 41
+ hvi: 42
+ licon1: 43
+ padCenter: 45
+ nsm: 47
+ cpwbm: 51
+ cfom: 52
+ ldntm: 53
+ cp1m: 55
+ cnsdm: 56
+ cpsdm: 57
+ cntm: 58
+ cctm1: 59
+ cmm1: 60
+ cviam: 61
+ cmm2: 62
+ cviam2: 63
+ cmm3: 64
+ cpdm: 66
+ cviam3: 67
+ cmm4: 68
+ cviam4: 69
+ cmm5: 70
+ capm: 75
+ pmm: 76
+ fom: 77
+ cdnm: 79
+ urpm: 81
+ crrpm: 82
+ cli1m: 83
+ curpm: 84
+ chvtpm: 85
+ cap2m: 86
+ crpm: 87
+ vhvi: 88
+ clvom: 89
+ cncm: 90
+ ctunm: 91
+ hvtp: 92
+ conom: 93
+ clicm1: 95
+ ncm: 96
+ cpmm: 97
+ overlap: 99
+ rrpm: 100
+ pnp: 101
+ chvntm: 102
+ capacitor: 103
+ rpm: 106
+ target: 107
+ cnwm: 109
+ areaid: 110
+ npn: 111
+ hvtr: 113
+ cpmm2: 114
+ npc: 115
+ cnpc: 116
+ pmm2: 117
+ chvtrm: 118
+ cpbo: 119
+ clvtnm: 120
+ pwelliso: 122
+ blanking: 123
+ cldntm: 126
+ rdl: 136
+ ubm: 140
+ bump: 141
+ ccu1m: 142
+ cubm: 143
+ cbump: 144
+ cpwdem: 169
+ pwde: 170
+ pwbm: 173
+ uhvi: 174
+ Unrouted: 200
+ Row: 201
+ Group: 202
+ Cannotoccupy: 203
+ Canplace: 204
+ hardFence: 205
+ softFence: 206
+ y0: 207
+ y1: 208
+ y2: 209
+ y3: 210
+ y4: 211
+ y5: 212
+ y6: 213
+ y7: 214
+ y8: 215
+ y9: 216
+ designFlow: 217
+ stretch: 218
+ edgeLayer: 219
+ changedLayer: 220
+ unset: 221
+ unknown: 222
+ spike: 223
+ hiz: 224
+ resist: 225
+ drive: 226
+ supply: 227
+ wire: 228
+ pin: 229
+ text: 230
+ device: 231
+ border: 232
+ snap: 233
+ align: 234
+ prBoundary: 235
+ instance: 236
+ annotate: 237
+ marker: 238
+ select: 239
+ substrate: 240
+ solderMaskBottom: 241
+ beginGenericLayer: 242
+ internalGenericLayer: 243
+ endGenericLayer: 244
+ solderMaskTop: 245
+ drill: 246
+ wirebond: 247
+ wirebondFingerGuide: 248
+ assemblyBoundary: 249
+ grid: 251
+ axis: 252
+ hilite: 253
+ background: 254
+purpose:
+ seal: 1
+ core: 2
+ frame: 3
+ waffleDrop: 4
+ standardc: 5
+ sigPadDiff: 6
+ sigPadWell: 7
+ sigPadMetNtr: 8
+ ferro: 9
+ moduleCut: 10
+ dieCut: 11
+ frameRect: 12
+ zener: 13
+ extDrain20: 14
+ cut: 15
+ res: 16
+ esd: 17
+ tmppnp: 18
+ short: 19
+ mask: 20
+ maskAdd: 21
+ maskDrop: 22
+ diode: 23
+ fuse: 24
+ gate: 25
+ hvnwell: 26
+ rdlprobepad: 27
+ hv: 28
+ probe: 29
+ extFab: 30
+ option1: 31
+ option2: 32
+ option3: 33
+ option4: 34
+ option5: 35
+ option6: 36
+ option7: 37
+ option8: 38
+ precres: 39
+ silicon: 40
+ vlc: 41
+ met3: 42
+ met2: 43
+ met1: 44
+ li1: 45
+ poly: 46
+ injection: 47
+ nodnw: 49
+ deadZon: 50
+ critCorner: 51
+ critSid: 52
+ substrateCut: 53
+ opcDrop: 54
+ cuPillar: 55
+ techCd: 56
+ term1: 57
+ term2: 58
+ term3: 59
+ scr: 60
+ port: 61
+ port1: 62
+ region: 63
+ ppath: 65
+ ppath1: 66
+ macro: 67
+ nwellIsolation: 68
+ waffleWindow: 69
+ block: 70
+ waffleAdd1: 71
+ waffleAdd2: 72
+ cuDrop: 74
+ extendedDrain: 75
+ subcktDevice: 76
+ pixel: 77
+ capacitor: 78
+ analog: 79
+ lvdnw: 80
+ photo: 81
+ guardring: 82
+ model: 83
+ ipExempt: 84
+ pitch: 85
+ HighVt: 86
+ lvNative: 87
+ psa1: 88
+ psa2: 89
+ psa3: 90
+ psa4: 91
+ psa5: 92
+ psa6: 93
+ hole: 94
+ select: 95
+ dummy: 96
+ umconly: 97
+ opc: 98
+ nodummy: 99
+ drc: 100
+ etest: 101
+ vss: 102
+ fc: 103
+ fix: 104
+ mim: 105
+ nmim: 106
+ pad: 107
+ per: 108
+ cvs: 109
+ ext: 110
+ ip: 111
+ low_vt: 112
+ cis_array: 113
+ imagers: 114
+ t3: 115
+ logic: 116
+ dio: 117
+ cap: 118
+ res1: 119
+ bjt: 120
+ efuseMark: 121
+ slotBlock: 122
+ fuseMark: 123
+ umcIP: 124
+ rfdiode: 125
+ lowTapDensity: 126
+ notCritSide: 127
+ fabBlock: 128
+ dynamic: 222
+ fatal: 223
+ critical: 224
+ soCritical: 225
+ soError: 226
+ ackWarn: 227
+ info: 228
+ track: 229
+ blockage: 230
+ grid: 231
+ warning: 234
+ tool1: 235
+ tool0: 236
+ label: 237
+ flight: 238
+ error: 239
+ annotate: 240
+ drawing1: 241
+ drawing2: 242
+ drawing3: 243
+ drawing4: 244
+ drawing5: 245
+ drawing6: 246
+ drawing7: 247
+ drawing8: 248
+ drawing9: 249
+ boundary: 250
+ pin: 251
+ net: 253
+ cell: 254
+ all: 255
+ customFill: 4294967284
+ fillOPC: 4294967285
+ redundant: 4294967288
+ gapFill: 4294967289
+ annotation: 4294967290
+ OPCAntiSerif: 4294967291
+ OPCSerif: 4294967292
+ slot: 4294967293
+ fill: 4294967294
+ drawing: 4294967295
+via_layers:
+ TPL1_C:
+ - [22, 4294967295]
+ - [43, 4294967295]
+ - [3, 4294967295]
+ PYL1_C:
+ - [4, 4294967295]
+ - [43, 4294967295]
+ - [22, 4294967295]
+ L1M1_C:
+ - [6, 4294967295]
+ - [5, 4294967295]
+ - [22, 4294967295]
+ M1M2_C:
+ - [8, 4294967295]
+ - [7, 4294967295]
+ - [6, 4294967295]
+ M2M3_C:
+ - [10, 4294967295]
+ - [9, 4294967295]
+ - [8, 4294967295]
+ M3M4_C:
+ - [13, 4294967295]
+ - [12, 4294967295]
+ - [10, 4294967295]
+ M4M5_C:
+ - [15, 4294967295]
+ - [14, 4294967295]
+ - [13, 4294967295]
diff --git a/src/templates_skywater130/mim/__init__.py b/src/templates_skywater130/mim/__init__.py
new file mode 100755
index 0000000..6ae3ea6
--- /dev/null
+++ b/src/templates_skywater130/mim/__init__.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
diff --git a/src/templates_skywater130/mim/tech.py b/src/templates_skywater130/mim/tech.py
new file mode 100755
index 0000000..2e13f62
--- /dev/null
+++ b/src/templates_skywater130/mim/tech.py
@@ -0,0 +1,280 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+from typing import Tuple
+
+from pybag.core import BBox
+
+from bag.layout.tech import TechInfo
+
+from xbase.layout.data import LayoutInfoBuilder, ViaInfo
+from xbase.layout.cap.tech import MIMTech
+from xbase.layout.cap.tech import MIMLayInfo
+
+
+class MIMTechSkywater130(MIMTech):
+ def __init__(self, tech_info: TechInfo) -> None:
+ MIMTech.__init__(self, tech_info)
+
+ # noinspection PyMethodMayBeStatic
+ def get_port_layers(self, mim_type: str) -> Tuple[int, int]:
+ if mim_type == 'standard' or mim_type == '45' or mim_type == 45:
+ return 4, 5
+ if mim_type == '34' or mim_type == 34:
+ return 3, 4
+ raise ValueError(f'Invalid mim_type={mim_type}. Use \'standard\' or \'45\' or \'34\'')
+
+ def get_mim_cap_info(self, bot_layer: int, top_layer: int, unit_width: int, unit_height: int,
+ num_rows: int, num_cols: int, dum_row_b: int, dum_row_t: int, dum_col_l: int, dum_col_r: int,
+ bot_w: int, top_w: int) -> MIMLayInfo:
+ assert bot_layer == top_layer - 1, 'MIMCap can exist between adjacent layers only'
+ cap_info = self.mim_config['cap_info']
+ if top_layer not in cap_info:
+ raise ValueError(f'MIMCap does not exist with top_layer={top_layer}')
+
+ cap_lp, cap_w, cap_sp = cap_info[top_layer]
+ bot_lp = self._tech_info.get_lay_purp_list(bot_layer)[0]
+ top_lp = self._tech_info.get_lay_purp_list(top_layer)[0]
+
+ width = num_cols * unit_width
+ width_total = (num_cols + dum_col_l + dum_col_r) * unit_width
+ height = num_rows * unit_height
+ height_total = (num_rows + dum_row_b + dum_row_t) * unit_height
+
+ if dum_row_b > 0 or dum_row_t > 0:
+ raise NotImplementedError('Contact Felicia')
+ if dum_col_r > 0:
+ raise NotImplementedError('Contact Felicia')
+
+ via_info = self.mim_config['via_info']
+ via_type, via_dim, via_sp, via_bot_enc, via_top_enc = via_info[bot_layer]
+
+ if min(width, height) < min(bot_w, top_w):
+ raise ValueError('Unit cell dimensions are too small')
+
+ # DRC rules
+ min_width: int = self.mim_config['min_width']
+ ratio: int = self.mim_config['max_ratio']
+ cap_bound: int = self.mim_config['top_to_cap_sp']
+
+ if min(width, height) < min_width:
+ raise ValueError(f'Unit cell dimensions have to be larger than {min_width}')
+
+ if top_layer == 4:
+ via_bnd: int = self.mim_config['capvia_cap']
+ bot_sp = -(- cap_sp // 2)
+ else:
+ via_bnd = via_bot_enc
+ bot_sp = bot_w
+
+ top_ext = 2 * top_w + cap_bound
+ bot_ext = 2 * bot_w + cap_bound
+
+ builder = LayoutInfoBuilder()
+
+ # Cap construction
+ # array
+ if max(num_rows, num_cols) > 1 or max(dum_row_b, dum_row_t, dum_col_l, dum_col_r) > 0:
+ cap_off_h = cap_sp + bot_ext
+
+ if unit_height / unit_width > ratio or unit_width / unit_height > ratio:
+ raise ValueError('Unit dimensions violate DRC rules')
+
+ tot_rows = num_rows + dum_row_b + dum_row_t
+ tot_cols = num_cols + dum_col_l + dum_col_r
+ block_w = unit_width
+ base_y = bot_sp + cap_bound
+ for ridx in range(0, tot_rows):
+ y_bot = base_y + ridx * (unit_height + cap_off_h)
+ for cidx in range(0, tot_cols):
+ xl_cap = bot_ext + cidx * (block_w + cap_off_h)
+ xh_cap = xl_cap + block_w
+ yl_cap = y_bot
+ yh_cap = y_bot + unit_height
+
+ xl_via = xl_cap + via_bnd
+ xh_via = xh_cap - via_bnd
+ yl_via = yl_cap + via_bnd
+ yh_via = yh_cap - via_bnd
+
+ builder.add_rect_arr(cap_lp, BBox(xl_cap, yl_cap, xh_cap, yh_cap))
+ builder.add_via(get_via_info(via_type, BBox(xl_via, yl_via, xh_via, yh_via),
+ via_dim, via_sp, via_bot_enc, via_top_enc))
+ if dum_col_l > 0 or dum_col_r > 0:
+ # for the actual cap
+ xl_top = width_total - width + dum_col_l * cap_off_h + bot_ext
+ xh_top = width_total + (tot_cols - 1) * cap_off_h + top_ext + bot_ext + cap_bound
+ yl_top = bot_sp + cap_bound
+ yh_top = height_total + (tot_rows - 1) * cap_off_h + bot_sp + cap_bound
+
+ xl_bot = width_total - width + dum_col_l * cap_off_h
+ xh_bot = width_total + (tot_cols - 1) * cap_off_h + bot_ext + cap_bound
+ yl_bot = bot_sp
+ yh_bot = height_total + (tot_rows - 1) * cap_off_h + 2 * cap_bound + bot_sp
+
+ builder.add_rect_arr(bot_lp, BBox(xl_bot, yl_bot, xh_bot, yh_bot))
+ builder.add_rect_arr(top_lp, BBox(xl_top, yl_top, xh_top, yh_top))
+
+ # for the dummy
+ xl_dtop = bot_ext
+ xh_dtop = width_total - width + (dum_col_l - 1) * cap_off_h + bot_ext + cap_bound
+ yl_dtop = bot_sp + cap_bound
+ yh_dtop = height + (tot_rows - 1) * cap_off_h + bot_sp + cap_bound
+
+ xl_dbot = 0
+ xh_dbot = width_total - width + (dum_col_l - 1) * cap_off_h + bot_ext + cap_bound
+ yl_dbot = bot_sp
+ yh_dbot = height + (tot_rows - 1) * cap_off_h + 2 * cap_bound + bot_sp
+
+ builder.add_rect_arr(bot_lp, BBox(xl_dbot, yl_dbot, xh_dbot, yh_dbot))
+ builder.add_rect_arr(top_lp, BBox(xl_dtop, yl_dtop, xh_dtop, yh_dtop))
+ else:
+ xl_top = bot_ext
+ xh_top = width + (tot_cols - 1) * cap_off_h + top_ext + bot_ext
+ yl_top = bot_sp + cap_bound
+ yh_top = height + (tot_rows - 1) * cap_off_h + bot_sp + cap_bound
+
+ xl_bot = 0
+ xh_bot = width + (tot_cols - 1) * cap_off_h + bot_ext + cap_bound
+ yl_bot = bot_sp
+ yh_bot = height + (tot_rows - 1) * cap_off_h + 2 * cap_bound + bot_sp
+
+ builder.add_rect_arr(bot_lp, BBox(xl_bot, yl_bot, xh_bot, yh_bot))
+ builder.add_rect_arr(top_lp, BBox(xl_top, yl_top, xh_top, yh_top))
+
+ # add top metal and bottom
+ w_tot = xh_top
+ h_tot = bot_sp + cap_bound + height + tot_rows * cap_off_h
+
+ pin_bot_yl = bot_sp
+ pin_bot_yh = h_tot - cap_sp
+
+ pin_top_yl = bot_sp + cap_bound
+ pin_top_yh = h_tot - cap_sp
+ pin_bot_xl = width_total - width + dum_col_l * cap_off_h
+ pin_top_xh = w_tot
+
+ bnd_box = BBox(0, 0, w_tot, h_tot)
+
+ # not arrayed
+ else:
+ xl_top = bot_ext
+ xh_top = width + top_ext + bot_ext
+ yl_top = bot_sp + cap_bound
+ yh_top = height + bot_sp + cap_bound
+
+ xl_bot = 0
+ xh_bot = width + bot_ext + cap_bound
+ yl_bot = bot_sp
+ yh_bot = height + 2 * cap_bound + bot_sp
+
+ builder.add_rect_arr(bot_lp, BBox(xl_bot, yl_bot, xh_bot, yh_bot))
+ builder.add_rect_arr(top_lp, BBox(xl_top, yl_top, xh_top, yh_top))
+
+ # This only deals with long widths
+ if width / height > ratio:
+ num_blocks = -(- max(width, height) // (ratio * min(width, height)))
+
+ block_w = -(- (width - (num_blocks - 1) * cap_sp) // num_blocks)
+ for bidx in range(0, num_blocks):
+ xl_cap = bot_ext + bidx * (block_w + cap_sp)
+ xh_cap = xl_cap + block_w
+ yl_cap = bot_sp + cap_bound
+ yh_cap = yl_cap + height
+
+ xl_via = xl_cap + via_bnd
+ xh_via = xh_cap - via_bnd
+ yl_via = yl_cap + via_bnd
+ yh_via = yh_cap - via_bnd
+
+ builder.add_rect_arr(cap_lp, BBox(xl_cap, yl_cap, xh_cap, yh_cap))
+ builder.add_via(get_via_info(via_type, BBox(xl_via, yl_via, xh_via, yh_via),
+ via_dim, via_sp, via_bot_enc, via_top_enc))
+
+ else:
+ xl_cap = bot_ext
+ xh_cap = xl_cap + width
+ yl_cap = bot_sp + cap_bound
+ yh_cap = yl_cap + height
+
+ xl_via = xl_cap + via_bnd
+ xh_via = xh_cap - via_bnd
+ yl_via = yl_cap + via_bnd
+ yh_via = yh_cap - via_bnd
+ builder.add_rect_arr(cap_lp, BBox(xl_cap, yl_cap, xh_cap, yh_cap))
+ builder.add_via(get_via_info(via_type, BBox(xl_via, yl_via, xh_via, yh_via),
+ via_dim, via_sp, via_bot_enc, via_top_enc))
+
+ w_tot = bot_ext + width + top_ext
+ h_tot = bot_sp + 2 * cap_bound + height + cap_sp
+
+ pin_bot_yl = bot_sp
+ pin_bot_yh = height + 2 * cap_bound + bot_sp
+
+ pin_top_yl = bot_sp + cap_bound
+ pin_top_yh = bot_sp + height + cap_bound
+ pin_bot_xl = 0
+ pin_top_xh = w_tot
+
+ # set size
+ bnd_box = BBox(0, 0, w_tot, h_tot)
+
+ return MIMLayInfo(builder.get_info(bnd_box), (pin_bot_yl, pin_bot_yh), (pin_top_yl, pin_top_yh),
+ pin_bot_xl, pin_top_xh)
+
+
+def get_via_info(via_type: str, box: BBox, via_dim: int, via_sp: int, bot_enc: int, top_enc: int) -> ViaInfo:
+ """Create vias over specified area."""
+ xc = (box.xl + box.xh) // 2
+ yc = (box.yl + box.yh) // 2
+
+ enc1 = (bot_enc, bot_enc, bot_enc, bot_enc)
+ enc2 = (top_enc, top_enc, top_enc, top_enc)
+
+ vnx = (box.xh - box.xl) // (via_dim + via_sp)
+ vny = (box.yh - box.yl) // (via_dim + via_sp)
+
+ nx = 1
+ ny = 1
+ return ViaInfo(via_type, xc, yc, via_dim, via_dim, enc1, enc2,
+ vnx, vny, via_sp, via_sp, nx, ny, 0, 0)
+
+ # viaInfo needs
+ # via_type - via name
+ # xc: x coordinate center
+ # yc: y coordinate center
+ # w: via width
+ # h: via height
+ # enc1: Tuple[int, int, int, int] = (0, 0, 0, 0)
+ # bottom layer via enclosure
+ # enc2: Tuple[int, int, int, int] = (0, 0, 0, 0)
+ # top layer via enclosure
+ # vnx: number of vias in x direction
+ # vny: number of vias in y direction
+ # vspx: via x spacing
+ # vspy: via y spacing
+ # nx: int = 1
+ # ny: int = 1
+ # spx: int = 0
+ # spy: int = 0
+
\ No newline at end of file
diff --git a/src/templates_skywater130/mos/__init__.py b/src/templates_skywater130/mos/__init__.py
new file mode 100755
index 0000000..50fa21e
--- /dev/null
+++ b/src/templates_skywater130/mos/__init__.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
diff --git a/src/templates_skywater130/mos/tech.py b/src/templates_skywater130/mos/tech.py
new file mode 100755
index 0000000..bda9506
--- /dev/null
+++ b/src/templates_skywater130/mos/tech.py
@@ -0,0 +1,963 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Tuple, FrozenSet, List, Mapping, Any, Union, Optional
+
+from dataclasses import dataclass
+
+from pybag.enum import Orient2D
+from pybag.core import BBox
+
+from bag.layout.tech import TechInfo
+from bag.layout.routing.grid import TrackSpec
+from bag.util.immutable import ImmutableSortedDict, ImmutableList, Param
+
+from xbase.layout.enum import MOSType, MOSPortType, MOSCutMode, MOSAbutMode, DeviceType
+from xbase.layout.data import LayoutInfoBuilder, ViaInfo, CornerLayInfo
+from xbase.layout.exception import ODImplantEnclosureError
+from xbase.layout.mos.tech import MOSTech
+from xbase.layout.mos.data import (
+ MOSRowSpecs, MOSRowInfo, BlkExtInfo, MOSEdgeInfo, MOSLayInfo, ExtWidthInfo, LayoutInfo,
+ ExtEndLayInfo, RowExtInfo
+)
+from ..util import add_base, add_base_mos, get_arr_edge_dim
+
+MConnInfoType = Tuple[int, int, Orient2D, int, Tuple[str, str]]
+
+
+@dataclass(eq=True, frozen=True)
+class ConnInfo:
+ w: int
+ len_min: int
+ sp_le: int
+ orient: Orient2D
+ via_w: int
+ via_h: int
+ via_sp: int
+ via_bot_enc: int
+ via_top_enc: int
+
+ def get_via_info(self, via_type: str, xc: int, yc: int, bot_w: int, ortho: bool = True,
+ num: int = 1, nx: int = 1, ny: int = 1, spx: int = 0, spy: int = 0) -> ViaInfo:
+ vw = self.via_w
+ vh = self.via_h
+ vsp = self.via_sp
+
+ bot_orient = self.orient
+ if ortho:
+ bot_orient = bot_orient.perpendicular()
+
+ if bot_orient is Orient2D.x:
+ bot_encx = self.via_bot_enc
+ bot_ency = (bot_w - vh) // 2
+ else:
+ bot_encx = (bot_w - vw) // 2
+ bot_ency = self.via_bot_enc
+
+ if self.orient is Orient2D.x:
+ top_encx = self.via_top_enc
+ top_ency = (self.w - vh) // 2
+ vnx = num
+ vny = 1
+ else:
+ top_encx = (self.w - vw) // 2
+ top_ency = self.via_top_enc
+ vnx = 1
+ vny = num
+
+ enc1 = (bot_encx, bot_encx, bot_ency, bot_ency)
+ enc2 = (top_encx, top_encx, top_ency, top_ency)
+ return ViaInfo(via_type, xc, yc, self.via_w, self.via_h, enc1, enc2,
+ vnx, vny, vsp, vsp, nx, ny, spx, spy)
+
+
+class MOSTechSkywater130(MOSTech):
+ ignore_vm_sp_le_layers: FrozenSet[str] = frozenset(('li1',))
+
+ def __init__(self, tech_info: TechInfo, lch: int, arr_options: Mapping[str, Any]) -> None:
+ MOSTech.__init__(self, tech_info, lch, arr_options)
+
+ @property
+ def can_draw_double_gate(self) -> bool:
+ return False
+
+ @property
+ def has_double_guard_ring(self) -> bool:
+ return True
+
+ @property
+ def blk_h_pitch(self) -> int:
+ return self.mos_config['blk_h_pitch']
+
+ @property
+ def end_h_min(self) -> int:
+ # return self.mos_config['imp_h_min'] // 2
+ end_margin: int = self.mos_config['end_margin']
+ return -(-end_margin//self.blk_h_pitch) * self.blk_h_pitch
+
+ @property
+ def min_sep_col(self) -> int:
+ sd_pitch = self.sd_pitch
+ od_spx: int = self.mos_config['od_spx']
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+ imp_sp: int = self.mos_config['imp_same_sp']
+ od_sep = max(od_spx, imp_sp + 2 * imp_od_encx)
+ ans = -(-(od_sep + sd_pitch) // sd_pitch)
+
+ return ans # This is not enforcing even col spacing for smallest possible spacing
+
+ @property
+ def sub_sep_col(self) -> int:
+ sd_pitch = self.sd_pitch
+ od_spx: int = self.mos_config['od_spx']
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+ imp_sp: int = self.mos_config['imp_diff_sp']
+ od_sep = max(od_spx, imp_sp + 2 * imp_od_encx)
+ ans = -(-(od_sep + sd_pitch) // sd_pitch)
+
+ return ans + (ans & 1)
+
+ @property
+ def min_sub_col(self) -> int:
+ return self.min_od_col
+
+ @property
+ def gr_edge_col(self) -> int:
+ return self.min_od_col
+
+ @property
+ def min_od_col(self) -> int:
+ lch = self.lch
+ sd_pitch = self.sd_pitch
+ od_po_extx = self.od_po_extx
+
+ od_w_min: int = self.mos_config['mos_w_range'][0]
+ return -(-max(0, od_w_min - 2 * od_po_extx - lch) // sd_pitch) + 1
+
+ @property
+ def abut_mode(self) -> MOSAbutMode:
+ return MOSAbutMode.NONE
+
+ @property
+ def od_po_extx(self) -> int:
+ return self.mos_config['od_po_extx']
+
+ @property
+ def well_w_edge(self) -> int:
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+ nwell_imp: int = self.mos_config['nwell_imp']
+ well_w_edge = -(self.sd_pitch - self.lch) // 2 + self.od_po_extx + nwell_imp + imp_od_encx
+ return -(-well_w_edge // self.sd_pitch) * self.sd_pitch
+
+ def get_max_col_spacing_from_tap(self, pad_prox: bool = True) -> int:
+ """Gets maximum columns from nearest well tap rule.
+
+ Parameters
+ ----------
+ pad_prox: Union[str, int, bool]
+ Proximity to signal pad to determine appropriate rule. Default True.
+ If True, cell is assumed close to pad diffusion. If False, cell is
+ assumed far from pad diffusion.
+ """
+ max_dist_tap_far = self.mos_config['latchup']['max_distance_from_tap__far']
+ max_dist_tap_near = self.mos_config['latchup']['max_distance_from_tap__near']
+ dist = max_dist_tap_near if pad_prox else max_dist_tap_far
+ col_dist = dist // self.sd_pitch
+ return col_dist
+
+ def get_conn_info(self, conn_layer: int, is_gate: bool) -> ConnInfo:
+ mconf = self.mos_config
+ wire_info = mconf['g_wire_info' if is_gate else 'd_wire_info']
+
+ idx = conn_layer - wire_info['bot_layer']
+ w, is_horiz, v_w, v_h, v_sp, v_bot_enc, v_top_enc = wire_info['info_list'][idx]
+ orient = Orient2D(int(is_horiz ^ 1))
+ tech_info = self.tech_info
+ lay, purp = tech_info.get_lay_purp_list(conn_layer)[0]
+ # make sure minimum length satisfies via enclosure rule
+ cur_len = 2 * v_top_enc + (v_w if is_horiz else v_h)
+ len_min = tech_info.get_next_length(lay, purp, orient, w, cur_len, even=True)
+ sp_le = tech_info.get_min_line_end_space(lay, w, purpose=purp, even=True)
+
+ return ConnInfo(w, len_min, sp_le, orient, v_w, v_h, v_sp, v_bot_enc, v_top_enc)
+
+ # noinspection PyMethodMayBeStatic
+ def can_short_adj_tracks(self, conn_layer: int) -> bool:
+ return False
+
+ def get_track_specs(self, conn_layer: int, top_layer: int) -> List[TrackSpec]:
+ assert conn_layer == 0, 'currently only work for conn_layer = 0'
+
+ grid_info = self.mos_config['grid_info']
+
+ return [TrackSpec(layer=lay, direction=Orient2D.y, width=vm_w,
+ space=vm_sp, offset=(num_sd * (vm_w + vm_sp)) // 2)
+ for lay, vm_w, vm_sp, num_sd in grid_info if conn_layer <= lay <= top_layer]
+
+ def get_edge_width(self, mos_arr_width: int, blk_pitch: int) -> int:
+ # w_edge_min = self.mos_config['imp_od_encx'] + self.sd_pitch // 2
+ # return = get_arr_edge_dim(mos_arr_width, w_edge_min, blk_pitch)
+ edge_margin: int = self.mos_config['edge_margin']
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+ od_extx = self.od_po_extx - (self.sd_pitch - self.lch) // 2
+ num_sd = -(-(od_extx + imp_od_encx) // self.sd_pitch)
+ return -(-edge_margin // self.sd_pitch) * self.sd_pitch + num_sd * self.sd_pitch
+
+ def get_mos_row_info(self, conn_layer: int, specs: MOSRowSpecs, bot_mos_type: MOSType,
+ top_mos_type: MOSType, global_options: Param) -> MOSRowInfo:
+ guard_ring: bool = specs.options.get('guard_ring', False)
+ guard_ring_col: bool = specs.options.get('guard_ring_col', False)
+
+ assert conn_layer == 0, 'currently only work for conn_layer = 0'
+
+ blk_p = self.blk_h_pitch
+
+ w = specs.width
+ w_sub = specs.sub_width
+ mos_type = specs.mos_type
+ threshold = specs.threshold
+
+ mconf = self.mos_config
+ po_spy: int = mconf['po_spy']
+ od_spy: int = mconf['od_spy']
+ po_h_gate: int = mconf['po_h_gate']
+ po_od_exty: int = mconf['po_od_exty']
+ mg_imp_spy: int = mconf['mg_imp_spy']
+ imp_h_min: int = mconf['imp_h_min']
+ imp_od_ency: int = mconf['imp_od_ency']
+ po_spy2 = po_spy // 2
+ imp_h_min2 = imp_h_min // 2
+
+ md_info = self.get_conn_info(0, False)
+ od_vency = md_info.via_bot_enc
+ md_top_vency = md_info.via_top_enc
+ md_vency = md_info.via_top_enc
+ md_spy = md_info.sp_le
+ md_h_min = md_info.len_min
+ v0_h = md_info.via_h
+
+ if mos_type.is_substrate:
+ mg_h = 0
+ else:
+ mg_info = self.get_conn_info(0, True)
+ mg_h = mg_info.w
+
+ po_yl = po_spy2
+ po_yh_gate = po_yl + po_h_gate
+
+ if mos_type.is_substrate:
+ od_yl = po_spy2 + po_od_exty
+ else:
+ po_yc_gate = (po_yl + po_yh_gate) // 2
+ gmd_yh = po_yc_gate + v0_h // 2 + md_vency
+ gmd_yl = min(po_yc_gate - v0_h // 2 - md_vency, gmd_yh - md_h_min)
+ # fix mg_imp spacing
+ imp_yl = max(imp_h_min2, po_yc_gate + mg_h // 2 + mg_imp_spy)
+ od_yl = imp_yl + imp_od_ency
+
+ dmd_yl = gmd_yh + md_spy
+ dvc_yl = dmd_yl + md_top_vency
+ od_yl = max(od_yl, dvc_yl - od_vency)
+
+ od_yh = od_yl + w
+ po_yh = od_yh + po_od_exty
+ blk_yh = max(od_yh + imp_od_ency + imp_h_min2, po_yh + po_spy2)
+ blk_yh = -(-blk_yh // blk_p) * blk_p
+
+ dmd_yl, dmd_yh, _ = self._get_conn_params(md_info, od_yl, od_yh)
+
+ if guard_ring:
+ dmd_yl = min(dmd_yl, od_yl)
+ dmd_yh = max(dmd_yh, od_yh)
+
+ if mos_type.is_substrate:
+ gmd_yl, gmd_yh = dmd_yl, dmd_yh
+
+ # return MOSRowInfo
+ top_einfo = RowExtInfo(
+ mos_type, threshold,
+ ImmutableSortedDict(dict(
+ mos_type=mos_type,
+ margins=dict(
+ od=(blk_yh - od_yh, od_spy),
+ po=(blk_yh - po_yh, po_spy),
+ md=(blk_yh - dmd_yh, md_spy),
+ ),
+ guard_ring=guard_ring,
+ guard_ring_col=guard_ring_col,
+ )),
+ )
+ bot_einfo = RowExtInfo(
+ mos_type, threshold,
+ ImmutableSortedDict(dict(
+ mos_type=mos_type,
+ margins=dict(
+ od=(od_yl, od_spy),
+ po=(po_yl, po_spy),
+ md=(gmd_yl, md_spy),
+ ),
+ guard_ring=guard_ring,
+ guard_ring_col=guard_ring_col,
+ )),
+ )
+ info = dict(
+ imp_y=(od_yl - imp_od_ency, od_yh + imp_od_ency),
+ od_y=(od_yl, od_yh),
+ po_y=(po_yh_gate, po_yh),
+ po_y_gate=(po_yl, po_yh_gate),
+ )
+
+ if mos_type.is_substrate:
+ g_y = ds_y = ds_g_y = sub_y = (dmd_yl, dmd_yh)
+ g_m_y = (0, po_yl)
+ ds_m_y = (po_yh, blk_yh)
+ else:
+ g_y = (gmd_yl, gmd_yh)
+ g_m_y = (0, po_yl)
+ ds_y = ds_g_y = sub_y = (dmd_yl, dmd_yh)
+ ds_m_y = (po_yh, blk_yh)
+ return MOSRowInfo(self.lch, w, w_sub, mos_type, specs.threshold, blk_yh, specs.flip,
+ top_einfo, bot_einfo, ImmutableSortedDict(info), g_y, g_m_y, ds_y,
+ ds_m_y, ds_g_y, sub_y, guard_ring=guard_ring, guard_ring_col=guard_ring_col)
+
+ def get_ext_width_info(self, bot_row_ext_info: RowExtInfo, top_row_ext_info: RowExtInfo,
+ ignore_vm_sp_le: bool = False) -> ExtWidthInfo:
+ assert not ignore_vm_sp_le, 'ignore_vm_sp_le is not supported'
+
+ blk_p = self.blk_h_pitch
+
+ bot_margins = bot_row_ext_info['margins']
+ top_margins = top_row_ext_info['margins']
+ ext_h_min = 0
+ for key, (bot_val, sp) in bot_margins.items():
+ top_info = top_margins.get(key, None)
+ if top_info is not None:
+ top_val = top_info[0]
+ ext_h_min = max(ext_h_min, sp - (top_val + bot_val))
+ w_min = -(-ext_h_min // blk_p)
+
+ return ExtWidthInfo([], w_min)
+
+ # noinspection PyMethodMayBeStatic
+ def get_extension_regions(self, bot_info: RowExtInfo, top_info: RowExtInfo, height: int
+ ) -> Tuple[MOSCutMode, int, int]:
+ bot_gr = bot_info.info['guard_ring'] or bot_info.info['guard_ring_col']
+ top_gr = top_info.info['guard_ring'] or top_info.info['guard_ring_col']
+ if bot_gr and top_gr:
+ cut_mode = MOSCutMode.BOTH
+ bot_exty = 0
+ top_exty = 0
+ elif _get_extend_bot_implant(bot_info, top_info):
+ # split at top
+ cut_mode = MOSCutMode.TOP
+ bot_exty = height
+ top_exty = 0
+ else:
+ # split at bottom
+ cut_mode = MOSCutMode.BOT
+ bot_exty = 0
+ top_exty = height
+
+ return cut_mode, bot_exty, top_exty
+
+ def get_mos_conn_info(self, row_info: MOSRowInfo, conn_layer: int, seg: int, w: int, stack: int,
+ g_on_s: bool, options: Param) -> MOSLayInfo:
+ assert conn_layer == 0, 'currently only work for conn_layer = 0'
+
+ sep_g = options.get('sep_g', False)
+ export_mid = options.get('export_mid', False)
+ export_mid = export_mid and stack == 2
+
+ sd_pitch = self.sd_pitch
+
+ height = row_info.height
+ row_type = row_info.row_type
+ imp_y: Tuple[int, int] = row_info['imp_y']
+ po_y_gate: Tuple[int, int] = row_info['po_y_gate']
+
+ # compute gate wires location
+ fg = seg * stack
+ wire_pitch = stack * sd_pitch
+ conn_pitch = 2 * wire_pitch
+ num_s = seg // 2 + 1
+ num_d = (seg + 1) // 2
+ s_xc = 0
+ d_xc = wire_pitch
+
+ # get gate wires
+ g_pitch = 2 * sd_pitch
+ if g_on_s:
+ g_xc = 0
+ num_g = fg // 2 + 1
+ else:
+ g_xc = sd_pitch
+ num_g = (fg + 1) // 2
+
+ # draw device
+ builder = LayoutInfoBuilder()
+ od_y = self._add_mos_active(builder, row_info, 0, fg, w)
+
+ # draw gate connection
+ self._draw_g_conn(builder, sep_g, g_xc, po_y_gate, fg, g_pitch, g_on_s)
+
+ # draw drain/source connections
+ d0_info = self.get_conn_info(0, False)
+ md_yl, md_yh, num_vc = self._get_conn_params(d0_info, od_y[0], od_y[1])
+ md_y = (md_yl, md_yh)
+ self._draw_ds_conn(builder, d0_info, od_y, md_y, num_vc,
+ d_xc, num_d, conn_pitch)
+ self._draw_ds_conn(builder, d0_info, od_y, md_y, num_vc,
+ s_xc, num_s, conn_pitch)
+
+ if export_mid:
+ m_xc = sd_pitch
+ num_m = fg + 1 - num_s - num_d
+ m_info = (m_xc, num_m, wire_pitch)
+ self._draw_ds_conn(builder, d0_info, od_y, md_y, num_vc,
+ m_xc, num_m, wire_pitch)
+ else:
+ m_info = None
+
+ bbox = BBox(0, 0, fg * sd_pitch, height)
+
+ edge_info = MOSEdgeInfo(mos_type=row_type, imp_y=imp_y, has_od=True)
+ be = BlkExtInfo(row_type, row_info.threshold, False, ImmutableList([(fg, row_type)]),
+ ImmutableSortedDict())
+ return MOSLayInfo(builder.get_info(bbox), edge_info, edge_info, be, be,
+ g_info=(g_xc, num_g, g_pitch), d_info=(d_xc, num_d, conn_pitch),
+ s_info=(s_xc, num_s, conn_pitch), m_info=m_info,
+ shorted_ports=ImmutableList([MOSPortType.G]))
+
+ def _draw_g_conn(self, builder: LayoutInfoBuilder, sep_g: bool, g_xc: int,
+ po_y_gate: Tuple[int, int], fg: int, conn_pitch: int, g_on_s: bool) -> None:
+ lch = self.lch
+ sd_pitch = self.sd_pitch
+ mconf = self.mos_config
+ npc_w: int = mconf['npc_w']
+ npc_h: int = mconf['npc_h']
+ npc_w2 = npc_w // 2
+ npc_h2 = npc_h // 2
+
+ g0_info = self.get_conn_info(0, True)
+
+ po_lp = self.tech_info.config['mos_lay_table']['PO']
+
+ if g_on_s:
+ g_xc = 0
+ num_g = fg // 2 + 1
+ po_xl_even = g_xc
+ po_xh_even = g_xc + sd_pitch // 2 + lch // 2
+ po_xl_odd = sd_pitch + sd_pitch // 2 - lch // 2
+ po_xh_odd = 2 * sd_pitch
+ else:
+ g_xc = sd_pitch
+ num_g = (fg + 1) // 2
+ po_xl_even = sd_pitch // 2 - lch // 2
+ po_xh_even = sd_pitch
+ po_xl_odd = sd_pitch
+ po_xh_odd = sd_pitch + sd_pitch // 2 + lch // 2
+
+ builder.add_rect_arr(po_lp, BBox(po_xl_even, po_y_gate[0], po_xh_even, po_y_gate[1]),
+ nx=(fg - (fg // 2)), spx=conn_pitch)
+ builder.add_rect_arr(po_lp, BBox(po_xl_odd, po_y_gate[0], po_xh_odd, po_y_gate[1]),
+ nx=(fg // 2), spx=conn_pitch)
+
+ po_yc_gate = (po_y_gate[0] + po_y_gate[1]) // 2
+ po_h_gate = sd_pitch - lch
+ builder.add_via(g0_info.get_via_info('PYL1_C', g_xc, po_yc_gate, po_h_gate,
+ ortho=False, num=1, nx=num_g, spx=conn_pitch))
+ # poly via draws npc layer wrong
+ npc_box = BBox(g_xc - npc_w2, po_yc_gate - npc_h2, g_xc + npc_w2, po_yc_gate + npc_h2)
+ builder.add_rect_arr(('npc', 'drawing'), npc_box, nx=num_g, spx=conn_pitch)
+
+ po_w_min = g0_info.len_min
+ if sep_g:
+ mp_xl = g_xc - po_w_min // 2
+ builder.add_rect_arr(po_lp, BBox(mp_xl, po_y_gate[0], mp_xl + po_w_min, po_y_gate[1]),
+ nx=num_g, spx=conn_pitch)
+ else:
+ mp_dx = g0_info.via_w
+ mp_xl = g_xc - mp_dx
+ mp_xh = g_xc + (num_g - 1) * conn_pitch + mp_dx
+ builder.add_rect_arr(po_lp, BBox(mp_xl, po_y_gate[0], mp_xh, po_y_gate[1]))
+
+ def _draw_ds_conn(self, builder: LayoutInfoBuilder, d0_info: ConnInfo,
+ od_y: Tuple[int, int], md_y: Tuple[int, int], num_vc: int,
+ xc: int, nx: int, spx: int) -> None:
+ # connect to MD
+ md_w = d0_info.w
+ vc_w = d0_info.via_w
+ vc_h = d0_info.via_h
+ vc_sp = d0_info.via_sp
+ vc_p = vc_w + vc_sp
+ vc_w2 = vc_w // 2
+ vc_h2 = vc_h // 2
+ md_w2 = md_w // 2
+ md_lp = self.tech_info.config['mos_lay_table']['MD']
+
+ od_yc = (od_y[0] + od_y[1]) // 2
+ vc_h_arr = num_vc * vc_p - vc_sp
+ vc_yc_bot = od_yc + (vc_h - vc_h_arr) // 2
+ vc_box = BBox(xc - vc_w2, vc_yc_bot - vc_h2, xc + vc_w2, vc_yc_bot + vc_h2)
+ md_box = BBox(xc - md_w2, md_y[0], xc + md_w2, md_y[1])
+ builder.add_rect_arr(('licon1', 'drawing'), vc_box, nx=nx, spx=spx, ny=num_vc, spy=vc_p)
+ builder.add_rect_arr(md_lp, md_box, nx=nx, spx=spx)
+
+ def get_mos_abut_info(self, row_info: MOSRowInfo, edgel: MOSEdgeInfo, edger: MOSEdgeInfo
+ ) -> LayoutInfo:
+ raise ValueError('This method is not supported in this technology.')
+
+ def get_mos_tap_info(self, row_info: MOSRowInfo, conn_layer: int, seg: int,
+ options: Param) -> MOSLayInfo:
+ assert conn_layer == 0, 'currently only work for conn_layer = 0'
+ row_type = row_info.row_type
+
+ guard_ring: bool = options.get('guard_ring', row_info.guard_ring)
+ guard_ring_col: bool = options.get('guard_ring_col', row_info.guard_ring_col)
+ gr = guard_ring or guard_ring_col
+ if gr:
+ sub_type: MOSType = options.get('sub_type', row_type.sub_type)
+ else:
+ sub_type: MOSType = row_type.sub_type
+
+ sd_pitch: int = self.sd_pitch
+
+ w: int = row_info.sub_width
+ height: int = row_info.height
+ imp_y: Tuple[int, int] = row_info['imp_y']
+
+ # draw device
+ builder = LayoutInfoBuilder()
+ # draws diffusion and tap
+ od_y = self._add_mos_active(builder, row_info, 0, seg, w, is_sub=True, sub_type=sub_type)
+
+ # draw drain/source connections
+ d0_info = self.get_conn_info(0, False)
+ md_yl, md_yh, num_vc = self._get_conn_params(d0_info, od_y[0], od_y[1])
+ md_y = (md_yl, md_yh)
+ if guard_ring:
+ md_y = row_info.ds_conn_y
+
+ # draws in vias connecting tap cell to metal 1
+ self._draw_ds_conn(builder, d0_info, od_y, md_y, num_vc, 0, seg + 1, sd_pitch)
+
+ bbox = BBox(0, 0, seg * sd_pitch, height)
+ edge_info = MOSEdgeInfo(mos_type=sub_type, imp_y=imp_y, has_od=True)
+ be = BlkExtInfo(row_type, row_info.threshold, gr, ImmutableList([(seg, sub_type)]),
+ ImmutableSortedDict())
+ wire_info = (0, seg + 1, sd_pitch)
+ return MOSLayInfo(builder.get_info(bbox), edge_info, edge_info, be, be,
+ g_info=wire_info, d_info=wire_info, s_info=wire_info,
+ shorted_ports=ImmutableList())
+
+ def get_mos_space_info(self, row_info: MOSRowInfo, num_cols: int, left_info: MOSEdgeInfo,
+ right_info: MOSEdgeInfo) -> MOSLayInfo:
+ lch = self.lch
+ sd_pitch = self.sd_pitch
+ od_po_extx = self.od_po_extx
+
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+
+ row_type = row_info.row_type
+ threshold = row_info.threshold
+ imp_y: Tuple[int, int] = row_info['imp_y']
+
+ blk_xh = num_cols * sd_pitch
+ blk_yh = row_info.height
+ bbox = BBox(0, 0, blk_xh, blk_yh)
+
+ # get information from edge information dictionary
+ # if MOSEdgeInfo evaluates to False, that means this space block is on the boundary.
+ if left_info:
+ typel: MOSType = left_info['mos_type']
+ if right_info:
+ typer: MOSType = right_info['mos_type']
+ else:
+ typer = typel
+ elif right_info:
+ typer: MOSType = right_info['mos_type']
+ typel = typer
+ else:
+ typel = typer = row_type
+
+ guard_ring = row_info.guard_ring or row_info.guard_ring_col
+
+ builder = LayoutInfoBuilder()
+
+ # find dummy OD columns
+ od_extx = od_po_extx - (sd_pitch - lch) // 2
+ delta_implant = od_extx + imp_od_encx
+ delta_implant = -(-delta_implant // sd_pitch) * sd_pitch
+ if typel == typer:
+ # same implant on left and right
+ if guard_ring and typel.is_substrate:
+ raise ValueError('Cannot have empty spaces between guard ring edges.')
+
+ be = BlkExtInfo(row_type, threshold, False, ImmutableList([(num_cols, typel)]),
+ ImmutableSortedDict())
+ add_base(builder, typel, threshold, imp_y, bbox)
+ edger = edgel = MOSEdgeInfo(mos_type=typel, imp_y=imp_y, has_od=False)
+ else:
+ # find implant split coordinate
+ # split closer to the side with the following priority:
+ # 1. is a opposite tap (i.e. ntap in nmos row)
+ # 2. is a substrate tap (i.e. ptap in nmos row)
+ if typel is not row_type:
+ if delta_implant > blk_xh:
+ raise ODImplantEnclosureError('Insufficient space to satisfy '
+ 'implant-OD horizontal enclosure.')
+ add_base(builder, typel, threshold, imp_y, BBox(0, 0, delta_implant, blk_yh))
+ xl = delta_implant
+ fgl = delta_implant // sd_pitch
+ else:
+ xl = 0
+ fgl = 0
+
+ if typer is not row_type:
+ xr = blk_xh - delta_implant
+ if xr < xl:
+ raise ODImplantEnclosureError('Insufficient space to satisfy '
+ 'implant-OD horizontal enclosure.')
+ add_base(builder, typer, threshold, imp_y, BBox(xr, 0, blk_xh, blk_yh))
+ fgr = delta_implant // sd_pitch
+ else:
+ xr = blk_xh
+ fgr = 0
+
+ if xr > xl:
+ # draw implant in middle region
+ fgm = (xr - xl) // sd_pitch
+ if typel is row_type:
+ fgl += fgm
+ add_base(builder, typel, threshold, imp_y, BBox(xl, 0, xr, blk_yh))
+ else:
+ fgr += fgm
+ add_base(builder, typer, threshold, imp_y, BBox(xl, 0, xr, blk_yh))
+
+ fg_dev_list = []
+ if fgl > 0:
+ fg_dev_list.append((fgl, typel))
+ if fgr > 0:
+ fg_dev_list.append((fgr, typer))
+
+ be = BlkExtInfo(row_type, threshold, guard_ring, ImmutableList(fg_dev_list),
+ ImmutableSortedDict())
+ edgel = MOSEdgeInfo(mos_type=typel, imp_y=imp_y, has_od=False)
+ edger = edgel.copy_with(mos_type=typer)
+
+ wire_info = (0, 0, 0)
+ return MOSLayInfo(builder.get_info(bbox), edgel, edger, be, be, g_info=wire_info,
+ d_info=wire_info, s_info=wire_info, shorted_ports=ImmutableList())
+
+ def get_mos_ext_info(self, num_cols: int, blk_h: int, bot_einfo: RowExtInfo,
+ top_einfo: RowExtInfo, gr_info: Tuple[int, int]) -> ExtEndLayInfo:
+ if _get_extend_bot_implant(bot_einfo, top_einfo):
+ row_type = bot_einfo.row_type
+ threshold = bot_einfo.threshold
+ else:
+ row_type = top_einfo.row_type
+ threshold = top_einfo.threshold
+ return self._get_mos_ext_info_helper(num_cols, blk_h, row_type, threshold)
+
+ def get_mos_ext_gr_info(self, num_cols: int, edge_cols: int, blk_h: int, bot_einfo: RowExtInfo,
+ top_einfo: RowExtInfo, sub_type: MOSType, einfo: MOSEdgeInfo
+ ) -> ExtEndLayInfo:
+ if _get_extend_bot_implant(bot_einfo, top_einfo):
+ threshold = bot_einfo.threshold
+ else:
+ threshold = top_einfo.threshold
+ return self._get_mos_ext_info_helper(num_cols, blk_h, sub_type, threshold, guard_ring=True)
+
+ def _get_mos_ext_info_helper(self, num_cols: int, blk_h: int, row_type: MOSType, threshold: str,
+ guard_ring: bool = False) -> ExtEndLayInfo:
+ sd_pitch = self.sd_pitch
+
+ blk_w = num_cols * sd_pitch
+ blk_rect = BBox(0, 0, blk_w, blk_h)
+
+ builder = LayoutInfoBuilder()
+
+ if guard_ring:
+ md_info = self.get_conn_info(0, False)
+ v_w = md_info.via_w
+ od_tap_extx = self.mos_config['od_tap_extx'] # determines the amount to extend material from licon
+ od_sd_dx = od_tap_extx + v_w // 2
+
+ od_lp = self.tech_info.config['mos_lay_table']['OD']['sub']
+ md_lp = self.tech_info.config['mos_lay_table']['MD']
+ od_xl = - od_sd_dx
+ od_xr = sd_pitch * (num_cols - 1) + od_sd_dx
+ builder.add_rect_arr(od_lp, BBox(od_xl, 0, od_xr, blk_h))
+ builder.add_rect_arr(md_lp, BBox(od_xl, 0, od_xr, blk_h))
+ blk_xl = od_xl - (blk_w - od_xr)
+ blk_rect = BBox(blk_xl, 0, blk_w, blk_h)
+ imp_y = (0, blk_h)
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+ add_base_mos(builder, row_type, threshold, imp_y, blk_rect,
+ imp_x=(od_xl - imp_od_encx, od_xr + imp_od_encx), is_sub=row_type.is_substrate)
+ else:
+ imp_y = (0, 0)
+ add_base(builder, row_type, threshold, imp_y, blk_rect)
+
+ edge_info = MOSEdgeInfo(blk_h=blk_h, row_type=row_type, mos_type=row_type, threshold=threshold, imp_y=imp_y)
+ return ExtEndLayInfo(builder.get_info(blk_rect), edge_info)
+
+ def get_ext_geometries(self, re_bot: RowExtInfo, re_top: RowExtInfo,
+ be_bot: ImmutableList[BlkExtInfo], be_top: ImmutableList[BlkExtInfo],
+ cut_mode: MOSCutMode, bot_exty: int, top_exty: int,
+ dx: int, dy: int, w_edge: int) -> LayoutInfo:
+ sd_pitch = self.sd_pitch
+ well_w_edge = self.well_w_edge
+
+ ymid = dy + bot_exty
+ ytop = ymid + top_exty
+
+ # draw extensions
+ builder = LayoutInfoBuilder()
+ if bot_exty > 0:
+ xcur = dx
+ for info in be_bot:
+ xcur = _add_blk_ext_info(sd_pitch, builder, info, xcur, dy, ymid)
+ w_tot = xcur + w_edge
+ _add_blk_ext_edge(sd_pitch, builder, be_bot[0], dy, ymid, w_edge, 0, well_w_edge)
+ _add_blk_ext_edge(sd_pitch, builder, be_bot[-1], dy, ymid, w_edge, w_tot, well_w_edge)
+ if top_exty > 0:
+ xcur = dx
+ for info in be_top:
+ xcur = _add_blk_ext_info(sd_pitch, builder, info, xcur, ymid, ytop)
+ w_tot = xcur + w_edge
+ _add_blk_ext_edge(sd_pitch, builder, be_top[0], ymid, ytop, w_edge, 0, well_w_edge)
+ _add_blk_ext_edge(sd_pitch, builder, be_top[-1], ymid, ytop, w_edge, w_tot, well_w_edge)
+
+ # Note: bbox not used, just pass in some value.
+ return builder.get_info(BBox(0, 0, 0, 0))
+
+ def get_mos_end_info(self, blk_h: int, num_cols: int, einfo: RowExtInfo) -> ExtEndLayInfo:
+ blk_rect = BBox(0, 0, num_cols * self.sd_pitch, blk_h)
+ builder = LayoutInfoBuilder()
+ row_type = einfo.row_type
+ threshold = einfo.threshold
+ imp_y = (blk_rect.yl, blk_rect.yl)
+ add_base(builder, row_type, threshold, imp_y, blk_rect)
+ edge_info = MOSEdgeInfo(row_type=row_type, imp_y=imp_y, threshold=threshold)
+ return ExtEndLayInfo(builder.get_info(blk_rect), edge_info)
+
+ def get_mos_row_edge_info(self, blk_w: int, rinfo: MOSRowInfo, einfo: MOSEdgeInfo
+ ) -> LayoutInfo:
+ blk_h = rinfo.height
+ mos_type: MOSType = einfo['mos_type']
+ return self._edge_info_helper(blk_w, blk_h, mos_type, rinfo.threshold, rinfo['imp_y'])
+
+ def get_mos_ext_edge_info(self, blk_w: int, einfo: MOSEdgeInfo) -> LayoutInfo:
+ row_type: MOSType = einfo['row_type']
+ threshold: str = einfo['threshold']
+ blk_h: int = einfo['blk_h']
+ imp_y: Tuple[int, int] = einfo['imp_y']
+ return self._edge_info_helper(blk_w, blk_h, row_type, threshold, imp_y)
+
+ def get_mos_corner_info(self, blk_w: int, blk_h: int, einfo: MOSEdgeInfo) -> CornerLayInfo:
+ lch = self.lch
+ sd_pitch = self.sd_pitch
+ well_w_edge = self.well_w_edge
+
+ row_type: MOSType = einfo['row_type']
+ threshold: str = einfo['threshold']
+
+ well_yl = 0
+ blk_rect = BBox(blk_w - sd_pitch, well_yl, blk_w, blk_h)
+ builder = LayoutInfoBuilder()
+
+ well_xl = blk_w - well_w_edge
+ add_base(builder, row_type, threshold, (blk_rect.yl, blk_rect.yl), blk_rect,
+ well_x=(well_xl, blk_w))
+
+ x_margins = dict(well=well_xl)
+ y_margins = dict(well=well_yl)
+ edgel = ImmutableSortedDict(dict(dev_type=DeviceType.MOS, lch=lch, margins=x_margins))
+ edgeb = ImmutableSortedDict(dict(dev_type=DeviceType.MOS, lch=lch, margins=y_margins))
+ return CornerLayInfo(builder.get_info(blk_rect), (0, 0), edgel, edgeb)
+
+ @staticmethod
+ def _get_conn_params(info: ConnInfo, bot_cl: int, bot_ch: int) -> Tuple[int, int, int]:
+ v_dim = info.via_h if info.orient is Orient2D.y else info.via_w
+ v_sp = info.via_sp
+ v_bot_enc = info.via_bot_enc
+ v_top_enc = info.via_top_enc
+ v_pitch = v_dim + v_sp
+
+ v_num = (bot_ch - bot_cl - v_bot_enc * 2 + v_sp) // v_pitch
+ v_dim_arr = v_num * v_pitch - v_sp
+ top_dim = max(info.len_min, v_dim_arr + 2 * v_top_enc)
+ top_cl = (bot_cl + bot_ch - top_dim) // 2
+ top_ch = top_cl + top_dim
+ return top_cl, top_ch, v_num
+
+ def _get_od_sep_col(self, spx: int) -> int:
+ lch = self.lch
+ sd_pitch = self.sd_pitch
+ od_po_extx = self.od_po_extx
+
+ return -(-(spx + lch + 2 * od_po_extx) // sd_pitch) - 1
+
+ def _add_mos_active(self, builder: LayoutInfoBuilder, row_info: MOSRowInfo,
+ start: int, stop: int, w: int, is_sub: bool = False, sub_type: Optional[MOSType] = None
+ ) -> Tuple[int, int]:
+ po_yl: int = row_info['po_y'][0]
+ od_yl: int = row_info['od_y'][0]
+ guard_ring: bool = row_info.guard_ring
+ guard_ring_col: bool = row_info.guard_ring_col
+ blk_yh: int = row_info.height
+
+ sd_pitch = self.sd_pitch
+
+ mconf = self.mos_config
+ po_h_min: int = mconf['po_h_min']
+ po_od_exty: int = mconf['po_od_exty']
+
+ md_info = self.get_conn_info(0, False)
+ v_w = md_info.via_w
+
+ # draw PO
+ od_yh = od_yl + w
+ if is_sub:
+ od_lp = self.tech_info.config['mos_lay_table']['OD']['sub']
+ od_tap_extx = mconf['od_tap_extx'] # determines the amount to extend material from licon
+ od_sd_dx = od_tap_extx + v_w // 2
+ else:
+ od_lp = self.tech_info.config['mos_lay_table']['OD']['active']
+ po_y = (po_yl, max(po_yl + po_h_min, od_yh + po_od_exty))
+ self._add_po_array(builder, po_y, start, stop)
+ od_sd_dx = sd_pitch // 2
+
+ # draw OD
+ od_xl = start * sd_pitch - od_sd_dx
+ od_xh = stop * sd_pitch + od_sd_dx
+ builder.add_rect_arr(od_lp, BBox(od_xl, od_yl, od_xh, od_yh))
+ imp_y = row_info['imp_y']
+ if is_sub:
+ md_lp = self.tech_info.config['mos_lay_table']['MD']
+ if guard_ring and stop - start > self.gr_edge_col:
+ if sub_type.is_n_plus:
+ imp_lp = ('nsdm', 'drawing')
+ else:
+ imp_lp = ('psdm', 'drawing')
+ imp_od_encx: int = mconf['imp_od_encx']
+ md_y = row_info.ds_conn_y
+ # OD, implant, li1 for left small rectangle
+ od_xh2 = start * sd_pitch + self.gr_edge_col * sd_pitch + od_sd_dx
+ builder.add_rect_arr(od_lp, BBox(od_xl, od_yh, od_xh2, blk_yh))
+ builder.add_rect_arr(imp_lp, BBox(od_xl - imp_od_encx, od_yh, od_xh2 + imp_od_encx, blk_yh))
+ builder.add_rect_arr(md_lp, BBox(od_xl, od_yh, od_xh2, blk_yh))
+ od_xl2 = stop * sd_pitch - self.gr_edge_col * sd_pitch - od_sd_dx
+ # OD, implant, li1 for right small rectangle
+ builder.add_rect_arr(od_lp, BBox(od_xl2, od_yh, od_xh, blk_yh))
+ builder.add_rect_arr(imp_lp, BBox(od_xl2 - imp_od_encx, od_yh, od_xh + imp_od_encx, blk_yh))
+ builder.add_rect_arr(md_lp, BBox(od_xl2, od_yh, od_xh, blk_yh))
+ # li1 for main OD
+ builder.add_rect_arr(md_lp, BBox(od_xl, md_y[0], od_xh, md_y[1]))
+ if guard_ring_col and stop - start == self.gr_edge_col:
+ # OD, implant, li1 for entire height
+ builder.add_rect_arr(od_lp, BBox(od_xl, 0, od_xh, blk_yh))
+ builder.add_rect_arr(md_lp, BBox(od_xl, 0, od_xh, blk_yh))
+ imp_y = (0, blk_yh)
+
+ # draw base
+ imp_od_encx: int = self.mos_config['imp_od_encx']
+ bbox = BBox(od_xl-imp_od_encx, 0, od_xh+imp_od_encx, blk_yh)
+
+ if is_sub:
+ mos_type = sub_type
+ else:
+ mos_type = row_info.row_type
+ add_base_mos(builder, mos_type, row_info.threshold, imp_y, bbox, is_sub=is_sub)
+
+ return od_yl, od_yh
+
+ def _add_po_array(self, builder: LayoutInfoBuilder, po_y: Tuple[int, int], start: int,
+ stop: int) -> None:
+ po_lp = self.tech_info.config['mos_lay_table']['PO']
+ lch = self.lch
+ sd_pitch = self.sd_pitch
+ po_x0 = (sd_pitch - lch) // 2 + sd_pitch * start
+ fg = stop - start
+ if po_y[1] > po_y[0]:
+ builder.add_rect_arr(po_lp, BBox(po_x0, po_y[0], po_x0 + lch, po_y[1]),
+ nx=fg, spx=sd_pitch)
+
+ def _edge_info_helper(self, blk_w: int, blk_h: int, row_type: MOSType, threshold: str,
+ imp_y: Tuple[int, int]) -> LayoutInfo:
+ sd_pitch = self.sd_pitch
+ well_w_edge = self.well_w_edge
+
+ blk_rect = BBox(blk_w - sd_pitch, 0, blk_w, blk_h)
+ builder = LayoutInfoBuilder()
+ add_base(builder, row_type, threshold, imp_y, blk_rect, well_x=(blk_w - well_w_edge, blk_w))
+ return builder.get_info(blk_rect)
+
+
+def _get_extend_bot_implant(bot_info: RowExtInfo, top_info: RowExtInfo) -> bool:
+ # prefer n implant over p implant, prefer transistor over substrate
+ bot_row_type = bot_info.row_type
+ top_row_type = top_info.row_type
+ if bot_row_type.is_pwell:
+ return True
+ if top_row_type.is_pwell:
+ return False
+ if not bot_row_type.is_substrate and top_row_type.is_substrate:
+ return True
+ if not top_row_type.is_substrate and bot_row_type.is_substrate:
+ return False
+ return bot_info.threshold < top_info.threshold
+
+
+def _add_blk_ext_edge(sd_pitch: int, builder: LayoutInfoBuilder, binfo: BlkExtInfo,
+ yl: int, yh: int, blk_w: int, w_tot: int, well_w_edge: int) -> None:
+ threshold = binfo.threshold
+
+ if w_tot == 0:
+ blk_rect = BBox(blk_w - sd_pitch, yl, blk_w, yh)
+ mos_idx = 0
+ well_x = (blk_w - well_w_edge, blk_w)
+ else:
+ xl = w_tot - blk_w
+ blk_rect = BBox(xl, yl, xl + sd_pitch, yh)
+ mos_idx = -1
+ well_x = (xl, xl + well_w_edge)
+
+ add_base(builder, binfo.fg_dev[mos_idx][1], threshold, (blk_rect.yl, blk_rect.yl),
+ blk_rect, well_x=well_x)
+
+
+def _add_blk_ext_info(sd_pitch: int, builder: LayoutInfoBuilder,
+ info: BlkExtInfo, xl: int, yl: int, yh: int) -> int:
+ threshold = info.threshold
+
+ # add base
+ xcur = xl
+ for fg, dev in info.fg_dev:
+ xh = xcur + fg * sd_pitch
+ add_base(builder, dev, threshold, (yl, yl), BBox(xcur, yl, xh, yh))
+ xcur = xh
+
+ return xcur
diff --git a/src/templates_skywater130/res/__init__.py b/src/templates_skywater130/res/__init__.py
new file mode 100755
index 0000000..6ae3ea6
--- /dev/null
+++ b/src/templates_skywater130/res/__init__.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
diff --git a/src/templates_skywater130/res/tech.py b/src/templates_skywater130/res/tech.py
new file mode 100644
index 0000000..f794f94
--- /dev/null
+++ b/src/templates_skywater130/res/tech.py
@@ -0,0 +1,231 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+from typing import Any, Optional, List, Tuple, Sequence, Mapping
+
+from pybag.enum import Orient2D
+from pybag.core import BBox
+
+from bag.util.immutable import ImmutableSortedDict, Param
+from bag.layout.routing.grid import TrackSpec
+from bag.layout.tech import TechInfo
+
+from xbase.layout.data import LayoutInfo, LayoutInfoBuilder, CornerLayInfo, ViaInfo
+from xbase.layout.array.data import ArrayLayInfo, ArrayEndInfo
+from xbase.layout.res.tech import ResTech
+
+
+class ResTechSkywater130(ResTech):
+ """Resistor class for SkyWater130
+ """
+ def __init__(self, tech_info: TechInfo, metal: bool = False) -> None:
+ ResTech.__init__(self, tech_info, metal=metal)
+ if metal:
+ raise RuntimeError("Metal resistors currently not supported")
+
+ def get_width(self, **kwargs) -> int:
+ if "unit_specs" not in kwargs:
+ raise RuntimeError("Please add unit_specs")
+ w_unit: int = kwargs['unit_specs']['params']['w']
+ w_min: int = self._res_config['w_min']
+ if w_unit < w_min:
+ raise ValueError(f'w={w_unit} has to be greater than or equal to w_min={w_min}.')
+ return w_unit
+
+ def get_length(self, **kwargs) -> int:
+ if "unit_specs" not in kwargs:
+ raise RuntimeError("Please add unit_specs")
+ l_unit: int = kwargs['unit_specs']['params']['l']
+ l_min: int = self._res_config['l_min']
+ if l_unit < l_min:
+ raise ValueError(f'l={l_unit} has to be greater than or equal to l_min={l_min}.')
+ return l_unit
+
+ @property
+ def min_size(self) -> Tuple[int, int]:
+ return self._res_config['min_size']
+
+ @property
+ def blk_pitch(self) -> Tuple[int, int]:
+ return self._res_config['blk_pitch']
+
+ def get_track_specs(self, conn_layer: int, top_layer: int) -> List[TrackSpec]:
+ grid_info: Sequence[Tuple[int, int, int]] = self._res_config['grid_info']
+
+ return [TrackSpec(layer=lay, direction=Orient2D.y, width=vm_w, space=vm_sp, offset=(vm_w + vm_sp) // 2)
+ for lay, vm_w, vm_sp in grid_info if conn_layer < lay <= top_layer]
+
+ def get_edge_width(self, info: ImmutableSortedDict[str, Any], arr_dim: int, blk_pitch: int) -> int:
+ edge_margin: int = self._res_config['edge_margin']
+ return -(- edge_margin // blk_pitch) * blk_pitch
+
+ def get_end_height(self, info: ImmutableSortedDict[str, Any], arr_dim: int, blk_pitch: int) -> int:
+ end_margin: int = self._res_config['end_margin']
+ return -(- end_margin // blk_pitch) * blk_pitch
+
+ def get_blk_info(self, conn_layer: int, w: int, h: int, nx: int, ny: int, **kwargs: Any) -> Optional[ArrayLayInfo]:
+ po_id_exty: int = self._res_config['po_id_exty']
+ npc_po_enc: int = self._res_config['npc_po_enc']
+ imp_npc_enc: Tuple[int, int] = self._res_config['imp_npc_enc']
+ tap_imp_h: int = self._res_config['tap_imp_h']
+ rlay_npc_enc: int = self._res_config['rlay_npc_enc']
+ npc_sp: int = self._res_config['npc_sp']
+
+ tap_imp_h2 = tap_imp_h // 2
+
+ # unit resistor dimensions
+ w_unit = self.get_width(**kwargs)
+ l_unit = self.get_length(**kwargs)
+
+ w_pitch, h_pitch = self.blk_pitch
+ w_blk = -(-(w_unit + 2 * (npc_po_enc + max(rlay_npc_enc, npc_sp // 2))) // w_pitch) * w_pitch
+ h_blk = -(-(l_unit + 2 * (po_id_exty + npc_po_enc + imp_npc_enc[1] + tap_imp_h2)) // h_pitch) * h_pitch
+ if w < w_blk or h < h_blk:
+ return None
+
+ res_lay_table = self._tech_info.config['res_lay_table']
+
+ # --- Compute layout --- #
+ top_bbox = BBox(0, 0, w, h)
+ builder = LayoutInfoBuilder()
+
+ # draw ID layer in the center
+ w2 = w // 2
+ h2 = h // 2
+ w_unit2 = w_unit // 2
+ l_unit2 = l_unit // 2
+ id_lp = res_lay_table['ID']
+ builder.add_rect_arr(id_lp, BBox(w2 - w_unit2, h2 - l_unit2, w2 + w_unit2, h2 + l_unit2))
+
+ # draw cut layer
+ cut_lp = res_lay_table['CUT']
+ builder.add_rect_arr(cut_lp, BBox(w2 - w_unit2, h2, w2 + w_unit2, h2 + 1))
+
+ # draw poly: same width as ID layer, height extends beyond ID layer
+ po_lp = res_lay_table['PO']
+ builder.add_rect_arr(po_lp, BBox(w2 - w_unit2, h2 - l_unit2 - po_id_exty,
+ w2 + w_unit2, h2 + l_unit2 + po_id_exty))
+
+ # draw npc enclosing poly
+ npc_lp = res_lay_table['NPC']
+ builder.add_rect_arr(npc_lp, BBox(w2 - w_unit2 - npc_po_enc, h2 - l_unit2 - po_id_exty - npc_po_enc,
+ w2 + w_unit2 + npc_po_enc, h2 + l_unit2 + po_id_exty + npc_po_enc))
+
+ # draw resistor layer: span entire width, extend beyond npc in height
+ res_type: str = kwargs['unit_specs']['params']['res_type']
+ r_lp = self._res_config['rlay'][res_type]
+ builder.add_rect_arr(r_lp, BBox(0, h2 - l_unit2 - po_id_exty - npc_po_enc - rlay_npc_enc,
+ w, h2 + l_unit2 + po_id_exty + npc_po_enc + rlay_npc_enc))
+
+ # draw implant layer extending beyond taps on top and bottom
+ imp_lp = res_lay_table['IMP']
+ builder.add_rect_arr(imp_lp, BBox(0, - tap_imp_h2, w, h + tap_imp_h2))
+
+ # add bottom tap
+ tap_h: int = self._res_config['tap_h']
+ tap_h2 = tap_h // 2
+ od_lp = res_lay_table['OD_sub']
+ tap_via_specs: Mapping[str, Any] = self._res_config['tap_via_specs']
+ tap_via_name: str = tap_via_specs['name']
+ tap_via_w, tap_via_h = tap_via_specs['dim']
+ tap_via_bot_enc: Tuple[int, int] = tap_via_specs['bot_enc']
+ tap_via_top_enc: Tuple[int, int] = tap_via_specs['top_enc']
+ tap_via_spx: int = tap_via_specs['spx']
+ tap_via_benc = (tap_via_bot_enc[0], tap_via_bot_enc[0], tap_via_bot_enc[1], tap_via_bot_enc[1])
+ tap_via_tenc = (tap_via_top_enc[0], tap_via_top_enc[0], tap_via_top_enc[1], tap_via_top_enc[1])
+ tap_vnx = (w_unit - 2 * tap_via_bot_enc[0] + tap_via_spx) // (tap_via_w + tap_via_spx)
+ tap_via_tot_w = tap_via_w * tap_vnx + tap_via_spx * (tap_vnx - 1)
+ builder.add_rect_arr(od_lp, BBox(w2 - w_unit2, - tap_h2, w2 + w_unit2, tap_h2))
+ builder.add_via(ViaInfo(tap_via_name, w2, 0, tap_via_w, tap_via_h, tap_via_benc, tap_via_tenc, tap_vnx, 1,
+ tap_via_spx))
+
+ # add top tap
+ builder.add_rect_arr(od_lp, BBox(w2 - w_unit2, h - tap_h2, w2 + w_unit2, h + tap_h2))
+ builder.add_via(ViaInfo(tap_via_name, w2, h, tap_via_w, tap_via_h, tap_via_benc, tap_via_tenc, tap_vnx, 1,
+ tap_via_spx))
+
+ # vias to conn_layer ports
+ po_via_specs: Mapping[str, Any] = self._res_config['po_via_specs']
+ po_via_name: str = po_via_specs['name']
+ po_via_w, po_via_h = po_via_specs['dim']
+ po_via_bot_enc: Tuple[int, int] = po_via_specs['bot_enc']
+ po_via_top_enc: Tuple[int, int] = po_via_specs['top_enc']
+ po_via_spx: int = po_via_specs['spx']
+ po_via_benc = (po_via_bot_enc[0], po_via_bot_enc[0], po_via_bot_enc[1], po_via_bot_enc[1])
+ po_via_tenc = (po_via_top_enc[0], po_via_top_enc[0], po_via_top_enc[1], po_via_top_enc[1])
+ po_vnx = (w_unit - 2 * po_via_bot_enc[0] + po_via_spx) // (po_via_w + po_via_spx)
+ po_via_tot_w = po_via_w * po_vnx + po_via_spx * (po_vnx - 1)
+ builder.add_via(ViaInfo(po_via_name, w2, h2 - l_unit2 - po_via_h // 2, po_via_w, po_via_h, po_via_benc,
+ po_via_tenc, po_vnx, 1, po_via_spx))
+ builder.add_via(ViaInfo(po_via_name, w2, h2 + l_unit2 + po_via_h // 2, po_via_w, po_via_h, po_via_benc,
+ po_via_tenc, po_vnx, 1, po_via_spx))
+
+ # ports on conn_layer
+ conn_lp = self._tech_info.get_lay_purp_list(self.conn_layer)[0]
+ minus_bbox = BBox(w2 - po_via_tot_w // 2 - po_via_top_enc[0], h2 - l_unit2 - po_via_h - po_via_top_enc[1],
+ w2 + po_via_tot_w // 2 + po_via_top_enc[0], h2 - l_unit2 + po_via_top_enc[1])
+ builder.add_rect_arr(conn_lp, minus_bbox)
+
+ plus_bbox = BBox(w2 - po_via_tot_w // 2 - po_via_top_enc[0], h2 + l_unit2 - po_via_top_enc[1],
+ w2 + po_via_tot_w // 2 + po_via_top_enc[0], h2 + l_unit2 + po_via_h + po_via_top_enc[1])
+ builder.add_rect_arr(conn_lp, plus_bbox)
+
+ tap_via_h2 = tap_via_h // 2
+ tap_via_tot_w2 = tap_via_tot_w // 2
+ bulk0_bbox = BBox(w2 - tap_via_tot_w2 - tap_via_top_enc[0], - tap_via_h2 - tap_via_top_enc[1],
+ w2 + tap_via_tot_w2 + tap_via_top_enc[0], tap_via_h2 + tap_via_top_enc[1])
+ builder.add_rect_arr(conn_lp, bulk0_bbox)
+ bulk1_bbox = BBox(w2 - tap_via_tot_w2 - tap_via_top_enc[0], h - tap_via_h2 - tap_via_top_enc[1],
+ w2 + tap_via_tot_w2 + tap_via_top_enc[0], h + tap_via_h2 + tap_via_top_enc[1])
+ builder.add_rect_arr(conn_lp, bulk1_bbox)
+
+ ports = dict(MINUS=[(conn_lp[0], [minus_bbox])], PLUS=[(conn_lp[0], [plus_bbox])],
+ BULK=[(conn_lp[0], [bulk0_bbox, bulk1_bbox])])
+
+ lay_info = builder.get_info(top_bbox)
+ edge_info = Param(dict(od_margin=0))
+ end_info = Param(dict(od_margin=0))
+ ports = Param(ports)
+ return ArrayLayInfo(lay_info, ports, edge_info, end_info)
+
+ # noinspection PyMethodMayBeStatic
+ def get_edge_info(self, w: int, h: int, info: ImmutableSortedDict[str, Any], **kwargs: Any) -> LayoutInfo:
+ builder = LayoutInfoBuilder()
+ blk_bbox = BBox(0, 0, w, h)
+ return builder.get_info(blk_bbox)
+
+ # noinspection PyMethodMayBeStatic
+ def get_end_info(self, w: int, h: int, info: ImmutableSortedDict[str, Any], **kwargs: Any) -> ArrayEndInfo:
+ builder = LayoutInfoBuilder()
+ blk_bbox = BBox(0, 0, w, h)
+ return ArrayEndInfo(builder.get_info(blk_bbox), ImmutableSortedDict())
+
+ # noinspection PyMethodMayBeStatic
+ def get_corner_info(self, w: int, h: int, info: ImmutableSortedDict[str, Any], **kwargs: Any) -> CornerLayInfo:
+ x_margins = dict(well=0, base=0)
+ y_margins = dict(well=0, base=0)
+ edgel = Param(dict(margins=x_margins))
+ edgeb = Param(dict(margins=y_margins))
+ builder = LayoutInfoBuilder()
+ blk_bbox = BBox(0, 0, w, h)
+ return CornerLayInfo(builder.get_info(blk_bbox), (0, 0), edgel, edgeb)
diff --git a/src/templates_skywater130/tech.py b/src/templates_skywater130/tech.py
new file mode 100755
index 0000000..ae5cb54
--- /dev/null
+++ b/src/templates_skywater130/tech.py
@@ -0,0 +1,173 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Tuple, Optional, Mapping
+
+from pybag.core import BBox
+
+from bag.util.immutable import Param
+from bag.layout.tech import TechInfo
+from bag.layout.template import TemplateBase
+
+from xbase.layout.enum import DeviceType
+
+from . import config as _config
+from . import config_fname as _config_fname
+from .mos.tech import MOSTechSkywater130
+from .mim.tech import MIMTechSkywater130
+# from .fill.tech import FillTechSkywater130
+from .res.tech import ResTechSkywater130
+
+
+class TechInfoSkywater130(TechInfo):
+ def __init__(self, process_params):
+ TechInfo.__init__(self, process_params, _config, _config_fname)
+
+ self.register_device_tech('mos', MOSTechSkywater130)
+ self.register_device_tech('mim', MIMTechSkywater130)
+ self.register_device_tech('res', ResTechSkywater130)
+ # self.register_device_tech('fill', FillTechSkywater130)
+
+ def get_margin(self, is_vertical: bool, edge1: Param, edge2: Optional[Param]) -> int:
+ if edge2 is None:
+ dev_type = edge1['dev_type']
+ if dev_type is DeviceType.MOS:
+ margins: Mapping[str, int] = edge1['margins']
+ table: Mapping[str, Tuple[int, int]] = self.config['margins']
+ max_sp = 0
+ for name, val in margins.items():
+ sp_tot = -(-table[name][is_vertical] // 2)
+ max_sp = max(sp_tot - val, max_sp)
+ return max_sp
+ else:
+ # TODO: implement this
+ raise ValueError('Not implemented yet, see developer.')
+ else:
+ # TODO: implement this
+ raise ValueError('Not implemented yet, see developer.')
+
+ def add_cell_boundary(self, template: TemplateBase, box: BBox) -> None:
+ if box.is_physical():
+ pt_list = [(box.xl, box.yl), (box.xl, box.yh), (box.xh, box.yh), (box.xh, box.yl)]
+ # template.add_boundary(BoundaryType.PR, pt_list)
+
+ def draw_device_blockage(self, template: TemplateBase) -> None:
+ pass
+
+ def get_metal_em_specs(self, layer: str, purpose: str, w: int, length: int = -1,
+ vertical: bool = False, dc_temp: int = -1000, rms_dt: int = -1000
+ ) -> Tuple[float, float, float]:
+ idc = self._get_metal_idc(layer, purpose, w, length, vertical, dc_temp)
+ irms = self._get_metal_irms(layer, purpose, w, rms_dt)
+ ipeak = float('inf')
+ return idc, irms, ipeak
+
+ def get_via_em_specs(self, layer_dir: int, layer: str, purpose: str, adj_layer: str,
+ adj_purpose: str, cut_w: int, cut_h: int, m_w: int = -1, m_l: int = -1,
+ adj_m_w: int = -1, adj_m_l: int = -1, array: bool = False,
+ dc_temp: int = -1000, rms_dt: int = -1000) -> Tuple[float, float, float]:
+ def_purpose = self.default_purpose
+ purpose = purpose or def_purpose
+ adj_purpose = adj_purpose or def_purpose
+
+ lay_vec = [None, None]
+ dim_vec = [None, None]
+
+ lay_vec[layer_dir] = (layer, purpose)
+ lay_vec[1 - layer_dir] = (adj_layer, adj_purpose)
+ dim_vec[layer_dir] = (m_w, m_l)
+ dim_vec[1 - layer_dir] = (adj_m_w, adj_m_l)
+
+ idc = self._get_via_idc(lay_vec[0], lay_vec[1], cut_w, cut_h, dim_vec[0], dim_vec[1],
+ array, dc_temp)
+ # via do not have AC current specs
+ irms = float('inf')
+ ipeak = float('inf')
+ return idc, irms, ipeak
+
+ def get_res_em_specs(self, res_type: str, w: int, *, length: int = -1,
+ dc_temp: int = -1000, rms_dt: int = -1000) -> Tuple[float, float, float]:
+ dc_temp = self.get_dc_temp(dc_temp)
+ rms_dt = self.get_rms_dt(rms_dt)
+
+ idc_scale = self.get_idc_scale_factor('', '', dc_temp, is_res=True)
+ idc = 1.0e-3 * w * idc_scale
+
+ irms = 1e-3 * (0.02 * rms_dt * w * (w + 0.5)) ** 0.5
+
+ ipeak = 5e-3 * 2 * w
+ return idc, irms, ipeak
+
+ # noinspection PyUnusedLocal,PyMethodMayBeStatic
+ def _get_metal_idc_factor(self, layer: str, purpose: str, w: int, length: int):
+ return 1
+
+ def _get_metal_idc(self, layer: str, purpose: str, w: int, length: int,
+ vertical: bool, dc_temp: int) -> float:
+ if vertical:
+ raise NotImplementedError('Vertical DC current not supported yet')
+
+ inorm, woff = 1.0, 0.0
+ idc = inorm * self._get_metal_idc_factor(layer, purpose, w, length) * (w - woff)
+ return self.get_idc_scale_factor(layer, purpose, self.get_dc_temp(dc_temp)) * idc * 1e-3
+
+ # noinspection PyUnusedLocal
+ def _get_metal_irms(self, layer: str, purpose: str, w: int, rms_dt: int):
+ b = 0.0443
+ k, wo, a = 6.0, 0.0, 0.2
+
+ irms_ma = (k * self.get_rms_dt(rms_dt) * (w - wo)**2 * (w - wo + a) / (w - wo + b))**0.5
+ return irms_ma * 1e-3
+
+ # noinspection PyUnusedLocal
+ def _get_via_idc(self, bot_lp: Tuple[str, str], top_lp: Tuple[str, str], cut_w: int,
+ cut_h: int, bot_dim: Tuple[int, int], top_dim: Tuple[int, int],
+ array: bool, dc_temp: int) -> float:
+ if bot_dim[0] > 0:
+ bf = self._get_metal_idc_factor(bot_lp[0], bot_lp[1], bot_dim[0], bot_dim[1])
+ else:
+ bf = 1.0
+
+ if top_dim[0] > 0:
+ tf = self._get_metal_idc_factor(top_lp[0], top_lp[1], top_dim[0], top_dim[1])
+ else:
+ tf = 1.0
+
+ factor = min(bf, tf)
+ via_id = self.config['via_id'][(bot_lp, top_lp)]
+
+ if via_id in ('M1_LiPo', 'M1_LiAct', 'M2_M1', 'M3_M2', 'M4_M3'):
+ if cut_w == cut_h == 64:
+ idc = 0.1
+ elif cut_w != cut_h:
+ idc = 0.2
+ else:
+ # we do not support 2X square via, as it has large
+ # spacing rule to square/rectangle vias.
+ raise ValueError('Unsupported via w/h: ({},{})'.format(cut_w, cut_h))
+ else:
+ idc = 0.4
+
+ temp = self.get_dc_temp(dc_temp)
+ return factor * self.get_idc_scale_factor(bot_lp[0], bot_lp[1], temp) * idc * 1e-3
diff --git a/src/templates_skywater130/util.py b/src/templates_skywater130/util.py
new file mode 100755
index 0000000..9d19f4f
--- /dev/null
+++ b/src/templates_skywater130/util.py
@@ -0,0 +1,115 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+
+from typing import Optional, Tuple
+
+from pybag.core import BBox
+
+from xbase.layout.enum import MOSType
+from xbase.layout.data import LayoutInfoBuilder
+
+
+def add_base(builder: LayoutInfoBuilder, row_type: MOSType, threshold: str, imp_y: Tuple[int, int],
+ rect: BBox, well_x: Optional[Tuple[int, int]] = None) -> None:
+ # draws nwell, n+ implant (ndsm) and p+ implant (pdsm)
+ # for non mos devices (corners, edges, etc)
+
+ if rect.is_physical():
+ if not row_type.is_pwell:
+ well_lp = ('nwell', 'drawing')
+ if well_x is None:
+ builder.add_rect_arr(well_lp, rect)
+ else:
+ builder.add_rect_arr(well_lp, BBox(well_x[0], rect.yl, well_x[1], rect.yh))
+
+ thres_lp = _get_thres_lp(row_type, threshold)
+ if thres_lp[0] != '':
+ builder.add_rect_arr(thres_lp, rect)
+
+
+def add_base_mos(builder: LayoutInfoBuilder, row_type: MOSType, threshold: str, imp_y: Tuple[int, int],
+ rect: BBox, well_x: Optional[Tuple[int, int]] = None, imp_x: Optional[Tuple[int, int]] = None,
+ is_sub: bool = False) -> None:
+ # new func draws nwell, n+ implant (ndsm) and p+ implant (pdsm)
+ if rect.is_physical():
+ # only draw nwells if not a tap cell and pch, or is tap cell and nch
+ if (not row_type.is_pwell and not is_sub) or (is_sub and row_type.is_n_plus):
+ well_lp = ('nwell', 'drawing')
+ if well_x is None:
+ builder.add_rect_arr(well_lp, rect)
+ else:
+ builder.add_rect_arr(well_lp, BBox(well_x[0], rect.yl, well_x[1], rect.yh))
+
+ # draw the respective implant
+ if row_type.is_n_plus:
+ imp_lp = ('nsdm', 'drawing')
+ else:
+ imp_lp = ('psdm', 'drawing')
+ if imp_x is None:
+ imp_bbox = BBox(rect.xl, imp_y[0], rect.xh, imp_y[1])
+ else:
+ imp_bbox = BBox(imp_x[0], imp_y[0], imp_x[1], imp_y[1])
+ builder.add_rect_arr(imp_lp, imp_bbox)
+
+ thres_lp = _get_thres_lp(row_type, threshold)
+ if thres_lp[0] != '':
+ builder.add_rect_arr(thres_lp, rect)
+
+
+def get_arr_edge_dim(arr_dim: int, edge_min_dim: int, blk_pitch: int, edge_pitch: int = 1,
+ edge_offset: int = 0) -> int:
+ dim_tot = -(-(arr_dim + 2 * edge_min_dim) // blk_pitch) * blk_pitch
+ dim2 = dim_tot - arr_dim
+ if dim2 & 1 == 1:
+ if blk_pitch & 1 == 1:
+ dim2 += blk_pitch
+ else:
+ raise RuntimeError(f'Parity Error: impossible to center ArrayBase with '
+ f'arr_dim={arr_dim}, blk_pitch={blk_pitch}, '
+ f'and edge_min_dim={edge_min_dim}.')
+
+ ans = dim2 // 2
+ if (ans - edge_offset) % edge_pitch != 0:
+ # precondition: we know that edge_pitch divides blk_pitch
+ blk_pitch2 = blk_pitch // 2
+ if blk_pitch & 1 != 0 or (ans + blk_pitch2 - edge_offset) % edge_pitch != 0:
+ raise RuntimeError(f'Parity Error: impossible to center ArrayBase with '
+ f'arr_dim={arr_dim}, blk_pitch={blk_pitch}, '
+ f'edge_min_dim={edge_min_dim}, edge_pitch={edge_pitch}, '
+ f'and edge_offset={edge_offset}')
+ ans += blk_pitch2
+
+ return ans
+
+
+def _get_thres_lp(row_type: MOSType, threshold: str) -> Tuple[str, str]:
+ if threshold == 'standard':
+ return '', ''
+ if threshold == 'lvt':
+ return 'lvtn', 'drawing'
+ if threshold == 'hvt':
+ if row_type.is_n_plus:
+ raise ValueError('Threshold hvt not supported for nmos')
+ return 'hvtp', 'drawing'
+ raise ValueError(f'unknown threshold: {threshold}')
diff --git a/tech_config.yaml b/tech_config.yaml
new file mode 100644
index 0000000..f1aedb0
--- /dev/null
+++ b/tech_config.yaml
@@ -0,0 +1,65 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+# the Technology class.
+class: "templates_skywater130.tech.TechInfoSkywater130"
+
+# default EM spec calculation settings
+em:
+ # DC current temperature
+ dc_temp: 70
+ # RMS current allowable temperature increase
+ rms_dt: 10
+
+# transistor technology parameters
+mos:
+ # the transistor width minimum resolution.
+ width_resolution: 1.0e-9
+ # the transistor length minimum resolution.
+ length_resolution: 1.0e-9
+
+# routing grid parameters
+routing_grid:
+ 0: [y, 34, 52]
+ 1: [x, 58, 28]
+ 2: [y, 56, 30]
+ 3: [x, 66, 106]
+ 4: [y, 66, 106]
+ 5: [x, 320, 368]
+
+# MOM cap parameters
+mom_cap:
+ standard:
+ bot_dir: x
+ info:
+ # w, sp, margin, num_ports, port_tr_w
+ 1: !!python/tuple [58, 28, 86, 2, 1]
+ 2: !!python/tuple [56, 28, 84, 2, 1]
+ 3: !!python/tuple [66, 60, 86, 2, 1]
+ 4: !!python/tuple [66, 60, 84, 1, 1]
+# 5: !!python/tuple [320, 320, 320, 1, 1]
+
+# fill parameters
+fill:
+ # sp_x, sp_y, margin_x, margin_y, density
+ 1: !!python/tuple [2000, 2000, 1000, 1000, 0.2]
+ 2: !!python/tuple [2000, 2000, 1000, 1000, 0.2]
+ 3: !!python/tuple [2000, 2000, 1000, 1000, 0.2]
+ 4: !!python/tuple [2000, 2000, 1000, 1000, 0.2]
+ 5: !!python/tuple [2000, 2000, 1000, 1000, 0.2]
diff --git a/workspace_setup/.bashrc b/workspace_setup/.bashrc
new file mode 100644
index 0000000..b12fac5
--- /dev/null
+++ b/workspace_setup/.bashrc
@@ -0,0 +1,62 @@
+#! /usr/bin/env bash
+export PYTHONPATH=""
+
+### Setup BAG
+source .bashrc_bag
+
+export PDK_HOME=$BAG_TECH_CONFIG_DIR/workspace_setup/PDK
+export SW_PDK_ROOT=/tools/commercial/skywater
+export SW_IP_HOME=${SW_PDK_ROOT}/s8_ip
+export METAL_STACK="s8phirs_10r"
+
+# location of various tools
+export MGC_HOME=/tools/mentor/calibre/aoi_cal_2022.2_24.16
+export CDS_INST_DIR=/tools/cadence/ICADVM/ICADVM181
+export PVS_HOME=/tools/cadence/PVS/PVS151
+export SPECTRE_HOME=/tools/cadence/SPECTRE/SPECTRE201
+export QRC_HOME=/tools/cadence/EXT/EXT191_ISR3
+export CMAKE_HOME=/tools/C/bag/programs/cmake-3.17.0
+
+export CDSHOME=${CDS_INST_DIR}
+export MMSIM_HOME=${SPECTRE_HOME}
+
+# OA settings
+export OA_CDS_ROOT=${CDS_INST_DIR}/oa_v22.60.s007
+export OA_PLUGIN_PATH=${OA_CDS_ROOT}/data/plugins:${OA_PLUGIN_PATH:-}
+export OA_BIT=64
+
+# PATH setup
+export PATH=${MGC_HOME}/bin:${PATH}
+export PATH=${PVS_HOME}/bin:${PATH}
+export PATH=${QRC_HOME}/bin:${PATH}
+export PATH=${CDS_INST_DIR}/tools/plot/bin:${PATH}
+export PATH=${CDS_INST_DIR}/tools/dfII/bin:${PATH}
+export PATH=${CDS_INST_DIR}/tools/bin:${PATH}
+export PATH=${MMSIM_HOME}/bin:${PATH}
+export PATH=${BAG_TOOLS_ROOT}/bin:${PATH}
+export PATH=${CMAKE_HOME}/bin:${PATH}
+
+# LD_LIBRARY_PATH setup
+export LD_LIBRARY_PATH=${BAG_WORK_DIR}/cadence_libs:${LD_LIBRARY_PATH}
+export LD_LIBRARY_PATH=${BAG_TOOLS_ROOT}/lib:${LD_LIBRARY_PATH}
+export LD_LIBRARY_PATH=${BAG_TOOLS_ROOT}/lib64:${LD_LIBRARY_PATH}
+
+# Virtuoso options
+export SPECTRE_DEFAULTS=-E
+export CDS_Netlisting_Mode="Analog"
+export CDS_AUTO_64BIT=ALL
+
+# License setup
+source /license/paths
+
+# Setup LSF (BWRC specific)
+# source /tools/support/lsf/conf/profile.lsf
+# export LBS_BASE_SYSTEM=LBS_LSF
+
+# Enable devtoolset
+source /opt/rh/devtoolset-8/enable
+source /opt/rh/rh-git29/enable
+source /opt/rh/httpd24/enable
+
+# pybag compiler settings
+export CMAKE_PREFIX_PATH=${BAG_TOOLS_ROOT}
diff --git a/workspace_setup/.bashrc_bag b/workspace_setup/.bashrc_bag
new file mode 100644
index 0000000..7d1c589
--- /dev/null
+++ b/workspace_setup/.bashrc_bag
@@ -0,0 +1,19 @@
+#! /usr/bin/env bash
+
+export BAG_WORK_DIR=$(pwd)
+export BAG_TOOLS_ROOT=/tools/C/bag/miniconda3/envs/latest
+export BAG_FRAMEWORK=${BAG_WORK_DIR}/BAG_framework
+export BAG_TECH_CONFIG_DIR=${BAG_WORK_DIR}/skywater130
+export BAG_TEMP_DIR=/path/to/scratch/${USER}/BAGTMP/skywater130
+export IPYTHONDIR=${BAG_WORK_DIR}/.ipython
+
+# disable hash-salting. We need stable hashing across sessions for caching purposes.
+export PYTHONHASHSEED=0
+# set program locations
+export BAG_PYTHON=${BAG_TOOLS_ROOT}/bin/python3
+
+# set location of BAG configuration file
+export BAG_CONFIG_PATH=${BAG_WORK_DIR}/bag_config.yaml
+
+# setup pybag
+export PYBAG_PYTHON=${BAG_PYTHON}
diff --git a/workspace_setup/.cdsenv b/workspace_setup/.cdsenv
new file mode 100644
index 0000000..49a05c5
--- /dev/null
+++ b/workspace_setup/.cdsenv
@@ -0,0 +1,91 @@
+license VLSL_UseNextLicense string "always"
+license ADEL_UseNextLicense string "always"
+license VLSXL_UseNextLicense string "always"
+license VSEL_UseNextLicense string "always"
+
+asimenv.startup simulator string "spectre"
+asimenv.startup projectDir string "/tools/scratch/$USER/skywater130"
+; Allows you to use multibit buses in stimulus files [#in_bits<0>], [#in_bits<1>], etc
+asimenv mappingMode string "oss"
+
+; have CDF term Order update whenever the symbol is updated
+auCore.misc updateCDFtermOrder boolean t
+ihdl maxNetNameLength int 16000
+
+layout stopLevel int 32
+layout dotsOn boolean t
+layout useTrueBBox boolean t
+layout xSnapSpacing float 0.001
+layout ySnapSpacing float 0.001
+layout displayPinNames boolean t
+
+; enable partial selection by defeault
+layout partialSelect boolean t
+
+; when move/copy/creating rectangles, automatically use the current mouse-over point.
+ui infix boolean t
+
+; set layout property dimension
+layout propEditorWidth int 500
+layout propEditorHeight int 580
+
+; set roman as default label font
+layout labelFontStyle cyclic "roman"
+
+; disable connectivity reference dialog box
+layoutXL lxSchematicDefaultApp cyclic "None"
+
+; turn off via stack selection
+graphic viaStackSelection boolean nil
+
+; correct schematic/symbol port order automatically.
+; this makes DARPA cosim demo look good.
+schematic disablePortOrderPopup boolean t
+
+; default waveform display setup
+viva.trace lineStyle string "solid"
+viva.trace lineThickness string "thick"
+viva.rectGraph foreground string "black"
+viva.rectGraph background string "white"
+viva.axis majorGridForeground string "black"
+viva.axis minorGridForeground string "gray"
+viva.axis foreground string "black"
+viva.axis background string "white"
+viva.axis font string "Default,14,-1,5,75,0,0,0,0,0"
+viva.graphLabel font string "Default,14,-1,5,75,0,0,0,0,0"
+; viva.probe font string "Default,14,-1,5,75,0,0,0,0,0"
+; viva.traceLegend font string "Default,14,-1,5,75,0,0,0,0,0"
+
+; LSF setup parameters
+
+; default job name
+; asimenv.distributed userDefinedJobName string "virtuoso_lsf"
+
+; use .cdsenv variables default and do not bring up job parameter form
+asimenv.distributed autoJobSubmit boolean t
+
+; set LSF resource string
+; asimenv.distributed selectLsfResourceString boolean t
+; asimenv.distributed lsfResourceString string "[ptile=4]"
+
+; set LSF queue name
+asimenv.distributed queueName string "normal"
+
+; use ssh for connection
+asimenv.distributed remoteShell string "ssh"
+
+; block ADE/Ocean until all jobs have finished
+asimenv.distributed block boolean t
+
+; LSF jobs log directory
+; asimenv.distributed logsDir string "./LSF_logs"
+
+; delete job after it's complete; allows job name recycling
+; asimenv.distributed deleteJob boolean t
+
+; if you submit a job with the same name, delete old data
+; asimenv.distributed removeJobData boolean t
+
+; number of processors to use for LSF
+asimenv.distributed selectLsfNoOfProcessors boolean t
+asimenv.distributed lsfNoOfProcessors string "4"
diff --git a/workspace_setup/.cdsenv.personal b/workspace_setup/.cdsenv.personal
new file mode 100644
index 0000000..96a7d7e
--- /dev/null
+++ b/workspace_setup/.cdsenv.personal
@@ -0,0 +1,4 @@
+; set default window size and location
+; schematic symWindowBBox string "((20 20) (1900 1060))"
+; schematic schWindowBBox string "((20 20) (1900 1060))"
+; layout leWindowBBox string "((20 20) (1900 1060))"
diff --git a/workspace_setup/.cdsinit b/workspace_setup/.cdsinit
new file mode 100644
index 0000000..b1b929b
--- /dev/null
+++ b/workspace_setup/.cdsinit
@@ -0,0 +1,151 @@
+
+printf("STARTING CDSINIT\n")
+
+; load configuration skill scripts.
+let( (configFileList file path saveSkillPath)
+ configFileList = '(
+ )
+ ; paths of the configuration files.
+ path = strcat(
+ ". ~ "
+ prependInstallPath("local ")
+ )
+ saveSkillPath=getSkillPath()
+ setSkillPath(path)
+
+ foreach(file configFileList
+ if(isFile(file) then
+ loadi(file)
+ )
+ )
+ setSkillPath(saveSkillPath)
+)
+
+; load key bindings scripts
+let( (bindKeyFileList file path saveSkillPath)
+ bindKeyFileList = '(
+ "leBindKeys.il"
+ "schBindKeys.il"
+ )
+ ; paths of key binding scripts
+ path = strcat(
+ ". ~ "
+ prependInstallPath("local ")
+ prependInstallPath("samples/local")
+ )
+ saveSkillPath=getSkillPath()
+ setSkillPath(path)
+
+ foreach(file bindKeyFileList
+ if(isFile(file ) then
+ loadi(file)
+ )
+ )
+ setSkillPath(saveSkillPath)
+)
+
+sstatus(writeProtect nil)
+
+let((skillPath)
+ skillPath= strcat(
+ ". ~ " ; Current & home directory
+ prependInstallPath("samples/techfile ") ; sample source technology files
+ )
+ setSkillPath(skillPath)
+)
+
+;
+; check CALIBRE_HOME
+;
+cal_home=getShellEnvVar("CALIBRE_HOME")
+if( cal_home==nil then
+ cal_home=getShellEnvVar("MGC_HOME")
+ if( cal_home!=nil then
+ printf("// CALIBRE_HOME environment variable not set; setting it to value of MGC_HOME\n");
+ )
+)
+
+if( cal_home!=nil && isDir(cal_home) && isReadable(cal_home) then
+
+ ; Load calibre.skl or calibre.4.3.skl, not both!
+
+ if( getShellEnvVar("MGC_CALIBRE_REALTIME_VIRTUOSO_ENABLED") &&
+ getShellEnvVar("MGC_REALTIME_HOME") && dbGetDatabaseType()=="OpenAccess" then
+ load(strcat(getShellEnvVar("MGC_REALTIME_HOME") "/lib/calibre.skl"))
+ else
+ ; Load calibre.skl for Cadence versions 4.4 and greater
+ load(strcat(cal_home "/lib/calibre.skl"))
+ )
+
+ ;;;;Load calibre.4.3.skl for Cadence version 4.3
+ ;;; load(strcat(cal_home "/lib/calibre.4.3.skl"))
+
+else
+
+ ; CALIBRE_HOME is not set correctly. Report the problem.
+
+ printf("// Calibre Error: Environment variable ")
+
+ if( cal_home==nil || cal_home=="" then
+ printf("CALIBRE_HOME is not set.");
+ else
+ if( !isDir(cal_home) then
+ printf("CALIBRE_HOME does not point to a directory.");
+ else
+ if( !isReadable(cal_home) then
+ printf("CALIBRE_HOME points to an unreadable directory.");
+ )
+ )
+ )
+ printf(" Calibre Skill Interface not loaded.\n")
+
+ ; Display a dialog box message about load failure.
+
+ hiDisplayAppDBox(
+ ?name 'MGCHOMEErrorDlg
+ ?dboxBanner "Calibre Error"
+ ?dboxText "Calibre Skill Interface not loaded."
+ ?dialogType hicErrorDialog
+ ?dialogStyle 'modal
+ ?buttonLayout 'Close
+ )
+)
+
+printf("END OF STANDARD CONFIG SETTINGS\n")
+
+; set default editor
+editor = "emacs"
+
+envLoadFile( "./.cdsenv" )
+
+if( isFile( ".cdsenv.personal" ) then
+ envLoadFile( ".cdsenv.personal" )
+)
+
+cdlOutKeys = list(nil
+ 'incFILE "$BAG_TECH_CONFIG_DIR/calibre_setup/source.added"
+)
+
+if( isFile( ".cdsinit.personal" ) then
+ load(".cdsinit.personal")
+)
+
+; open library manager
+ddsOpenLibManager()
+
+
+;; Set Default Model Files. Note the "#;" de-selects the model call.
+
+setModelFiles=strcat(
+ " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_fet"
+ " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_cell"
+ " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_parRC"
+ " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;tt_rc"
+ " " getShellEnvVar("PDK_HOME") "/MODELS/SPECTRE/" getShellEnvVar("METAL_STACK") "/Models/design_wrapper.lib.scs;npn_t"
+)
+
+envSetVal("spectre.envOpts" "modelFiles" 'string setModelFiles)
+envSetVal("spectre.envOpts" "controlMode" 'string "batch")
+
+
+printf("END OF CUSTOM CONFIG SETTINGS\n")
diff --git a/workspace_setup/.cdsinit.personal b/workspace_setup/.cdsinit.personal
new file mode 100644
index 0000000..a2b9d22
--- /dev/null
+++ b/workspace_setup/.cdsinit.personal
@@ -0,0 +1,5 @@
+; set simulation results to be saved in /tools/scratch
+envSetVal("asimenv.startup" "projectDir" 'string sprintf( nil "%s/simulation" getShellEnvVar( "BAG_TEMP_DIR" ) ) )
+
+; resize CIW window
+; hiResizeWindow(window(1) list(540:100 1260:480))
diff --git a/workspace_setup/.gitignore b/workspace_setup/.gitignore
new file mode 100644
index 0000000..36ca3d3
--- /dev/null
+++ b/workspace_setup/.gitignore
@@ -0,0 +1,75 @@
+# python/IDE files
+*.pyc
+__pycache__
+venv
+
+# Pycharm files
+.idea/tasks.xml
+.idea/usage.statistics.xml
+.idea/workspace.xml
+
+# misc edit/log files
+*~
+*.log
+core.*
+IPOPT.out
+lsyncd.status
+
+# misc BAG files
+bag_sim
+bag_stimuli
+BAG_server_port.txt
+BAG_sim_server_port.txt
+gen_outputs
+gen_outputs_scratch
+pytest_output
+
+
+# misc configuration/history files
+.ipynb_checkpoints
+.ipython
+.jupyter
+
+# generated files/directories
+BAGTMP
+calibre_run
+cdl_netlist
+cds.lib
+gen_libs
+netlist
+pvs_run
+sim
+simulation
+spectre_run
+
+# cadence files
+.abstract
+abstract*
+beol.drc.*
+.cadence
+cadence_libs
+*.cdslck
+.calibreviewsetup
+gui.tcl
+hdl.var
+lefout.list
+libManager.log.*
+PIPO.*
+si.env
+.tmp_*
+xOasisOut_cellMap.txt
+
+# calibre files
+.cgidrcdb
+.cgilvsdb
+calibreview.setup
+ihnl
+map
+.stimulusFile.auCdl
+
+# pvs files
+.preRcx.Last.State
+.QRC.run
+.qrc.Last.state
+
+.nfs*
diff --git a/workspace_setup/.simrc b/workspace_setup/.simrc
new file mode 100644
index 0000000..293bf73
--- /dev/null
+++ b/workspace_setup/.simrc
@@ -0,0 +1,3 @@
+auCdlCDFPinCntrl = t
+auCdlSkipMEGA = 't
+simDetectPCellFailure="ignore"
diff --git a/workspace_setup/PDK b/workspace_setup/PDK
new file mode 120000
index 0000000..61572bf
--- /dev/null
+++ b/workspace_setup/PDK
@@ -0,0 +1 @@
+/tools/commercial/skywater/swtech130/skywater-src-nda/s8/V2.0.0
\ No newline at end of file
diff --git a/workspace_setup/bag_config.yaml b/workspace_setup/bag_config.yaml
new file mode 100644
index 0000000..f375046
--- /dev/null
+++ b/workspace_setup/bag_config.yaml
@@ -0,0 +1,163 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+# BAG socket configuration
+socket:
+ # the host running the database. localhost if on the same machine.
+ host: "localhost"
+ # the port to communicate with.
+ port_file: "BAG_server_port.txt"
+ # the log file for socket communication debugging
+ log_file: "BAG_socket.log"
+ # number of messages allowed in a pipeline
+ pipeline: 100
+
+# CAD database configuration
+# Right now only virtuoso is supported.
+database:
+ # the python class that handles database interaction.
+# class: "bag.interface.oa.OAInterface"
+ class: "bag.interface.skill.SkillInterface"
+ # default directory to create generated libraries in.
+ default_lib_path: "${BAG_WORK_DIR}/gen_libs"
+ # If true, then everytime we generate schematic/layout from BAG, all opened cellviews are closed
+ close_all_cellviews: False
+
+ # configurations for schematic import and generation
+ schematic:
+ # technology library to configure new libraries with
+ tech_lib: "s8phirs_10r"
+ # libraries to exclude for schematic import
+ exclude_libraries: ["analogLib", "basic", "s8phirs_10r", "veriloga_lib", "ahdllib"]
+ # libraries to exclude for modeling purposes
+ model_exclude_libraries: []
+ # cells to exclude for modeling purposes
+ model_exclude_cells:
+ basic: ['noConn']
+ # symbol pin master
+ sympin: ["basic", "sympin", "symbolNN"]
+ # input pin master
+ ipin: ["basic", "ipin", "symbol"]
+ # output pin master
+ opin: ["basic", "opin", "symbol"]
+ # inout pin master
+ iopin: ["basic", "iopin", "symbolr"]
+ # simulators where termOrder CDF field should be filled
+ simulators: ["auLvs", "auCdl", "spectre", "hspiceD"]
+ # configurations used to create a Checker object to run LVS/RCX
+ checker:
+ # the Checker class.
+ checker_cls: 'bag.verification.calibre.Calibre'
+ # program used to run extraction
+ rcx_program: xrc
+ # maximum number of sub-processes BAG can launch.
+ max_workers: 2
+ # source.added location
+ source_added_file: "${BAG_TECH_CONFIG_DIR}/calibre_setup/source.added"
+ # root directories
+ root_dir:
+ drc: '${BAG_WORK_DIR}/calibre_run/drc'
+ lvs: '${BAG_WORK_DIR}/calibre_run/lvs'
+ rcx: '${BAG_WORK_DIR}/calibre_run/rcx'
+ # jinja template control files
+ template:
+ drc: '${BAG_TECH_CONFIG_DIR}/calibre_setup/drc.svrf'
+ lvs: '${BAG_TECH_CONFIG_DIR}/calibre_setup/lvs.svrf'
+ rcx: '${BAG_TECH_CONFIG_DIR}/calibre_setup/rcx.svrf'
+ # environment variables
+ env_vars:
+ drc: {}
+ lvs: {}
+ rcx: {}
+ link_files:
+ drc: []
+ lvs: []
+ rcx: []
+ # default parameters
+ params:
+ drc: {}
+ lvs: {}
+ rcx:
+ # extract_type: rc_coupled # r_only | c_only_decoupled | c_only_coupled | rc_decoupled | rc_coupled | rlc_decoupled | rlc_coupled for QRC
+ # extract_type: RCc # R | Cg | Cc | RCg | RCc for StarRC
+ extract_type: rcc # rcc | rc | r | c for xRC. See Parasitic Database (PDB) in manual
+ netlist_type: SPF # SPF or SPECTRE
+ # the SubProcessManager class
+ # mgr_class: 'bag.concurrent.lsf.LSFSubProcessManager' # runs jobs on the LSF
+ # mgr_kwargs:
+ # queue: rhel7 # LSF queue
+
+# Simulation configurations
+simulation:
+ # python class that talks with the simulator
+ class: "bag.simulation.spectre.SpectreInterface"
+ # maximum number of processes BAG can launch.
+ max_workers: 8
+ # when simulation goes long, a reminder message will be printed at this interval
+ update_timeout_ms: 120000
+ # amount of time to wait for process cancellation to succeed.
+ cancel_timeout_ms: 10000
+ # True to show interactive log viewer.
+ show_log_viewer: True
+ # corner configuration file
+ env_file: "${BAG_TECH_CONFIG_DIR}/corners_setup.yaml"
+ # command settings
+ kwargs:
+ # the command to start
+ command: spectre
+ # environment variables. Null for same environment as SkillOceanServer.
+ env: !!null
+ # True to run in 64-bit mode
+ run_64: True
+ # output format
+ format: psfbin #psfxl
+ # psf version
+ psfversion: '1.1'
+ options: ['++aps', '+lqtimeout', '0', '+mt=8', '+mp=8', '+postlayout']
+ # True if using pysrr for SRR to HDF5 conversion. False to use executable
+ # Executable runs faster for smaller simulation data, pysrr runs faster for highly parameterized simulation data
+ use_pysrr: False
+ # the SubProcessManager class
+ # mgr_class: 'bag.concurrent.lsf.LSFSubProcessManager' # runs jobs on the LSF
+ # mgr_kwargs:
+ # queue: rhel7 # LSF queue
+
+ compress: True
+ rtol: 1.0e-8
+ atol: 1.0e-22
+
+# LEF generation configuration
+lef:
+ class: 'bag.interface.abstract.AbstractInterface'
+ run_dir: 'abstract_run'
+ options_file: '${BAG_TECH_CONFIG_DIR}/abstract_setup/bag_abstract.options'
+ # the SubProcessManager class
+# mgr_class: 'bag.concurrent.lsf.LSFSubProcessManager' # runs jobs on the LSF
+# mgr_kwargs:
+# queue: rhel7 # LSF queue
+
+# technology specific configuration are stored in a separate file.
+# this field tells BAG where to look for it.
+tech_config_path: "${BAG_TECH_CONFIG_DIR}/tech_config.yaml"
+
+# BAG design libraries definition file.
+lib_defs: "bag_libs.def"
+
+# place to put new design libraries
+new_lib_path: "BagModules"
diff --git a/workspace_setup/bag_submodules.yaml b/workspace_setup/bag_submodules.yaml
new file mode 100644
index 0000000..cadb820
--- /dev/null
+++ b/workspace_setup/bag_submodules.yaml
@@ -0,0 +1,32 @@
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+BAG_framework:
+ url: git@10.8.0.1:bag/BAG_framework.git
+ branch: sim_refactor
+bag3_digital:
+ url: git@10.8.0.1:bag/bag3_digital.git
+ branch: sim_refactor
+bag3_testbenches:
+ url: git@10.8.0.1:bag/bag3_testbenches.git
+ branch: sim_refactor
+xbase_bcad:
+ url: git@10.8.0.1:bag/xbase_bcad.git
+ branch: sim_refactor
+
diff --git a/workspace_setup/cds.lib.core b/workspace_setup/cds.lib.core
new file mode 100644
index 0000000..ab18fcd
--- /dev/null
+++ b/workspace_setup/cds.lib.core
@@ -0,0 +1,24 @@
+# cadence base libraries
+DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib
+DEFINE basic $CDSHOME/tools/dfII/etc/cdslib/basic
+DEFINE ahdlLib $CDSHOME/tools/dfII/samples/artist/ahdlLib
+
+# technology base libraries
+DEFINE s8phirs_10r $BAG_TECH_CONFIG_DIR/workspace_setup/PDK/VirtuosoOA/libs/s8phirs_10r
+# legacy libraries
+DEFINE tech $BAG_TECH_CONFIG_DIR/workspace_setup/PDK/VirtuosoOA/libs/tech
+DEFINE technology_library $BAG_TECH_CONFIG_DIR/workspace_setup/PDK/VirtuosoOA/libs/technology_library
+DEFINE s8rf $BAG_TECH_CONFIG_DIR/workspace_setup/PDK/VirtuosoOA/libs/s8rf
+DEFINE s8rf2 $BAG_TECH_CONFIG_DIR/workspace_setup/PDK/VirtuosoOA/libs/s8rf2
+DEFINE s8rf2_dv $BAG_TECH_CONFIG_DIR/workspace_setup/PDK/VirtuosoOA/libs/s8rf2_dv
+DEFINE scs8hd /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/oa/scs8hd
+DEFINE scs8hd_dv /tools/commercial/skywater/swtech130/skywater-src-nda/scs8hd/V0.0.2/oa/scs8hd_dv
+
+ASSIGN tech DISPLAY Invisible
+ASSIGN technology_library DISPLAY Invisible
+#ASSIGN s8rf DISPLAY Invisible
+#ASSIGN s8rf2 DISPLAY Invisible
+#ASSIGN s8rf2_dv DISPLAY Invisible
+
+# BAG Libraries
+INCLUDE $BAG_WORK_DIR/cds.lib.bag
diff --git a/workspace_setup/display.drf b/workspace_setup/display.drf
new file mode 120000
index 0000000..14a5554
--- /dev/null
+++ b/workspace_setup/display.drf
@@ -0,0 +1 @@
+PDK/VirtuosoOA/libs/display.drf
\ No newline at end of file
diff --git a/workspace_setup/ipython_config.py b/workspace_setup/ipython_config.py
new file mode 100644
index 0000000..86807a0
--- /dev/null
+++ b/workspace_setup/ipython_config.py
@@ -0,0 +1,598 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+#
+# Configuration file for ipython.
+import os
+c = get_config()
+
+#------------------------------------------------------------------------------
+# InteractiveShellApp(Configurable) configuration
+#------------------------------------------------------------------------------
+
+## A Mixin for applications that start InteractiveShell instances.
+#
+# Provides configurables for loading extensions and executing files as part of
+# configuring a Shell environment.
+#
+# The following methods should be called by the :meth:`initialize` method of the
+# subclass:
+#
+# - :meth:`init_path`
+# - :meth:`init_shell` (to be implemented by the subclass)
+# - :meth:`init_gui_pylab`
+# - :meth:`init_extensions`
+# - :meth:`init_code`
+
+## Execute the given command string.
+#c.InteractiveShellApp.code_to_run = ''
+
+## Run the file referenced by the PYTHONSTARTUP environment variable at IPython
+# startup.
+#c.InteractiveShellApp.exec_PYTHONSTARTUP = True
+
+## List of files to run at IPython startup.
+c.InteractiveShellApp.exec_files = [
+]
+
+## lines of code to run at IPython startup.
+c.InteractiveShellApp.exec_lines = [
+ 'import numpy as np',
+ # enable autoreload
+ '%autoreload 2',
+]
+
+## A list of dotted module names of IPython extensions to load.
+c.InteractiveShellApp.extensions = ['autoreload']
+
+## dotted module name of an IPython extension to load.
+#c.InteractiveShellApp.extra_extension = ''
+
+## A file to be run
+#c.InteractiveShellApp.file_to_run = ''
+
+## Enable GUI event loop integration with any of ('glut', 'gtk', 'gtk2', 'gtk3',
+# 'osx', 'pyglet', 'qt', 'qt4', 'qt5', 'tk', 'wx', 'gtk2', 'qt4').
+# c.InteractiveShellApp.gui = 'qt5'
+
+## Should variables loaded at startup (by startup files, exec_lines, etc.) be
+# hidden from tools like %who?
+#c.InteractiveShellApp.hide_initial_ns = True
+
+## Configure matplotlib for interactive use with the default matplotlib backend.
+#c.InteractiveShellApp.matplotlib = None
+
+## Run the module as a script.
+#c.InteractiveShellApp.module_to_run = ''
+
+## Pre-load matplotlib and numpy for interactive use, selecting a particular
+# matplotlib backend and loop integration.
+#c.InteractiveShellApp.pylab = None
+
+## If true, IPython will populate the user namespace with numpy, pylab, etc. and
+# an ``import *`` is done from numpy and pylab, when using pylab mode.
+#
+# When False, pylab mode should not import any names into the user namespace.
+#c.InteractiveShellApp.pylab_import_all = True
+
+## Reraise exceptions encountered loading IPython extensions?
+#c.InteractiveShellApp.reraise_ipython_extension_failures = False
+
+#------------------------------------------------------------------------------
+# Application(SingletonConfigurable) configuration
+#------------------------------------------------------------------------------
+
+## This is an application.
+
+## The date format used by logging formatters for %(asctime)s
+#c.Application.log_datefmt = '%Y-%m-%d %H:%M:%S'
+
+## The Logging format template
+#c.Application.log_format = '[%(name)s]%(highlevel)s %(message)s'
+
+## Set the log level by value or name.
+#c.Application.log_level = 30
+
+#------------------------------------------------------------------------------
+# BaseIPythonApplication(Application) configuration
+#------------------------------------------------------------------------------
+
+## IPython: an enhanced interactive Python shell.
+
+## Whether to create profile dir if it doesn't exist
+#c.BaseIPythonApplication.auto_create = False
+
+## Whether to install the default config files into the profile dir. If a new
+# profile is being created, and IPython contains config files for that profile,
+# then they will be staged into the new directory. Otherwise, default config
+# files will be automatically generated.
+#c.BaseIPythonApplication.copy_config_files = False
+
+## Path to an extra config file to load.
+#
+# If specified, load this config file in addition to any other IPython config.
+#c.BaseIPythonApplication.extra_config_file = u''
+
+## The name of the IPython directory. This directory is used for logging
+# configuration (through profiles), history storage, etc. The default is usually
+# $HOME/.ipython. This option can also be specified through the environment
+# variable IPYTHONDIR.
+#c.BaseIPythonApplication.ipython_dir = u''
+
+## Whether to overwrite existing config files when copying
+#c.BaseIPythonApplication.overwrite = False
+
+## The IPython profile to use.
+#c.BaseIPythonApplication.profile = u'default'
+
+## Create a massive crash report when IPython encounters what may be an internal
+# error. The default is to append a short message to the usual traceback
+#c.BaseIPythonApplication.verbose_crash = False
+
+#------------------------------------------------------------------------------
+# TerminalIPythonApp(BaseIPythonApplication,InteractiveShellApp) configuration
+#------------------------------------------------------------------------------
+
+## Whether to display a banner upon starting IPython.
+# c.TerminalIPythonApp.display_banner = True
+
+## If a command or file is given via the command-line, e.g. 'ipython foo.py',
+# start an interactive shell after executing the file or command.
+#c.TerminalIPythonApp.force_interact = False
+
+## Start IPython quickly by skipping the loading of config files.
+#c.TerminalIPythonApp.quick = False
+
+#------------------------------------------------------------------------------
+# InteractiveShell(SingletonConfigurable) configuration
+#------------------------------------------------------------------------------
+
+## An enhanced, interactive shell for Python.
+
+## 'all', 'last', 'last_expr' or 'none', specifying which nodes should be run
+# interactively (displaying output from expressions).
+#c.InteractiveShell.ast_node_interactivity = 'last_expr'
+
+## A list of ast.NodeTransformer subclass instances, which will be applied to
+# user input before code is run.
+#c.InteractiveShell.ast_transformers = []
+
+## Make IPython automatically call any callable object even if you didn't type
+# explicit parentheses. For example, 'str 43' becomes 'str(43)' automatically.
+# The value can be '0' to disable the feature, '1' for 'smart' autocall, where
+# it is not applied if there are no more arguments on the line, and '2' for
+# 'full' autocall, where all callable objects are automatically called (even if
+# no arguments are present).
+#c.InteractiveShell.autocall = 0
+
+## Autoindent IPython code entered interactively.
+#c.InteractiveShell.autoindent = True
+
+## Enable magic commands to be called without the leading %.
+#c.InteractiveShell.automagic = True
+
+## The part of the banner to be printed before the profile
+#c.InteractiveShell.banner1 = 'Python 2.7.12 |Anaconda custom (64-bit)| (default, Jul 2 2016, 17:42:40) \nType "copyright", "credits" or "license" for more information.\n\nIPython 5.1.0 -- An enhanced Interactive Python.\n? -> Introduction and overview of IPython\'s features.\n%quickref -> Quick reference.\nhelp -> Python\'s own help system.\nobject? -> Details about \'object\', use \'object??\' for extra details.\n'
+
+## The part of the banner to be printed after the profile
+#c.InteractiveShell.banner2 = ''
+
+## Set the size of the output cache. The default is 1000, you can change it
+# permanently in your config file. Setting it to 0 completely disables the
+# caching system, and the minimum value accepted is 20 (if you provide a value
+# less than 20, it is reset to 0 and a warning is issued). This limit is
+# defined because otherwise you'll spend more time re-flushing a too small cache
+# than working
+#c.InteractiveShell.cache_size = 1000
+
+## Use colors for displaying information about objects. Because this information
+# is passed through a pager (like 'less'), and some pagers get confused with
+# color codes, this capability can be turned off.
+#c.InteractiveShell.color_info = True
+
+## Set the color scheme (NoColor, Neutral, Linux, or LightBG).
+c.InteractiveShell.colors = 'Linux'
+
+##
+#c.InteractiveShell.debug = False
+
+## **Deprecated**
+#
+# Will be removed in IPython 6.0
+#
+# Enable deep (recursive) reloading by default. IPython can use the deep_reload
+# module which reloads changes in modules recursively (it replaces the reload()
+# function, so you don't need to change anything to use it). `deep_reload`
+# forces a full reload of modules whose code may have changed, which the default
+# reload() function does not. When deep_reload is off, IPython will use the
+# normal reload(), but deep_reload will still be available as dreload().
+#c.InteractiveShell.deep_reload = False
+
+## Don't call post-execute functions that have failed in the past.
+#c.InteractiveShell.disable_failing_post_execute = False
+
+## If True, anything that would be passed to the pager will be displayed as
+# regular output instead.
+#c.InteractiveShell.display_page = False
+
+## (Provisional API) enables html representation in mime bundles sent to pagers.
+#c.InteractiveShell.enable_html_pager = False
+
+## Total length of command history
+#c.InteractiveShell.history_length = 10000
+
+## The number of saved history entries to be loaded into the history buffer at
+# startup.
+#c.InteractiveShell.history_load_length = 1000
+
+##
+#c.InteractiveShell.ipython_dir = ''
+
+## Start logging to the given file in append mode. Use `logfile` to specify a log
+# file to **overwrite** logs to.
+#c.InteractiveShell.logappend = ''
+
+## The name of the logfile to use.
+#c.InteractiveShell.logfile = ''
+
+## Start logging to the default log file in overwrite mode. Use `logappend` to
+# specify a log file to **append** logs to.
+#c.InteractiveShell.logstart = False
+
+##
+#c.InteractiveShell.object_info_string_level = 0
+
+## Automatically call the pdb debugger after every exception.
+#c.InteractiveShell.pdb = False
+
+## Deprecated since IPython 4.0 and ignored since 5.0, set
+# TerminalInteractiveShell.prompts object directly.
+#c.InteractiveShell.prompt_in1 = 'In [\\#]: '
+
+## Deprecated since IPython 4.0 and ignored since 5.0, set
+# TerminalInteractiveShell.prompts object directly.
+#c.InteractiveShell.prompt_in2 = ' .\\D.: '
+
+## Deprecated since IPython 4.0 and ignored since 5.0, set
+# TerminalInteractiveShell.prompts object directly.
+#c.InteractiveShell.prompt_out = 'Out[\\#]: '
+
+## Deprecated since IPython 4.0 and ignored since 5.0, set
+# TerminalInteractiveShell.prompts object directly.
+#c.InteractiveShell.prompts_pad_left = True
+
+##
+#c.InteractiveShell.quiet = False
+
+##
+#c.InteractiveShell.separate_in = '\n'
+
+##
+#c.InteractiveShell.separate_out = ''
+
+##
+#c.InteractiveShell.separate_out2 = ''
+
+## Show rewritten input, e.g. for autocall.
+#c.InteractiveShell.show_rewritten_input = True
+
+## Enables rich html representation of docstrings. (This requires the docrepr
+# module).
+#c.InteractiveShell.sphinxify_docstring = False
+
+##
+#c.InteractiveShell.wildcards_case_sensitive = True
+
+##
+#c.InteractiveShell.xmode = 'Context'
+
+#------------------------------------------------------------------------------
+# TerminalInteractiveShell(InteractiveShell) configuration
+#------------------------------------------------------------------------------
+
+## Set to confirm when you try to exit IPython with an EOF (Control-D in Unix,
+# Control-Z/Enter in Windows). By typing 'exit' or 'quit', you can force a
+# direct exit without any confirmation.
+#c.TerminalInteractiveShell.confirm_exit = True
+
+## Options for displaying tab completions, 'column', 'multicolumn', and
+# 'readlinelike'. These options are for `prompt_toolkit`, see `prompt_toolkit`
+# documentation for more information.
+#c.TerminalInteractiveShell.display_completions = 'multicolumn'
+
+## Shortcut style to use at the prompt. 'vi' or 'emacs'.
+#c.TerminalInteractiveShell.editing_mode = 'emacs'
+
+## Set the editor used by IPython (default to $EDITOR/vi/notepad).
+c.TerminalInteractiveShell.editor = 'gvim'
+
+## Highlight matching brackets .
+#c.TerminalInteractiveShell.highlight_matching_brackets = True
+
+## The name of a Pygments style to use for syntax highlighting: manni, igor,
+# lovelace, xcode, vim, autumn, vs, rrt, native, perldoc, borland, tango, emacs,
+# friendly, monokai, paraiso-dark, colorful, murphy, bw, pastie, algol_nu,
+# paraiso-light, trac, default, algol, fruity
+c.TerminalInteractiveShell.highlighting_style = 'paraiso-dark'
+
+## Override highlighting format for specific tokens
+#c.TerminalInteractiveShell.highlighting_style_overrides = {}
+
+## Enable mouse support in the prompt
+#c.TerminalInteractiveShell.mouse_support = False
+
+## Class used to generate Prompt token for prompt_toolkit
+#c.TerminalInteractiveShell.prompts_class = 'IPython.terminal.prompts.Prompts'
+
+## Use `raw_input` for the REPL, without completion, multiline input, and prompt
+# colors.
+#
+# Useful when controlling IPython as a subprocess, and piping STDIN/OUT/ERR.
+# Known usage are: IPython own testing machinery, and emacs inferior-shell
+# integration through elpy.
+#
+# This mode default to `True` if the `IPY_TEST_SIMPLE_PROMPT` environment
+# variable is set, or the current terminal is not a tty.
+#c.TerminalInteractiveShell.simple_prompt = False
+
+## Number of line at the bottom of the screen to reserve for the completion menu
+#c.TerminalInteractiveShell.space_for_menu = 6
+
+## Automatically set the terminal title
+c.TerminalInteractiveShell.term_title = False
+
+## Use 24bit colors instead of 256 colors in prompt highlighting. If your
+# terminal supports true color, the following command should print 'TRUECOLOR'
+# in orange: printf "\x1b[38;2;255;100;0mTRUECOLOR\x1b[0m\n"
+#c.TerminalInteractiveShell.true_color = False
+
+#------------------------------------------------------------------------------
+# HistoryAccessor(HistoryAccessorBase) configuration
+#------------------------------------------------------------------------------
+
+## Access the history database without adding to it.
+#
+# This is intended for use by standalone history tools. IPython shells use
+# HistoryManager, below, which is a subclass of this.
+
+## Options for configuring the SQLite connection
+#
+# These options are passed as keyword args to sqlite3.connect when establishing
+# database conenctions.
+#c.HistoryAccessor.connection_options = {}
+
+## enable the SQLite history
+#
+# set enabled=False to disable the SQLite history, in which case there will be
+# no stored history, no SQLite connection, and no background saving thread.
+# This may be necessary in some threaded environments where IPython is embedded.
+#c.HistoryAccessor.enabled = True
+
+## Path to file to use for SQLite history database.
+#
+# By default, IPython will put the history database in the IPython profile
+# directory. If you would rather share one history among profiles, you can set
+# this value in each, so that they are consistent.
+#
+# Due to an issue with fcntl, SQLite is known to misbehave on some NFS mounts.
+# If you see IPython hanging, try setting this to something on a local disk,
+# e.g::
+#
+# ipython --HistoryManager.hist_file=/tmp/ipython_hist.sqlite
+#
+# you can also use the specific value `:memory:` (including the colon at both
+# end but not the back ticks), to avoid creating an history file.
+#c.HistoryAccessor.hist_file = u''
+
+#------------------------------------------------------------------------------
+# HistoryManager(HistoryAccessor) configuration
+#------------------------------------------------------------------------------
+
+## A class to organize all history-related functionality in one place.
+
+## Write to database every x commands (higher values save disk access & power).
+# Values of 1 or less effectively disable caching.
+#c.HistoryManager.db_cache_size = 0
+
+## Should the history database include output? (default: no)
+#c.HistoryManager.db_log_output = False
+
+#------------------------------------------------------------------------------
+# ProfileDir(LoggingConfigurable) configuration
+#------------------------------------------------------------------------------
+
+## An object to manage the profile directory and its resources.
+#
+# The profile directory is used by all IPython applications, to manage
+# configuration, logging and security.
+#
+# This object knows how to find, create and manage these directories. This
+# should be used by any code that wants to handle profiles.
+
+## Set the profile location directly. This overrides the logic used by the
+# `profile` option.
+#c.ProfileDir.location = u''
+
+#------------------------------------------------------------------------------
+# BaseFormatter(Configurable) configuration
+#------------------------------------------------------------------------------
+
+## A base formatter class that is configurable.
+#
+# This formatter should usually be used as the base class of all formatters. It
+# is a traited :class:`Configurable` class and includes an extensible API for
+# users to determine how their objects are formatted. The following logic is
+# used to find a function to format an given object.
+#
+# 1. The object is introspected to see if it has a method with the name
+# :attr:`print_method`. If is does, that object is passed to that method
+# for formatting.
+# 2. If no print method is found, three internal dictionaries are consulted
+# to find print method: :attr:`singleton_printers`, :attr:`type_printers`
+# and :attr:`deferred_printers`.
+#
+# Users should use these dictionaries to register functions that will be used to
+# compute the format data for their objects (if those objects don't have the
+# special print methods). The easiest way of using these dictionaries is through
+# the :meth:`for_type` and :meth:`for_type_by_name` methods.
+#
+# If no function/callable is found to compute the format data, ``None`` is
+# returned and this format type is not used.
+
+##
+#c.BaseFormatter.deferred_printers = {}
+
+##
+#c.BaseFormatter.enabled = True
+
+##
+#c.BaseFormatter.singleton_printers = {}
+
+##
+#c.BaseFormatter.type_printers = {}
+
+#------------------------------------------------------------------------------
+# PlainTextFormatter(BaseFormatter) configuration
+#------------------------------------------------------------------------------
+
+## The default pretty-printer.
+#
+# This uses :mod:`IPython.lib.pretty` to compute the format data of the object.
+# If the object cannot be pretty printed, :func:`repr` is used. See the
+# documentation of :mod:`IPython.lib.pretty` for details on how to write pretty
+# printers. Here is a simple example::
+#
+# def dtype_pprinter(obj, p, cycle):
+# if cycle:
+# return p.text('dtype(...)')
+# if hasattr(obj, 'fields'):
+# if obj.fields is None:
+# p.text(repr(obj))
+# else:
+# p.begin_group(7, 'dtype([')
+# for i, field in enumerate(obj.descr):
+# if i > 0:
+# p.text(',')
+# p.breakable()
+# p.pretty(field)
+# p.end_group(7, '])')
+
+##
+#c.PlainTextFormatter.float_precision = ''
+
+## Truncate large collections (lists, dicts, tuples, sets) to this size.
+#
+# Set to 0 to disable truncation.
+#c.PlainTextFormatter.max_seq_length = 1000
+
+##
+#c.PlainTextFormatter.max_width = 79
+
+##
+#c.PlainTextFormatter.newline = '\n'
+
+##
+#c.PlainTextFormatter.pprint = True
+
+##
+#c.PlainTextFormatter.verbose = False
+
+#------------------------------------------------------------------------------
+# Completer(Configurable) configuration
+#------------------------------------------------------------------------------
+
+## Activate greedy completion PENDING DEPRECTION. this is now mostly taken care
+# of with Jedi.
+#
+# This will enable completion on elements of lists, results of function calls,
+# etc., but can be unsafe because the code is actually evaluated on TAB.
+#c.Completer.greedy = False
+
+#------------------------------------------------------------------------------
+# IPCompleter(Completer) configuration
+#------------------------------------------------------------------------------
+
+## Extension of the completer class with IPython-specific features
+
+## DEPRECATED as of version 5.0.
+#
+# Instruct the completer to use __all__ for the completion
+#
+# Specifically, when completing on ``object.<tab>``.
+#
+# When True: only those names in obj.__all__ will be included.
+#
+# When False [default]: the __all__ attribute is ignored
+#c.IPCompleter.limit_to__all__ = False
+
+## Whether to merge completion results into a single list
+#
+# If False, only the completion results from the first non-empty completer will
+# be returned.
+#c.IPCompleter.merge_completions = True
+
+## Instruct the completer to omit private method names
+#
+# Specifically, when completing on ``object.<tab>``.
+#
+# When 2 [default]: all names that start with '_' will be excluded.
+#
+# When 1: all 'magic' names (``__foo__``) will be excluded.
+#
+# When 0: nothing will be excluded.
+#c.IPCompleter.omit__names = 2
+
+#------------------------------------------------------------------------------
+# ScriptMagics(Magics) configuration
+#------------------------------------------------------------------------------
+
+## Magics for talking to scripts
+#
+# This defines a base `%%script` cell magic for running a cell with a program in
+# a subprocess, and registers a few top-level magics that call %%script with
+# common interpreters.
+
+## Extra script cell magics to define
+#
+# This generates simple wrappers of `%%script foo` as `%%foo`.
+#
+# If you want to add script magics that aren't on your path, specify them in
+# script_paths
+#c.ScriptMagics.script_magics = []
+
+## Dict mapping short 'ruby' names to full paths, such as '/opt/secret/bin/ruby'
+#
+# Only necessary for items in script_magics where the default path will not find
+# the right interpreter.
+#c.ScriptMagics.script_paths = {}
+
+#------------------------------------------------------------------------------
+# StoreMagics(Magics) configuration
+#------------------------------------------------------------------------------
+
+## Lightweight persistence for python variables.
+#
+# Provides the %store magic.
+
+## If True, any %store-d variables will be automatically restored when IPython
+# starts.
+#c.StoreMagics.autorestore = False
diff --git a/workspace_setup/leBindKeys.il b/workspace_setup/leBindKeys.il
new file mode 100644
index 0000000..701d345
--- /dev/null
+++ b/workspace_setup/leBindKeys.il
@@ -0,0 +1,127 @@
+;;-----------------------------------------------------------------------------
+;; Bindkeys for 'Layout'
+;; Inherited by:
+;; * Dracula Interactive
+;; * High Capacity Power IR/EM
+;; * NC-Verilog-MaskLayout
+;; * Other-Layout
+;; * Other-MaskLayout
+;; * Other-Symbolic
+;; * Pcell
+;; * Power IR/EM
+;; * Spectre-Layout
+;; * Spectre-MaskLayout
+;; * Spectre-Symbolic
+;; * UltraSim-Layout
+;; * UltraSim-MaskLayout
+;; * UltraSim-Symbolic
+;; * VLS-GXL
+;; * Virtuoso CE
+;; * Virtuoso XL
+;; * adegxl-maskLayout
+;; * adexl-maskLayout
+;; * parasitics-MaskLayout
+;;-----------------------------------------------------------------------------
+
+procedure(enable_sch_layers()
+ leSetLayerVisible( list("wire" "label") t )
+ leSetLayerVisible( list("wire" "drawing") t )
+ leSetLayerVisible( list("pin" "label") t )
+ leSetLayerVisible( list("pin" "drawing") t )
+ leSetLayerVisible( list("device" "drawing") t )
+ leSetLayerVisible( list("device" "drawing1") t )
+ leSetLayerVisible( list("device" "label") t )
+ leSetLayerVisible( list("instance" "label") t )
+ leSetLayerVisible( list("border" "drawing") t )
+
+ leSetLayerVisible( list("instance" "drawing") t )
+ leSetLayerVisible( list("text" "drawing") t )
+ leSetLayerVisible( list("device" "annotate") t )
+)
+
+procedure(show_od_m1()
+ leSetEntryLayer(list("poly" "drawing"))
+ leSetAllLayerVisible(nil)
+ leSetLayerVisible(list("nwell" "drawing") t)
+ leSetLayerVisible(list("nsdm" "drawing") t)
+ leSetLayerVisible(list("psdm" "drawing") t)
+ leSetLayerVisible(list("npc" "drawing") t)
+ leSetLayerVisible(list("diff" "drawing") t)
+ leSetLayerVisible(list("tap" "drawing") t)
+ leSetLayerVisible(list("poly" "drawing") t)
+ leSetLayerVisible(list("lvtn" "drawing") t)
+ leSetLayerVisible(list("hvtp" "drawing") t)
+ leSetLayerVisible(list("li1" "drawing") t)
+ leSetLayerVisible(list("licon1" "drawing") t)
+ leSetLayerVisible(list("mcon" "drawing") t)
+ leSetLayerVisible(list("met1" "drawing") t)
+ leSetLayerVisible(list("met1" "pin") t)
+
+ enable_sch_layers()
+ hiRedraw()
+)
+
+procedure(toggle_od()
+ leSetLayerVisible(list("diff" "drawing") not(leIsLayerVisible(list("diff" "drawing"))))
+ hiRedraw()
+)
+
+procedure( show_adjacent_metals( bot_layer )
+ let( (bot_name top_name via_name bot_dum top_dum)
+ sprintf(bot_name "met%d" bot_layer)
+ if( bot_layer < 2 then
+ sprintf(via_name "via")
+ else
+ sprintf(via_name "via%d" bot_layer)
+ )
+ sprintf(top_name "met%d" bot_layer + 1)
+
+ leSetEntryLayer(list(bot_name "drawing"))
+ leSetAllLayerVisible(nil)
+ leSetLayerVisible(list(bot_name "drawing") t)
+ leSetLayerVisible(list(bot_name "pin") t)
+ leSetLayerVisible(list(top_name "drawing") t)
+ leSetLayerVisible(list(top_name "pin") t)
+ leSetLayerVisible(list(via_name "drawing") t)
+ enable_sch_layers()
+ hiRedraw()
+ )
+)
+
+
+procedure( toggle_metal( layer_id )
+ let( (metal_name draw_layer dum_layer pin_layer exc_layer)
+ sprintf(metal_name "met%d" layer_id)
+ draw_layer = list(metal_name "drawing")
+ pin_layer = list(metal_name "pin")
+ leSetLayerVisible(draw_layer not(leIsLayerVisible(draw_layer)))
+ leSetLayerVisible(pin_layer not(leIsLayerVisible(pin_layer)))
+ hiRedraw()
+ )
+)
+
+
+hiSetBindKeys( "Layout" list(
+ list("Ctrl<Key>q" "leSetAllLayerVisible(t) hiRedraw()")
+ list("<Key>`" "show_od_m1()")
+ list("<Key>1" "show_adjacent_metals(1)")
+ list("<Key>2" "show_adjacent_metals(2)")
+ list("<Key>3" "show_adjacent_metals(3)")
+ list("<Key>4" "show_adjacent_metals(4)")
+ list("<Key>5" "show_adjacent_metals(5)")
+ list("<Key>6" "show_adjacent_metals(6)")
+ list("<Key>7" "show_adjacent_metals(7)")
+ list("<Key>8" "show_adjacent_metals(8)")
+ list("<Key>9" "show_adjacent_metals(9)")
+ list("Ctrl<Key>`" "toggle_od()")
+ list("Ctrl<Key>1" "toggle_metal(1)")
+ list("Ctrl<Key>2" "toggle_metal(2)")
+ list("Ctrl<Key>3" "toggle_metal(3)")
+ list("Ctrl<Key>4" "toggle_metal(4)")
+ list("Ctrl<Key>5" "toggle_metal(5)")
+ list("Ctrl<Key>6" "toggle_metal(6)")
+ list("Ctrl<Key>7" "toggle_metal(7)")
+ list("Ctrl<Key>8" "toggle_metal(8)")
+ list("Ctrl<Key>9" "toggle_metal(9)")
+ list("Ctrl<Key>10" "toggle_metal(10)")
+))
diff --git a/workspace_setup/models b/workspace_setup/models
new file mode 120000
index 0000000..0b4a84d
--- /dev/null
+++ b/workspace_setup/models
@@ -0,0 +1 @@
+PDK/MODELS/SPECTRE/s8phirs_10r/Models
\ No newline at end of file
diff --git a/workspace_setup/start_tutorial.sh b/workspace_setup/start_tutorial.sh
new file mode 100755
index 0000000..df42035
--- /dev/null
+++ b/workspace_setup/start_tutorial.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# Copyright 2019-2021 SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# This code is *alternatively* available under a BSD-3-Clause license, see
+# details in the README.md at the top level and the license text at
+# https://github.com/google/skywater-pdk-libs-sky130_bag3_pr/blob/master/LICENSE.alternative
+#
+# SPDX-License-Identifier: BSD-3-Clause OR Apache 2.0
+
+exec ${BAG_JUPYTER} --browser="firefox" tutorial_files
