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Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]1SkyWater Foundry Provided Standard Cell Libraries
2=================================================
3
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]4There are seven standard cell libraries provided directly by the SkyWater Technology foundry available for use on SKY130 designs, which differ in intended applications and come in three separate cell heights.
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]5
6Libraries :lib:`sky130_fd_sc_hs` (high speed), :lib:`sky130_fd_sc_ms` (medium speed), :lib:`sky130_fd_sc_ls` (low speed), and :lib:`sky130_fd_sc_lp` (low power) are compatible in size, with a 0.48 x 3.33um site, equivalent to about 11 :layer:`met1` tracks.
7
8Libraries :lib:`sky130_fd_sc_hd` (high density) and :lib:`sky130_fd_sc_hdll` (high density, low leakage) contain standard cells that are smaller, utilizing a 0.46 x 2.72um site, equivalent to 9 :layer:`met1` tracks.
9
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]10The :lib:`sky130_fd_sc_hvl` (high voltage) library contains 5V devices and utilizes a 0.48 x 4.07um site, or 14 :layer:`met1` tracks.
11
12Supply voltage, FETs, and approximate cell counts for these libraries appear in the table below:
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]13
14+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
15|   | :lib:`sky130_fd_sc_lp` | :lib:`sky130_fd_sc_ls` | :lib:`sky130_fd_sc_ms` | :lib:`sky130_fd_sc_hs` | :lib:`sky130_fd_sc_hd` | :lib:`sky130_fd_sc_hdll` | :lib:`sky130_fd_sc_hvl` |
16+===================================+=====================================+=====================================+=====================================+=====================================+=================================+=====================================+======================================+
17| VDD | 1.8 | 1.8 | 1.8 | 1.8 | 1.8 | 1.8 | 5 |
18+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
19| NMOS devices used | :cell:`sky130_fd_pr__nfet_01v8` | :cell:`sky130_fd_pr__nfet_01v8` | :cell:`sky130_fd_pr__nfet_01v8_lvt` | :cell:`sky130_fd_pr__nfet_01v8_lvt` | :cell:`sky130_fd_pr__nfet_01v8` | :cell:`sky130_fd_pr__nfet_01v8` | :cell:`sky130_fd_pr__nfet_g5v0d10v5` |
20+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
21| PMOS devices used | :cell:`sky130_fd_pr__pfet_01v8_hvt` | :cell:`sky130_fd_pr__pfet_01v8_hvt` | :cell:`sky130_fd_pr__pfet_01v8` | :cell:`sky130_fd_pr__pfet_01v8_lvt` | :cell:`sky130_fd_pr__pfet_01v8` | :cell:`sky130_fd_pr__pfet_01v8_hvt` | :cell:`sky130_fd_pr__pfet_g5v0d10v5` |
22+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
23| inverters, buffers | 108 | 48 | 48 | 48 | 56 | 62 | 19 |
24+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
25| AND, OR, NAND, NOR | 159 | 66 | 86 | 86 | 153 | 170 | 8 |
26+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
27| XOR, XNOR | 16 | 12 | 12 | 12 | 8 | 10 | 2 |
28+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
29| AND-OR-INV, OR-AND-INV | 138 | 71 | 71 | 71 | 115 | 125 | 4 |
30+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
31| AND-OR, OR-AND | 132 | 68 | 68 | 68 | 132 | 134 | 4 |
32+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
33| Adders, Comparators, Multiplexors | 59 | 37 | 33 | 33 | 31 | 44 | 11 |
34+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
35| Latches and Flip-Flops | 92 | 68 | 68 | 68 | 60 | 60 | 17 |
36+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
37| Custom power gating, bus cells | 43 | 66 | 42 | 42 | 51 | 42 | |
38+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
39| Macro cells | | 5 | | | | | |
40+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
41| UDB custom cells | | 21 | 17 | | | | |
42+-----------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+-------------------------------------+---------------------------------+-------------------------------------+--------------------------------------+
43
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]44The libraries uses 4 terminal transistors throughout. Individual cells do not have tap in them for the most part (there are a few exceptions). Instead, there are tap cells provided that allow for a staggered tap grid to be placed and connected to allow for body biasing, sleep mode support, and latchup protection.
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]45
46The following sections will review the libraries in more detail, in terms of performance.
47
48+-------------------------+-----------+--------------+--------------+--------------+
49| Architecture Comparison | Low Speed | High Density | High Density | High Voltage |
50| | | | Low Leakage | |
51+=========================+===========+==============+==============+==============+
52| TAP BAR | NO | NO | NO | YES |
53+-------------------------+-----------+--------------+--------------+--------------+
54| X-GRID | 0.480 | 0.460 | 0.460 | 0.480 |
55+-------------------------+-----------+--------------+--------------+--------------+
56| Y-GRID | 0.370 | 0.340 | 0.340 | 0.370 |
57+-------------------------+-----------+--------------+--------------+--------------+
58| CELL HEIGHT | 9 GRIDS | 8 GRIDS | 8 GRIDS | 11 GRIDS |
59+-------------------------+-----------+--------------+--------------+--------------+
60| CELL HEIGHT | 3.330 | 2.720 | 2.720 | 4.07 |
61+-------------------------+-----------+--------------+--------------+--------------+
62| NAND2 WIDTH | 3 GRIDS | 3 GRIDS | 4 GRIDS | 5 GRIDS |
63+-------------------------+-----------+--------------+--------------+--------------+
64| NAND2 WIDTH | 1.440 | 1.380 | 1.840 | 2.400 |
65+-------------------------+-----------+--------------+--------------+--------------+
66| NAND2 AREA | 4.7952 | 3.7536 | 5.0048 | 9.770 |
67+-------------------------+-----------+--------------+--------------+--------------+
68| WPMAX | 1.120 | 1.000 | 1.000 | 1.500 |
69+-------------------------+-----------+--------------+--------------+--------------+
70| WNMAX | 0.740 | 0.650 | 0.650 | 0.75 |
71+-------------------------+-----------+--------------+--------------+--------------+
72
73
74:lib:`sky130_fd_sc_hd` - High Density Standard Cell Library
75-----------------------------------------------------------
76
77The :lib:`sky130_fd_sc_hd` library is designed for high density.
78
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]79Compared to :lib:`sky130_fd_sc_ls`, this library enables higher routed gated density, lower dynamic power consumption, and comparable timing and leakage power. As a trade-off it has lower drive strength and does not support any drop in replacement medium or high speed library.
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]80
81- :lib:`sky130_fd_sc_hd` includes clock-gating cells to reduce active power during non-sleep modes.
82
83- Latches and flip-flops have scan equivalents to enable scan chain creation.
84
85- Multi-voltage domain library cells are provided.
86
87- Routed Gate Density is 160 kGates/mm^2 or better.
88
89- leakage @ttleak\_1.80v\_25C (no body bias) is 0.86 nA / kGate
90
91- :cell:`sky130_fd_sc_XX__buf_16` max cap (ss\_1.60v\_-40C, in/out tran=1.5ns) is 0.746 pF
92
93- Body Bias-able
94
95
96:lib:`sky130_fd_sc_hdll` - High Density, Low Leakage Standard Cell Library
97--------------------------------------------------------------------------
98
99The :lib:`sky130_fd_sc_hdll` library is a low leakage high density standard cell library.
100
101Compared to :lib:`sky130_fd_sc_hd`, this library enables 5-10X lower leakage power, but the same X, Y pin grids, routing layer pitches, and cell height.
102
103Blocks should be DRC clean when intermingled with :lib:`sky130_fd_sc_hd` cells.
104
105Raw gate density (number of :cell:`sky130_fd_sc_hdll__nand2_1` gates able to fit in 1mm2) for :lib:`sky130_fd_sc_hd` is 266kGates/mm2 and 200kGates/mm2 for :lib:`sky130_fd_sc_hdll`.
106
107- Includes integrating clock-gating cells to reduce active power during non-sleep modes
108
109- Latches and flip-flops in the library have a scan equivalent implementation to enable scan chain creation and testing supported by the synthesis tools
110
111- Multi-voltage domain library cells are provided
112
113- Routed Gate Density is 120 kGates/mm^2
114
115- leakage @ttleak\_1.80v\_25C (no body bias) is 0.08 nA / kGate
116
117- :cell:`sky130_fd_sc_XX__buf_16` max cap (ss\_1.60v\_-40C, in/out tran=1.5ns) < 1 pF
118
119- Multi-Voltage Design Support
120
121- Body Bias-able
122
123
124:lib:`sky130_fd_sc_hs` - Low Voltage (<2.0V), High Speed, Standard Cell Library
125-------------------------------------------------------------------------------
126
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]127:lib:`sky130_fd_sc_hs` library enables the implementation of low voltage high speed logic blocks in the SKY130 technology.
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]128
129:lib:`sky130_fd_sc_hs` cells are drop-in compatible with :lib:`sky130_fd_sc_ms`a or :lib:`sky130_fd_sc_ls` for the same function and drive strength. :lib:`sky130_fd_sc_hs` has the highest speed and the highest leakage of these.
130
131All logic cells are implemented with low voltage transistors and should be powered within the limits of those transistors. Specifically, the timing and power models are valid from 1.60V up to 1.95V, with timing data included for 10% and 20% dynamic IR drop analysis.
132
133All cells are functional at 1.2v. The low to high level shifter cells are capable of shifting from 1.2v to 1.95v.
134
135
136:lib:`sky130_fd_sc_ms` - Low Voltage (<2.0V), Medium Speed, Standard Cell Library
137----------------------------------------------------------------------------------
138
139:lib:`sky130_fd_sc_ms` is drop-in compatible with :lib:`sky130_fd_sc_ls` or :lib:`sky130_fd_sc_hs` libraries for cells of the same function and drive strength. :lib:`sky130_fd_sc_ms` cells have medium speed and leakage.
140
141:lib:`sky130_fd_sc_ms` is implemented with low voltage transistors; timing and power models are valid from 1.60V up to 1.95V. All cells are functional at 1.2v.
142
143The low to high level shifter cells are capable of shifting from 1.2v to 1.95v.
144
145- The library supports low leakage sleep mode via state retention flops
146
147- Includes integrating clock-gating cells to reduce active power during non-sleep modes
148
149- Latches and flip-flops in the library have a scan equivalent implementation to enable scan chain creation and testing supported by the synthesis tools
150
151- Library details:
152
153 - Inverters and buffers: 48
154
155 - AND, OR, NAND, NOR gates: 86
156
157 - Exclusive-OR and Exclusive-NOR: 12
158
159 - Inverted And-Or and Inverted Or-And: 71
160
161 - And-Or and Or-And: 68
162
163 - Adders, Comparators and Multiplexers: 33
164
165 - Latches and filp-flops: 68
166
167 - Low Power Flow Cells: 42
168
169 - UDB custom cells: 17
170
171
172:lib:`sky130_fd_sc_ls` - Low Voltage (<2.0V), Low Speed, Standard Cell Library
173-------------------------------------------------------------------------------
174
175:lib:`sky130_fd_sc_ls` cells are drop-in compatible with :lib:`sky130_fd_sc_ms`a or :lib:`sky130_fd_sc_hs` for the same function and drive strength. :lib:`sky130_fd_sc_ls` has the lowest speed and the lowest leakage of these.
176
177:lib:`sky130_fd_sc_ls` is implemented with low voltage transistors; timing and power models are valid from 1.60V up to 1.95V. All cells are functional at 1.2v.
178
179The low to high level shifter cells are capable of shifting from 1.2v to 1.95v.
180
181- The library supports low leakage sleep mode via sleep transistors
182
183- Includes integrating clock-gating cells to reduce active power during non-sleep modes
184
185- Latches and flip-flops in the library have a scan equivalent implementation to enable scan chain creation and testing supported by the synthesis tools
186
187- Drop-in compatible with :lib:`sky130_fd_sc_ms` and :lib:`sky130_fd_sc_hs` libraries
188
189- Only the high to low level-shifters are functional at 1v (:cell:`sky130_fd_sc_ls__lpflow_lsbuf_hl_*`). The low to high level-shifters (:cell:`sky130_fd_sc_ls__lpflow_lsbuf_lh_*`) are not functional at 1v as the threshold voltages of the FETs are not enough to flip the state.
190
191- Library details:
192
193 - Inverters and buffers: 48
194
195 - AND, OR, NAND, NOR gates: 86
196
197 - Exclusive-OR and Exclusive-NOR: 12
198
199 - Inverted And-Or and Inverted Or-And: 71
200
201 - And-Or and Or-And: 68
202
203 - Adders, Comparators and Multiplexers: 37
204
205 - Latches and filp-flops: 68
206
207 - Low Power Flow Cells: 66
208
209 - Macro Cells: 5
210
211 - UDB Custom Cells: 21
212
213
214:lib:`sky130_fd_sc_lp` - Low Voltage (<2.0V), Low Power, Standard Cell Library
215------------------------------------------------------------------------------
216
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]217:lib:`sky130_fd_sc_lp` is the largest of the SKY130 standard cell libraries at nearly 750 cells. All logic cells are implemented with low voltage transistors and should be powered within the limits of those transistors. Specifically, the timing and power models are valid from 1.55V up to 2.0V.
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]218
219- :lib:`sky130_fd_sc_lp` supports low leakage sleep mode via sleep transistors
220
221- Includes integrating clock-gating cells to reduce active power during non-sleep modes
222
223- Latches and flip-flops have scan equivalents to enable scan chain creation
224
225- Larger Library size:
226
227 - Inverters, Buffers: 108
228
229 - AND, OR, NAND, NOR gates: 159
230
231 - Exclusive-OR, Exclusive-NOR: 16
232
233 - AND-OR-Inverted, OR-AND-Inverted: 138
234
235 - AND-OR, OR-AND: 132
236
237 - Adders, Comparators, Multiplexors: 59
238
239 - Custom Power gating, bus cells: 43
240
241 - Latches and flip-flops: 92
242
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]243
244:lib:`sky130_fd_sc_hvl` - High Voltage (5V), Standard Cell Library
245------------------------------------------------------------------
246
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]247The :lib:`sky130_fd_sc_hvl` library has the smallest cell count of the SKY130 standard cell libraries, but is the only one that enables 5V tolerant logic blocks. All logic cells are implemented with 5v tolerant transistors; timing and power models are valid from 1.65v to 5.5v. The low voltage to high voltage level shifter is functional shifting from 1.2v to 5.5v.
Tim 'mithro' Ansell4abbce32020-10-09 12:20:17 -0700[diff] [blame]248
249Raw gate density (number of :cell:`sky130_fd_sc_hvl__nand2_1` gates able to fit in 1mm2) should be 170kGates/mm2.
250
Adrian Freeda651b172020-10-12 11:24:12 -0700[diff] [blame]251Routed should be >= 100kGates/mm2. Due to the gate length for these high voltage transistors, the actual gate density is lower than 170kGates/mm2. The size of a 2-input NAND gate in this library is actually 5 grids wide, whereas the 170k calculation is based on a gate that is 3 grids wide. With a 5 grid wide gate, the raw gate density is 102kGates/mm2.