| 1.8V low-VT PMOS FET |
| -------------------- |
| |
| Spice Model Information |
| ~~~~~~~~~~~~~~~~~~~~~~~ |
| |
| - Cell Name: :cell:`sky130_fd_pr__pfet_01v8` |
| - Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt` |
| |
| Operating Voltages where SPICE models are valid |
| |
| - V\ :sub:`DS` = 0 to -1.95V |
| - V\ :sub:`GS` = 0 to -1.95V |
| - V\ :sub:`BS` = -0.1 to +1.95V |
| |
| Details |
| ~~~~~~~ |
| |
| Major model output parameters are shown below and compared against the EDR (e-test) specs |
| |
| |
| .. include:: pfet_01v8_lvt-table0.rst |
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| Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations: |
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| .. include:: pfet_01v8_lvt-table1.rst |
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| |
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| The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below: |
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| |symbol-pfet_01v8_lvt| |
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| The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the V\ :sub:`T` adjust implants (to achieve the lower V\ :sub:`T`) |
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| |cross-section-pfet_01v8_lvt| |
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| .. |symbol-pfet_01v8_lvt| image:: symbol-pfet_01v8_lvt.svg |
| .. |cross-section-pfet_01v8_lvt| image:: cross-section-pfet_01v8_lvt.svg |
| |
