docs: Adding layers tables and LVS info.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/docs/rules.rst b/docs/rules.rst
index 32ad1c2..f6e0ede 100644
--- a/docs/rules.rst
+++ b/docs/rules.rst
@@ -8,6 +8,13 @@
rules/background
rules/masks
+
rules/assumptions
+
+ rules/layers
+
+ rules/summary
+
rules/periphery
+
rules/errors
diff --git a/docs/rules/layers.rst b/docs/rules/layers.rst
index b07f1a5..464ee1f 100644
--- a/docs/rules/layers.rst
+++ b/docs/rules/layers.rst
@@ -1,5 +1,5 @@
-Device, LVS and other CAD definitions
-=====================================
+Layers Reference
+================
Layers Definitions
------------------
@@ -7,6 +7,7 @@
.. csv-table:: Table C3: Device, LVS and other CAD definitions
:file: layers/table-c3-device-lvs-other.csv
:header-rows: 1
+ :stub-columns: 1
Auxiliary Layers
----------------
@@ -14,10 +15,31 @@
.. csv-table:: Table C4a: Purpose layer description in LSW window and Auxiliary Layers
:file: layers/table-c4a-layer-description.csv
:header-rows: 1
+ :stub-columns: 1
.. csv-table:: Table C4b: Purpose layer description in LSW window and Auxiliary Layers
:file: layers/table-c4b-layer-description.csv
:header-rows: 1
+ :stub-columns: 1
+
+Devices and Layout vs Schematic (LVS) Information
+-------------------------------------------------
+
+.. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS)
+ :file: layers/table-c4b-layer-description.csv
+ :header-rows: 1
+ :stub-columns: 1
+
+.. include:: layers/table-f2a-lvs-key.rst
+
+
+.. csv-table:: Table F2b: Mask Generation table
+ :file: layers/table-f2b-mask.tsv
+ :delim: "tab"
+ :header-rows: 1
+ :stub-columns: 1
+
+.. include:: layers/table-f2b-mask-key.rst
GDS Layers Information
@@ -29,5 +51,15 @@
.. csv-table:: Table - GDS Layers
:file: gds_layers.csv
:header-rows: 1
+ :stub-columns: 1
:widths: 10, 15, 10, 75
+Device and Layout vs. Schematic
+===============================
+
+.. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS)
+ :file: layers/table-f2a-lvs.tsv
+ :delim: "tab"
+ :header-rows: 1
+ :stub-columns: 1
+
diff --git a/docs/rules/layers/table-f2a-lvs-key.rst b/docs/rules/layers/table-f2a-lvs-key.rst
new file mode 100644
index 0000000..5b1f28a
--- /dev/null
+++ b/docs/rules/layers/table-f2a-lvs-key.rst
@@ -0,0 +1,28 @@
+Explanation of symbols:
+* ``-`` = Layer illegal for the device
+* ``+`` = Layer allowed to overlap
+* ``D`` = DRAWN indicates that a layer is drawn by Design.
+* ``C`` = CREATED indicates that the layer is only created by CAD.
+
+.. rubric:: Footnotes
+
+.. [#f1] Low vt needs to be set on the schematic element
+.. [#f2] Ncm is drawn inside core. Otherwise it is created in periphery. See rules ncm.X.* for details
+.. [#f3] Drawn over half of device
+.. [#f4] ASSUMPTION: FET models will be same regardless of backend flow
+.. [#f5] The 2 core FETs and flash npass must have a poly.ml label with their model name.
+.. [#f6] over the drain
+.. [#f7] over the source
+.. [#f8] Information for RCX
+.. [#f9] Uses a black box for LVS. This is a fixed layout; Use symbol provided by modeling group
+.. [#f10] LVS will check that phighvt inside areaid.ce overlaps ncm
+.. [#f11] The default model is sonos_e, sonos_de and nvssonos_e. If sonos_p, sonos_dp and nvssonos_p model are required, poly.ml must be used
+.. [#f12] The capacitor.dg is drawn 0.17um from the edge of the cell to be LVS clean
+.. [#f13] Devices are LVS'ed by cell name, m=1 per cell, fixed area and perimeter (see QHC-18)
+.. [#f14] (dnwell not (pwres or pnp or npn or areaid.en or areaid.de or areaid.po)) not nwell must have condiode text; Refer to VUN-104, 192 for condiode usage
+.. [#f15] Tech element is created by the user, no CAD supplied tech element
+.. [#f16] There are multiple configurations of the Cu inductor. The layers present in one configuration may not be drawn in the other configuration. Also rdl will not be routed over met5 cu inductor, not checkable by CAD flow.
+.. [#f17] Used for substrate noise isolation regions only
+.. [#f18] Either UHVI or areaid.low_vt should be drawn over the sturctures
+.. [#f19] Psub-Deep Nwell Diode must have condiode text "condiodeHvPsub"; CVA-596
+.. [#f20] mrp1 can't overlay capacitor.dg: exempted s8rf2_xcmvpp11p5x11p7_lim5shield from the rule
diff --git a/docs/rules/layers/table-f2a-lvs-print.py b/docs/rules/layers/table-f2a-lvs-print.py
new file mode 100755
index 0000000..37a97e0
--- /dev/null
+++ b/docs/rules/layers/table-f2a-lvs-print.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+
+import csv
+import os
+import pprint
+import sys
+
+__dir__ = os.path.dirname(os.path.abspath(__file__))
+
+TSV_FILE = os.path.join(__dir__, "table-f2a-lvs.tsv")
+
+
+def main(arg):
+ rows = []
+ with open(TSV_FILE, newline='') as csvfile:
+ reader = csv.reader(csvfile, delimiter='\t')
+ for r in reader:
+ rows.append(list(c.strip() for c in r))
+
+ rowlen = max(len(r) for r in rows)
+ for r in rows:
+ while len(r) < rowlen:
+ r.append('')
+
+ clen = [0] * rowlen
+ for i, _ in enumerate(clen):
+ clen[i] = max(len(r[i]) for r in rows)
+
+ for r in rows:
+ for i, m in enumerate(clen):
+ r[i] = r[i].ljust(m)
+
+ rows.insert(1, ['-'*m for m in clen])
+
+ for r in rows:
+ print("|", " | ".join(r), "|")
+
+ return 0
+
+
+if __name__ == "__main__":
+ sys.exit(main(sys.argv))
diff --git a/docs/rules/layers/table-f2a-lvs.tsv b/docs/rules/layers/table-f2a-lvs.tsv
new file mode 100644
index 0000000..6c503bd
--- /dev/null
+++ b/docs/rules/layers/table-f2a-lvs.tsv
@@ -0,0 +1,91 @@
+Category Name Used? Required schematic elements diff.dg diff.rs diff.ct cfom.wp tap.dg dnwell:dg pwbm.dg pwdem:dg hvtr.dg nwell.dg hvtp:dg lvtn:dg pwell.rs pwell.ct ncm.dg [#f2]_ tunm:dg hvi:dg rpm:dg poly.dg poly.rs poly.ct poly:ml ldntm:dg npc:dg nsdm.dg psdm.dg licon.dg li1.dg li.rs li.ct capm:dg capm_2t.dg metX.dg metX.fe met1:dg met2:dg met3:dg met4.dg met5.dg rdl.dg inductor:dg capacitor.dg areaid.le areaid.en pnp.dg npn.dg areaid.st areaid.de areaid.re areaid.po areaid:ce areaid.ed areaid.ext UHVI areaid.low_vt Drawn Route / Comments Layout Model
+RESISTOR n diff resistor X res resn D D D + - + - + - - - - + + - + - + - - - + + + D - + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdn
+RESISTOR HV n diff resistor X res resnhv D D D + - + - + - - - - + + - + D + - - - + + + D - + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdn_hv
+RESISTOR p diff resistor X res resp D D D + - + - + - D - - + + C + - + - - - + + + - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdp
+RESISTOR p diff resistor NV res resp D D D + - + - + - D - - + + C + - + - - - + + + - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdp
+RESISTOR HV p diff resistor X res resphv D D D + - + - + - D - - + + - + D + - - - + + + - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdp_hv
+RESISTOR Isolated Pwell resistor X respw + + + + D D - - - - + + D D + + + + - - - + + + + + + + + + + + + + + + + + + + - - - + + + + + - - + - - xpwres
+RESISTOR n+ poly resistor X res - - - + - + - + - + - - + + - + + - D D D + + - + + + + + - + + + - + + + + + + + - [#f20]_ - - - - + - + - - + - - mrp1
+RESISTOR p+ poly resistor X res3 - - - + - + - + - + - - + + + + + D D D D + + D - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - xhrpoly_*
+RESISTOR li resistor X res + + + + + + - + - + + + + + + + + + + + + + + + + + - D D D + + + + + + + + + + + - - - + + + + + - - + - - mrl1
+RESISTOR metal fuse X mrmX - - - + - + - + - - - - + + - - - - - + + + + + - - - - + + D D + + + + + + - - - - - - + - + - - - - - metX AND metX.fe mrmX
+32 A CMOS nmos 1.8V X nfet D - - + - + - - - - - - + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - + + - - nshort
+32 A CMOS pmos 1.8V X pfet D - - + - + - - - D C - + + C - - - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - - + - - pshort
+32 A CMOS Low Vt pmos 1.8V 32A X pfet D - - + - + - - - D - D + + - - - - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - - - - - plowvt
+32 A CMOS High Vt pmos 1.8V 32A [#f10]_ X pfet D - - + - + - - - D D C + + + - - - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - + - - - phighvt
+32 A CMOS Low Vt nmos 1.8V 32A X nfet D - - + - + - - - - - D + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - - - - nlowvt
+32 A CMOS nmos_core [#f5]_ X nfet D - - + - + - - - - - - + + - - - - D - - D - - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - npass npd
+32 A CMOS nmos_core NV [#f5]_ nfet D - - + - + - - - - - - + + D - - - D - - D D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - npassll npdll
+32 A CMOS pmos_core [#f5]_ X pfet D - - + - + - - - D D C + + D - - - D - - D - - - D + + - - + + + - + + + + + + + - - - - - + - + - D - - - ppu
+32 A CMOS pmos_core NV [#f5]_ pfet D - - + - + - - - D D C + + - - - - D - - D - - - D + + - - + + + - + + + + + + + - - - - - + - + - D - - - ppull
+32 A CMOS Low Vt nmos_core [#f5]_ X nfet D - - + - + - - - - - D + + - - - - D - - D - - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - nlvtpass
+32 A CMOS Low Vt Varactor X capbn_b - - - + D + - - - D - C + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - - - - xcnwvc
+32 A CMOS High Vt Varactor X capbn_b - - - + D + - - - D D C + + C - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - - - - xcnwvc2
+32 A CMOS HV varactor (floating gate) X capbn_b - - - + D + - - - D - D + + - - D - D - - + - - D - - + - - + + + - + + + + + + + - - - - - + - + - - - - - xchvnwc
+SONOS (& SONOS Latch) SONOS fet [#f11]_ X nfet D - - + - D - - - - - D + + - D - - D - - + D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - sonos_p/e
+SONOS (& SONOS Latch) SONOS fet [#f11]_ nfet D - - + - D - - - - - D + + - D - - D - - + D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - sonos_de/dp
+SONOS (& SONOS Latch) NV SONOS fet [#f11]_ nfet D - - + - + - - - - - D + + - D - - D - - D D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - nvssonos_p/e
+110A CMOS HV nmos 5/10.5V X nfet D - - + - + - - - - - - + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - + - - nhv
+110A CMOS HV nmos 5/10.5V nfet D - - + - + - - - - - - + + - - D - D - - D - - D - + + - - + + + - + + + + + + + - - - - - + - + - - + - - nhvcore
+110A CMOS HV pmos 5/10.5V X pfet D - - + - + - - - D - - + + - - D - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - - + - - phv
+110A CMOS HV pmos 5/10.5V pfet D - - + - + - - - D - - + + - - D - D - - D - - - D + + - - + + + - + + + + + + + - - - - - + - + - - + - - phvcore
+110A CMOS Native nmos 5V X nfet D - - + - + - - - - - D + + - - D - D - - + - - D - + + - - + + + - + + + + + + + + - - - - + - + - - - - - nhvnative
+110A CMOS Native nmos 3V X nfet D - - + - + - - - - - D + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - D - - - + - + - - - - - ntvnative
+110A CMOS Flash npass [#f5]_ X nfet D - - + - + - - - - - - + + - - D - D - - D D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - fnpass
+110A CMOS Flash npass NV nfet D - - + - + - - - - - - + + - - D - D - - D D - D [#f3]_ - + + - - + + + - + + + + + + + - - - - - + - + - D - - - nvsrnpass
+110A CMOS VHV nmos 5/16V DE X nfetextd D [#f7]_ - - + D [#f6]_ - - - - D - - + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - D - - + - + - - - - - nvhv
+110A CMOS VHV pmos 5/16V DE X pfetextd D [#f7]_ - - + D [#f6]_ D - - - D [#f3]_ - - + + - - D - D - - + - - - D + + - - + + + - + + + + + + + - - D - - + - + - - - - - pvhv
+110A CMOS UHV nmos 5/20V DE nfetextd D [#f7]_ - - + D [#f6]_ D [#f3]_ D [#f3]_ - - D [#f3]_ - D [#f3]_ + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20vhv1
+110A CMOS UHV iso nmos 5/20V DE nfetextdiso D [#f7]_ - - + D [#f6]_ D [#f3]_ D [#f3]_ - - D [#f3]_ - D [#f3]_ + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20vhviso1
+110A CMOS UHV Native nmos 5/20V DE nfetextd D [#f7]_ - - + D [#f6]_ D [#f3]_ D [#f3]_ - - D [#f3]_ - D + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20nativevhv1
+110A CMOS UHV Zvt nmos 5/20V DE nfetextd D [#f7]_ - - + D [#f6]_ D [#f3]_ D - - D [#f3]_ - D + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20zvtvhv1
+110A CMOS UHV pmos 5/20V DE pfetextd D [#f7]_ - - + D [#f6]_ D D [#f3]_ D [#f3]_ - D [#f3]_ - D [#f3]_ + + - - D - D - - + - - - D + + - - + + + - + + + + + + + - - - - - + - - - D D D p20vhv1
+CAPACITOR MiM (3 Terminal) cmim3c - + + + - + - + - + + + + + + + + + - + + + + + + + + - + + D - + - - D + + + + - - - - + + + + + - - + - - xcmimc
+CAPACITOR MiM (2 Terminal) cmimc + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + D D + - + D + + + + - - - - + + + + + - - + - - xcmimc2
+CAPACITOR VPP [#f9]_ X + + + + + + - + - + + + + + + + + + + + + + + + + + - D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp xcmvpp_2
+CAPACITOR VPP over NHVNATIVE X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp2_nhvnative10x4
+CAPACITOR VPP over PHV X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp2_phv5x4
+CAPACITOR VPP and NHVNATIVE X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D + + + + D - - + + + + + - - + - - xcmvppx4_2xnhvnative10x4
+CAPACITOR 4-Terminal VPP (with Met3 shield) [#f12]_ X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D + + + + D - - + + + + + - - + - - xcmvpp1p8x1p8_m3shield xcmvpp8p6x7p9_m3shield xcmvpp4p4x4p6_m3shield xcmvpp11p5x11p7_m3shield
+CAPACITOR 4-terminal VPP (with M5 shield) [#f12]_ X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D D D + + D - - + + + + + - - + - - xcmvpp11p5x11p7_m5shield xcmvpp11p5x11p7_polym5shield xcmvpp11p5x11p7_lim5shield xcmvpp8p6x7p9_m3_lim5shield xcmvpp11p5x11p7_m3_lim5shield xcmvpp4p4x4p6_m3_lim5shield xcmvpp11p5x11p7_m1m4m5shield xcmvpp11p5x11p7_polym50p4shield
+CAPACITOR 4-terminal VPP (with M4 shield) [#f12]_ X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D D + + + D - - + + + + + - - + - - xcmvpp11p5x11p7_m4shield xcmvpp11p5x11p7_polym4shield xcmvpp6p8x6p1_polym4shield xcmvpp6p8x6p1_lim4shield
+CAPACITOR 3-Terminal VPP [#f12]_ X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp1p8x1p8 xcmvpp3 xcmvpp4 xcmvpp5 xcmvpp4p4x4p6_m1m2 xcmvpp11p5x11p7_m1m2
+CAPACITOR 3-Terminal VPP [#f12]_ (for S8Q/S8P ONLY) X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D + + + + D - - + + + + + - - + - - xcmvpp8p6x7p9_m3_lishield xcmvpp4p4x4p6_m3_lishield xcmvpp11p5x11p7_m3_lishield
+CAPACITOR 3-Terminal VPP [#f12]_ (for S8P ONLY) X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D D + + + D - - + + + + + - - + - - xcmvpp11p5xx11p7_m1m4 xcmvpp_hd5_*
+INDUCTOR Inductor inductor + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + D + + + D - - - + + + + + - - + - - xind
+INDUCTOR Cu Inductor X ind4 + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + D + D [#f16]_ D [#f16]_ D D [#f16]_ D - - - - - - - - - - - - - *xind4*
+INDUCTOR Balun Inductor [#f15]_ X + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + D D D D - - - - - - - - - - - - - *balun*
+DIODE nDiode X lvsdiode D - - + - + - + - - - - + + - + - + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - + + - - ndiode
+DIODE HV nDiode X lvsdiode D - - + - + - + - - - - + + - + D + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - - + - - ndiode_h
+DIODE RF ESD HV nDiode [#f13]_ X lvsdiode D - - + - - - + - - - - + + - + D + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - - D - - xesd_ndiode_h_X (where X=100 200 300)
+DIODE RF ESD HV Deep Nwell nDiode [#f13]_ X lvsdiode D - - + - D - + - - - - + + - + D + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - - D - - xesd_ndiode_h_dnwl_X (where X=100 200 300)
+DIODE pDiode X lvsdiode D - - + - + - + - D - - + + C + - + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - + - - pdiode
+DIODE pDiode NV lvsdiode D - - + - + - + - D - - + + C + - + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - + - - pdiode
+DIODE HV pDiode X lvsdiode D - - + - + - + - D - - + + - + D + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - - + - - pdiode_h
+DIODE RF ESD HV pDiode [#f13]_ X lvsdiode D - - + - + - + - D - - + + - + D + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - - D - - xesd_pdiode_h_X (where X=100 200 300)
+DIODE Photo Diode X lvsdiode - - - + D D - - - D - - - - - - - - - - - - - - D - + + - - + + + - + + + + + + + - - - - - + D + D - - - - dnwdiode_psub
+DIODE Low Vt pdiode [#f8]_ X diode D + + + + + - + - D - D + + + + + + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + - + + - - pdiode_lvt
+DIODE High Vt pDiode [#f8]_ X diode D + + + + + - + - D D C + + + + - + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + - + + - - pdiode_hvt
+DIODE High Vt pDiode NV [#f8]_ diode D + + + + + - + - D D C + + C + - + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + - + + - - pdiode_hvt
+DIODE Low Vt nDiode [#f8]_ X diode D + + + + + - + - + + D + + + + + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + + - + + - - ndiode_lvt
+DIODE NV SONOS Diode [#f8]_ diode D + + + + + - + - + + D + + + D + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + + + + - D + - - ndiode_nvs
+DIODE Native nDiode [#f8]_ X diode D + + + + + - + - + + D + + + + D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - ndiode_native
+DIODE Nwell Diode [#f8]_ X diode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - nwdiode
+DIODE Nwdiode_victim [#f17]_ X lvsdiode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - nwdiode
+DIODE Nwdiode_aggressor [#f17]_ X lvsdiode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - nwdiode
+DIODE RF Nwell Diode [#f8]_ X diode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D - + + - - xnwdiode_rf
+DIODE Pwell-Deep Nwell Diode [#f8]_ X diode + + + + + D - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - dnwdiode_pw
+DIODE RF ESD Pwell-Deep Nwell Diode [#f8]_ X lvsdiode + + + + + D - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D + - + D - - xesd_dnwdiode_pw_X (where X=100 200 300)
+DIODE RF Pwell-Deep Nwell Diode [#f8]_ X diode + + + + + D - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D - + + - - xdnwdiode_pwell_rf
+DIODE Psub-Deep Nwell Diode [#f8]_ X diode + + + + + D - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_psub
+DIODE Psub-Deep Nwell Diode [#f17]_ X lvsdiode + + + + + D - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_psub
+DIODE Psub-Deep Nwell Diode [#f17]_ X lvsdiode + + + + + D - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_psub
+DIODE Psub-Deep Nwell Diode [#f8]_ [#f19]_ diode + + + + + D D + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + D [#f18]_ D [#f18]_ dnwhvdiode_psub
+DIODE HV Pwell-Deep Nwell Diode [#f8]_ [#f19]_ diode + + + + + D - D - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_hvpw
+PNP Parasitic PNP X pnp4 D - - + D - - - - D + - + + - + - + - - - + + + D D + + - - + + + - + + + + + + + - - - D - + - + - - - - - Layout provided by technology pnppar pnppar5x
+PNP Parasitic HV Gated NPN X npn4 D - - + + D - - - D + - - - - + D + D - - + + + D D + + - - + + + - + + + + + + + - - - - D + - + - - - - - Layout provided by technology npn_1x1_2p0_hv
+PNP Parasitic NPN X npn4 D - - + + D - - - D + - - - - + - + - - - + + + D D + + - - + + + - + + + + + + + - - - - D + - + - - - - - Layout provided by technology npnpar1x1 npnpar1x2
+ESD transistor LV nESD transistor X nfet D - - + - + - - - - - - + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - D - - NMOS with ESD_nwell_tap nshortesd
+ESD transistor HV nESD transistor X nfet D - - + - + - - - - - - + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - D - - NMOS with ESD_nwell_tap nhvesd
+ESD transistor HV Native nESD transistor X nfet D - - + - + - - - - - D + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - D - - NMOS with ESD_nwell_tap nhvnativeesd
+ESD transistor HV pESD transistor X pfet D - - + - + - - - D - - + + - - D - D - - + - - - D + + - - + + + - + + + + + + + - - - - - + - + - - D - - phvesd
diff --git a/docs/rules/layers/table-f2b-mask-key.rst b/docs/rules/layers/table-f2b-mask-key.rst
new file mode 100644
index 0000000..ddbb215
--- /dev/null
+++ b/docs/rules/layers/table-f2b-mask-key.rst
@@ -0,0 +1,9 @@
+Explanation of symbols:
+* ``-`` = Layer not created for the device
+* ``+`` = Layer allowed to overlap
+* ``C`` = CREATED
+* ``nr`` = next revision
+
+.. rubric:: Footnotes
+
+.. [#fb1] For RCX information
diff --git a/docs/rules/layers/table-f2b-mask-print.py b/docs/rules/layers/table-f2b-mask-print.py
new file mode 100755
index 0000000..983199f
--- /dev/null
+++ b/docs/rules/layers/table-f2b-mask-print.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+
+import csv
+import os
+import pprint
+import sys
+
+__dir__ = os.path.dirname(os.path.abspath(__file__))
+
+TSV_FILE = os.path.join(__dir__, "table-f2b-mask.tsv")
+
+
+def main(arg):
+ rows = []
+ with open(TSV_FILE, newline='') as csvfile:
+ reader = csv.reader(csvfile, delimiter='\t')
+ for r in reader:
+ rows.append(list(c.strip() for c in r))
+
+ rowlen = max(len(r) for r in rows)
+ for r in rows:
+ while len(r) < rowlen:
+ r.append('')
+
+ clen = [0] * rowlen
+ for i, _ in enumerate(clen):
+ clen[i] = max(len(r[i]) for r in rows)
+
+ for r in rows:
+ for i, m in enumerate(clen):
+ r[i] = r[i].ljust(m)
+
+ rows.insert(1, ['-'*m for m in clen])
+
+ for r in rows:
+ print("|", " | ".join(r), "|")
+
+ return 0
+
+
+if __name__ == "__main__":
+ sys.exit(main(sys.argv))
diff --git a/docs/rules/layers/table-f2b-mask.tsv b/docs/rules/layers/table-f2b-mask.tsv
new file mode 100644
index 0000000..6198206
--- /dev/null
+++ b/docs/rules/layers/table-f2b-mask.tsv
@@ -0,0 +1,77 @@
+Category Name Used? Layout Model and required schematic element FOM DNM PWBM PWDEM NWM HVTPM LVTNM NCM TUNM ONOM LVOM RPM P1M HVNTM NTM LDNTM NPC NSDM PSDM LICM1 LI1M CAPM MM1 MM2 MM3 MM5 CU1M INDM Drawn Route / Comments
+RESISTOR n diff resistor res r mrdn C + - - - - - - - - - + - - - - - C - + + + + + + + + +
+RESISTOR HV n diff resistor res r mrdn_hv C + - - - - - - - - C + - C C - - C - + + + + + + + + +
+RESISTOR p diff resistor res r mrdp C + - - C C - C - - - + - - C - - - C + + + + + + + + +
+RESISTOR p diff resistor NV res r mrdp C + - - C C - C - - - + - - C - - - C + + + + + + + + +
+RESISTOR HV p diff resistor res r mrdp_hv C + - - C - - - - - C + - - C - - - C + + + + + + + + +
+RESISTOR Isolated Pwell resistor respw xpwres C C - - - + + + + + + + - + + + + + + + + + + + + + + +
+RESISTOR n+ poly resistor res mrp1 - + - - + - - - + + + - C + + + - + + + + + + + + + + +
+RESISTOR p+ poly resistor res3 xhrpoly_*_* - + - - + - - + + + + C C - C - C - C + + + + + + + + +
+RESISTOR li resistor res mrl1 + + - - + + + + + + + + + + + + + + + - C + + + + + + +
+RESISTOR metal fuse_D mrmX mrmX - + - - - - - - - - - + - - - + + + + - - + + + C + + + metX AND metX.fe
+RESISTOR metal fuse_T mrmX mrmX - + - - - - - - - - - + - - - + + + + - - + + C + + + + metX AND metX.fe
+32 A CMOS nmos 1.8V nfet nshort C + - - - - - - - - - - C - - - - C - + + + + + + + + +
+32 A CMOS pmos 1.8V pfet pshort C + - - C C - C - - - - C - C - - - C + + + + + + + + +
+32 A CMOS pmos 1.8V NV pfet pshort C + - - C C - C - - - - C - C - - - C + + + + + + + + +
+32 A CMOS Low Vt pmos 1.8V 32A pfet plowvt C + - - C - C - - - - - C - C - - - C + + + + + + + + +
+32 A CMOS High Vt pmos 1.8V 32A pfet phighvt C + - - C C C C - - - - C - C - - - C + + + + + + + + +
+32 A CMOS High Vt pmos 1.8V 32A NV pfet phighvt C + - - C C C C - - - - C - C - - - C + + + + + + + + +
+32 A CMOS Low Vt nmos 1.8V 32A nfet nlowvt C + - - - - C - - - - - C - - - - C - + + + + + + + + +
+32 A CMOS nmos_core nfet npass npd C + - - - - - - - - - - C - - - - C - + + + + + + + + +
+32 A CMOS nmos_core NV nfet npassll npdll C + - - - - - C - - - - C - - C - C - + + + + + + + + +
+32 A CMOS pmos_core pfet ppu C + - - C C C C - - - - C - C - - - C + + + + + + + + +
+32 A CMOS pmos_core NV pfet ppull C + - - C C C - - - - - C - C - - - C + + + + + + + + +
+32 A CMOS Low Vt nmos_core C + - - - - C - - - - - C - - - - C - + + + + + + + + +
+32 A CMOS Low Vt Varactor capbn xcnwvc C + - - C - C - - - - - C - C - - C - + + + + + + + + +
+32 A CMOS High Vt Varactor capbn xcnwvc2 C + - - C C C C - - - - C - C - - C - + + + + + + + + +
+32 A CMOS HV varactor (floating gate) C C - - C - C - - - C - C C C - - C - - + + + + + + + +
+SONOS (& SONOS Latch) SONOS fet nfet sonos_p/e C C - - - - C - C C C - C - C C - C - + + + + + + + + +
+SONOS (& SONOS Latch) NV SONOS fet nfet nvssonos_p/e C + - - - - C - C C C - C - C C - C - + + + + + + + + +
+110A CMOS HV nmos 5/10.5V nfet nhv C + - - - - - - - - C - C C C - - C - + + + + + + + + +
+110A CMOS HV pmos 5/10.5 V pfet phv C + - - C - - - - - C - C - C - - - C + + + + + + + + +
+110A CMOS Native nmos 5V nfet nhvnative C + - - - - C - - - C - C C C - - C - + + + + + + + + +
+110A CMOS Native nmos 3V nfet ntvnative C + - - - - C - - - C - C C C - - C - + + + + + + + + +
+110A CMOS Flash npass nfet fnpass C + - - - - - - - - C - C - C C - C - + + + + + + + + +
+110A CMOS Flash npass NV nfet nvsrnpass C + - - - - - - - - C - C - C C - C - + + + + + + + + +
+110A CMOS VHV nmos 5/16V DE nfet nvhv C - - - C - - - - - C - C C C - - C - + + + + + + + + +
+110A CMOS VHV pmos 5/16V DE pfet pvhv C C - - C - - - - - C - C - C - - - C + + + + + + + + +
+110A CMOS UHV nmos 5/20V DE nfete C C C - C - C - - - C - C - - - - C - + + + + + + + + +
+110A CMOS UHV iso nmos 5/20V DE nfete C C C - C - C - - - C - C - - - - C - + + + + + + + + +
+110A CMOS UHV Native nmos 5/20V DE TBA C C C - C - C - - - C - C - - - - C - + + + + + + + + +
+110A CMOS UHV Native iso nmos 5/20V DE nfete C C C - C - C - - - C - C - - - - C - + + + + + + + + +
+110A CMOS UHV pmos 5/20V DE pfete C C C C C - C - - - C - C - - - - - C + + + + + + + + +
+CAPACITOR MiM cmim3 xcmimc + + - - + + + + + + + + + + + + + + + + + C + C + + + +
+CAPACITOR VPP cap xcmvpp + + - - + + + + + + + + + + + + + + + - C - C C + + + -
+CAPACITOR VPP (with met3 shield) vppca + + - - + + + + + + + + + + + + + + + - C - C C C + + -
+INDUCTOR Inductor induc xind + + - - + + + + + + + + + + + + + + + + + + + + + + + C
+INDUCTOR Cu Inductor induc xind + + - - + + + + + + + + + + + + + + + + + + + + + C C -
+INDUCTOR Balun Inductor induc xind + + - - + + + + + + + + + + + + + + + + + + + + + C C -
+DIODE nDiode lvsdi ndiode C + - - - - - - + + - + - - - + + C - + + + + + + + + +
+DIODE HV nDiode lvsdi ndiode_h C + - - - - - - + + C + - C C + + C - + + + + + + + + +
+DIODE RF ESD HV nDiode lvsdi ndiode_h C - - - - - - - + + C + - C C + + C - + + + + + + + + +
+DIODE RF ESD Deep Nwell nDiode lvsdi C C - - - - - - + + C + - C C + + C - + + + + + + + + +
+DIODE pDiode lvsdi pdiode C + - - C C - C + + - + - - C + + - C + + + + + + + + +
+DIODE pDiode NV lvsdi pdiode C + - - C C - C + + - + - - C + + - C + + + + + + + + +
+DIODE HV pDiode lvsdi pdiode_h C + - - C - - - + + C + - - C + + - C + + + + + + + + +
+DIODE RF ESD HV pDiode lvsdi pdiode_h C + - - C - - - + + C + - - C + + - C + + + + + + + + +
+DIODE Photo Diode lvsdi dnwdiode C C - - C C - C - - - - - - C - - C - + + + + + + + + +
+DIODE Low Vt pdiode [#fb1]_ diode pdiode_lvt C + - - C - C + + + + + + + C + + - C + + + + + + + + +
+DIODE High Vt pDiode [#fb1]_ diode pdiode_hvt C + - - C C C C + + + + + + C + + - C + + + + + + + + +
+DIODE High Vt pDiode NV [#fb1]_ diode pdiode_hvt C + - - C C C C + + + + + + C + + - C + + + + + + + + +
+DIODE Low Vt nDiode [#fb1]_ diode ndiode_lvt C + - - + + C + + + + + + + - + + C - + + + + + + + + +
+DIODE NV SONOS Diode [#fb1]_ diode ndiode_nvs C + - - + + C + C C C + + + + C + + + + + + + + + + + +
+DIODE Native nDiode [#fb1]_ diode ndiode_native C + - - + + C + + + C + + C C + + + + + + + + + + + + +
+DIODE Nwell Diode [#fb1]_ diode nwdiode + - - - C + + + + + + + + + + + + + + + + + + + + + + +
+DIODE RF Nwell Diode [#fb1]_ diode nwdiode + - - - C + + + + + + + + + + + + + + + + + + + + + + +
+DIODE Pwell-Deep Nwell Diode [#fb1]_ diode dnwdiode_pw + C - - - + + + + + + + + + + + + + + + + + + + + + + +
+DIODE RF ESD Pwell-Deep Nwell Diode [#fb1]_ diode dnwdiode_pw + C - - - + + + + + + + + + + + + + + + + + + + + + + +
+DIODE RF Pwell-Deep Nwell Diode [#fb1]_ diode dnwdiode_pw + C - - - + + + + + + + + + + + + + + + + + + + + + + +
+DIODE Psub-Deep Nwell Diode [#fb1]_ diode dnwdiode_psub + C - - + + + + + + + + + + + + + + + + + + + + + + + +
+DIODE Psub-Deep Nwell Diode [#fb1]_ diode dnwdiode_psub + C C - + + + + + + + + + + + + + + + + + + + + + + + +
+DIODE HV Pwell-Deep Nwell Diode [#fb1]_ diode dnwdiode_hvpw + C - - + + + + + + + + + + + + + + + + + + + + + + + +
+PNP Parasitic PNP pnp4 pnppar C - - - C C - C - - - + - - C - + C C + + + + + + + + + Layout provided by technology
+PNP Parasitic NPN pnp4 npnpar C C - - C + - - - - - + - - - - + C C + + + + + + + + + Layout provided by technology
+ESD transistor LV nESD transistor nfet nshortesd C + - - - - - - - - - - C - - - - C - + + + + + + + + + NMOS with ESD_nwell_tap
+ESD transistor HV nESD transistor nfet nhvesd C + - - - - - - - - C - C C C - - C - + + + + + + + + + NMOS with ESD_nwell_tap
+ESD transistor HV Native nESD transistor C + - - - - C - - - C - C C C - - C - + + + + + + + + +
+ESD transistor HV pESD transistor pfet phvesd C + - - C - - - - - C - C - C - - - C + + + + + + + + +
