docs: Fixing capacitance / resistance CSV files.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/docs/rules/rcx.rst b/docs/rules/rcx.rst
index 085d020..af330b0 100644
--- a/docs/rules/rcx.rst
+++ b/docs/rules/rcx.rst
@@ -58,7 +58,6 @@
.. csv-table:: Table of capacitance rules
:file: rcx/capacitance-rules.csv
:stub-columns: 1
- :delim: U+0009
Capacitance Values
diff --git a/docs/rules/rcx/capacitance-rules.csv b/docs/rules/rcx/capacitance-rules.csv
index 61180e9..851f317 100644
--- a/docs/rules/rcx/capacitance-rules.csv
+++ b/docs/rules/rcx/capacitance-rules.csv
@@ -1,30 +1,30 @@
-,General (CAP.-)
-.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.)
-
-,MOS Devices (MOS.-)
-.mos.1,area between poly and diff should not have capacitance extracted.
-.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8)
-.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).
-.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.
+,General (CAP.-),
+.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.),
+,,
+,MOS Devices (MOS.-),
+.mos.1,area between poly and diff should not have capacitance extracted.,
+.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8),
+.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).,
+.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.,
.mos.5,All 20V NMOS ISO DEFETs will have the parasitic diode included in the models.,This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub).
-.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.
+.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.,
.mos.7,The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor.,The model will over-write all other instance parameters from CAD extraction.
-
-,Resistors (RES.-)
-.res.1,short devices must not have capacitance calculated across the device.
-.res.2,fuse devices must have capacitance extracted.
-.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.
-.res.4,metops that are merged must have capacitance extracted.
-.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.
-.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).
-.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
-.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
-
-,Capacitors (PASSIVES.-)
-.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)"
-.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)"
-.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)"
-.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)"
-
-,Bipolar Devices
-,none
+,,
+,Resistors (RES.-),
+.res.1,short devices must not have capacitance calculated across the device.,
+.res.2,fuse devices must have capacitance extracted.,
+.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.,
+.res.4,metops that are merged must have capacitance extracted.,
+.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.,
+.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).,
+.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.",
+.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.",
+,,
+,Capacitors (PASSIVES.-),
+.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)",
+.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)",
+.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)",
+.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)",
+,,
+,Bipolar Devices,
+,none,
diff --git a/docs/rules/rcx/resistance-rules.csv b/docs/rules/rcx/resistance-rules.csv
index 18bb1a2..d7504ff 100644
--- a/docs/rules/rcx/resistance-rules.csv
+++ b/docs/rules/rcx/resistance-rules.csv
@@ -1,26 +1,26 @@
-,General (RES.-)
-.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.
-
-,Sheet Resistance (SR.-)
+,General (RES.-),
+.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.,
+,,
+,Sheet Resistance (SR.-),
.X,Calibre now extracts deltaW by bucketing the sheet rho based on different widths.,The accuracy of each bucket must be within 2% of the Sheet Rho Calc using deltaW.
-.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology)
-.met2,Parasitic resistance is calculated for all metal2.
-.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1
-.li1,Parasitic resistance is calculated for all li1.
-.poly.1,Parasitic resistance on gates is calculated to the center of the gate.
-.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.
-.diff.1,Parasitic resistance is not extracted for any diffusion regions.
-.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.
-.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.
-
-,contact-to-gate space (CT.-)
-.via,All vias will have parasitic resistance extracted.
-.mcon,All mcons will have parasitic resistance extracted.
-.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.
-.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.
-.licon.3,All licons that are connected to FETs will be extracted by RCX.
-.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.
-.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.
-.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.
-.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models."
-.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models."
+.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology),
+.met2,Parasitic resistance is calculated for all metal2.,
+.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1,
+.li1,Parasitic resistance is calculated for all li1.,
+.poly.1,Parasitic resistance on gates is calculated to the center of the gate.,
+.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.,
+.diff.1,Parasitic resistance is not extracted for any diffusion regions.,
+.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.,
+.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.,
+,,
+,contact-to-gate space (CT.-),
+.via,All vias will have parasitic resistance extracted.,
+.mcon,All mcons will have parasitic resistance extracted.,
+.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.,
+.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.,
+.licon.3,All licons that are connected to FETs will be extracted by RCX.,
+.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.,
+.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.,
+.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.,
+.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models.",
+.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models.",
