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foss-eda-tools/skywater-pdk/f3ed3d715481735d2768f5bf51c7c28164020c6e
commit
f3ed3d715481735d2768f5bf51c7c28164020c6e
[log]
author
Tim Ansell <me@mith.ro>
Tue Oct 06 08:29:53 2020 -0700
committer
GitHub <noreply@github.com>
Tue Oct 06 08:29:53 2020 -0700
tree
7b92a30f5778b46d329cfbd2d990f3fded842ef7
parent
3ac9f24a1bdf3e1ca388d643bf547e7acc1a03e9 [diff]
parent
795158aa4bbfa7c3b76dde32e1eb52be04687a1f [diff]
Merge pull request #167 from mithro/verilog-fix-3

verilog: Fix ordering of ports on mux primitives.
tree: 7b92a30f5778b46d329cfbd2d990f3fded842ef7
  1. .github/
  2. docs/
  3. libraries/
  4. scripts/
  5. .gitignore
  6. .gitmodules
  7. .readthedocs.yml
  8. .travis.yml
  9. AUTHORS
  10. environment.yml
  11. LICENSE
  12. Makefile
  13. README.rst
  14. README.src.rst
  15. requirements.txt