| commit | f3ed3d715481735d2768f5bf51c7c28164020c6e | [log] [tgz] |
|---|---|---|
| author | Tim Ansell <me@mith.ro> | Tue Oct 06 08:29:53 2020 -0700 |
| committer | GitHub <noreply@github.com> | Tue Oct 06 08:29:53 2020 -0700 |
| tree | 7b92a30f5778b46d329cfbd2d990f3fded842ef7 | |
| parent | 3ac9f24a1bdf3e1ca388d643bf547e7acc1a03e9 [diff] | |
| parent | 795158aa4bbfa7c3b76dde32e1eb52be04687a1f [diff] |
Merge pull request #167 from mithro/verilog-fix-3 verilog: Fix ordering of ports on mux primitives.