| commit | 3ac9f24a1bdf3e1ca388d643bf547e7acc1a03e9 | [log] [tgz] |
|---|---|---|
| author | Tim Ansell <me@mith.ro> | Mon Oct 05 20:12:03 2020 -0700 |
| committer | GitHub <noreply@github.com> | Mon Oct 05 20:12:03 2020 -0700 |
| tree | caa50eeecc05f88f9625214c15b5784970b23714 | |
| parent | 3f373a2b99a2f009e3f54138bfe0e039f18cfb95 [diff] | |
| parent | d1de6e82feba6e1ac3ae2ac7bfdf2a12f9e68ff5 [diff] |
Merge pull request #166 from mithro/verilog-fix-2 verilog: Fixing usage of cell reserved word.