Merge pull request #106 from mithro/res-cap
docs: Adding basic values for capacitance + resistance.
diff --git a/docs/rules/layers.rst b/docs/rules/layers.rst
index 464ee1f..01ca2b7 100644
--- a/docs/rules/layers.rst
+++ b/docs/rules/layers.rst
@@ -35,7 +35,7 @@
.. csv-table:: Table F2b: Mask Generation table
:file: layers/table-f2b-mask.tsv
- :delim: "tab"
+ :delim: U+0009
:header-rows: 1
:stub-columns: 1
@@ -59,7 +59,7 @@
.. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS)
:file: layers/table-f2a-lvs.tsv
- :delim: "tab"
+ :delim: U+0009
:header-rows: 1
:stub-columns: 1
diff --git a/docs/rules/layers/table-c4b-layer-description.csv b/docs/rules/layers/table-c4b-layer-description.csv
index 77f884c..129dcf9 100644
--- a/docs/rules/layers/table-c4b-layer-description.csv
+++ b/docs/rules/layers/table-c4b-layer-description.csv
@@ -79,4 +79,4 @@
natfet.dg {124:21},DEFETs,natfet.dg,"Add TUNM for SONOS channel implants. See SPR 117559, SGL-529",All,DRC/CLDRC
areaid:lw,Ultra High voltage id layer, ,Areaid low voltage: UHV box to put all HV/LV curcuits in,All,Analog
"* To distinguish the layers, the full name of the layer needs to be turned on in the LSW window",,,,,
-"As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3"
+"As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3",,,,,
diff --git a/docs/rules/rcx.rst b/docs/rules/rcx.rst
index 9450c84..af330b0 100644
--- a/docs/rules/rcx.rst
+++ b/docs/rules/rcx.rst
@@ -8,9 +8,10 @@
The CAD columns indicate sheets and contacts that are parasitics included in the schematic/layout RCX from Assura.
.. csv-table:: Parasitic Extraction Table
- :file: rcx/rcx-all.csv
+ :file: rcx/rcx-all.tsv
:header-rows: 2
:stub-columns: 1
+ :delim: U+0009
.. note:: The models includes M1/M2 capacitance. As a result of RCX extraction limitation M1/M2 routing over the varactor will have no capacitance extraction.
@@ -33,10 +34,21 @@
.. todo:: This table should be rendered like the periphery rules.
.. csv-table:: Table of resistance rules
- :file: rcx/resistance.csv
- :header-rows: 2
+ :file: rcx/resistance-rules.csv
:stub-columns: 1
+Resistance Values
+-----------------
+
+This section includes tables of basic resistance values for SKY130.
+
+Further data can be found in the `"SKY130 Stackup Capacitance Data" spreadsheet`_.
+
+.. csv-table:: Table - Resistances
+ :file: rcx/resistance-values.tsv
+ :header-rows: 1
+ :delim: U+0009
+
Capacitance Rules
-----------------
@@ -44,11 +56,58 @@
.. todo:: This table should be rendered like the periphery rules.
.. csv-table:: Table of capacitance rules
- :file: rcx/capacitance.csv
- :header-rows: 2
+ :file: rcx/capacitance-rules.csv
:stub-columns: 1
+Capacitance Values
+------------------
+
+This section includes tables of basic capacitance values for SKY130.
+
+Further data can be found in the `"SKY130 Stackup Capacitance Data" spreadsheet`_.
+
+.. _"SKY130 Stackup Capacitance Data" spreadsheet: https://docs.google.com/spreadsheets/d/1N9To-xTiA7FLfQ1SNzWKe-wMckFEXVE9WPkPPjYkaxE/edit#gid=226894802
+
+Basic Capacitance - Fringe Downward
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Fringe capacitances are a constant value per unit length and are an approximations. Determined by creating a layout with a 5um x 10um rectangle of each layer over or under a much larger rectangle of the other layer. The fringe capacitance computed from the total given minus the parallel plate capacitance.
+
+"downward direction" means that the larger plate is below the 5um x 10um plate.
+
+The layer in the first column is always the layer with the 5um x 10um plate.
+
+.. csv-table:: Table - Capacitance - Fringe Downward
+ :file: rcx/capacitance-fringe-downward.tsv
+ :header-rows: 1
+ :delim: U+0009
+
+
+Basic Capacitance - Fringe Upward
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Fringe capacitances are a constant value per unit length and are an approximations. Determined by creating a layout with a 5um x 10um rectangle of each layer over or under a much larger rectangle of the other layer. The fringe capacitance computed from the total given minus the parallel plate capacitance.
+
+"upward direction" means that the larger plate is above the 5um x 10um plate.
+
+The layer in the first column is always the layer with the 5um x 10um plate.
+
+.. csv-table:: Table - Capacitance - Fringe Upward
+ :file: rcx/capacitance-fringe-upward.tsv
+ :header-rows: 1
+ :delim: U+0009
+
+
+Basic Capacitance - Parallel
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. csv-table:: Table - Capacitance - Parallel
+ :file: rcx/capacitance-parallel.tsv
+ :header-rows: 1
+ :delim: U+0009
+
+
Discrepencies
-------------
@@ -62,3 +121,4 @@
The impact of this on total capacitance and parasitic capacitance is already comprehended in the model corners, however, cross-talk is not modeled. Also, parasitic cap is routed to ground and this may not be ideal for the scenario.
The parasitic cap can be estimated using RescapWeb.
+
diff --git a/docs/rules/rcx/capacitance-fringe-downward.tsv b/docs/rules/rcx/capacitance-fringe-downward.tsv
new file mode 100644
index 0000000..8497b33
--- /dev/null
+++ b/docs/rules/rcx/capacitance-fringe-downward.tsv
@@ -0,0 +1,7 @@
+Interlayer fringe capacitance (downward direction) (aF/um) Poly Local interconnect Metal1 Metal2 Metal3 Metal4
+Local interconnect 51.846
+Metal1 46.724 59.496
+Metal2 41.222 46.277 67.045
+Metal3 43.531 46.708 54.814 69.846
+Metal4 38.105 39.709 42.563 46.382 70.522
+Metal5 39.908 41.147 43.188 45.592 54.152 82.819
diff --git a/docs/rules/rcx/capacitance-fringe-upward.tsv b/docs/rules/rcx/capacitance-fringe-upward.tsv
new file mode 100644
index 0000000..c3a6951
--- /dev/null
+++ b/docs/rules/rcx/capacitance-fringe-upward.tsv
@@ -0,0 +1,7 @@
+Interlayer fringe capacitance (upward direction) (aF/um) Local interconnect Metal1 Metal2 Metal3 Metal4 Metal5
+Poly 25.138 16.691 11.166 9.18 6.3505 6.4903
+Local interconnect 34.7 21.739 15.078 10.141 7.6366
+Metal1 48.193 26.676 16.421 12.017
+Metal2 44.432 22.332 15.693
+Metal3 42.643 27.836
+Metal4 46.976
diff --git a/docs/rules/rcx/capacitance-parallel.tsv b/docs/rules/rcx/capacitance-parallel.tsv
new file mode 100644
index 0000000..9e9e990
--- /dev/null
+++ b/docs/rules/rcx/capacitance-parallel.tsv
@@ -0,0 +1,7 @@
+Interlayer parallel plate capacitance (aF/um^2) Local interconnect Metal1 Metal2 Metal3 Metal4 Metal5
+Poly 94.1644 44.8056 24.4968 16.0552 10.0131 7.2085
+Local interconnect 114.1970 37.5647 20.7915 11.6705 8.0265
+Metal1 133.8610 34.5350 15.0275 9.4789
+Metal2 86.1861 20.3321 11.3410
+Metal3 84.0346 19.6269
+Metal4 68.3252
diff --git a/docs/rules/rcx/capacitance.csv b/docs/rules/rcx/capacitance-rules.csv
similarity index 75%
rename from docs/rules/rcx/capacitance.csv
rename to docs/rules/rcx/capacitance-rules.csv
index efd0ec6..851f317 100644
--- a/docs/rules/rcx/capacitance.csv
+++ b/docs/rules/rcx/capacitance-rules.csv
@@ -1,30 +1,30 @@
-,General(CAP.-)
-.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.)
-
-,MOS Devices (MOS.-)
-.mos.1,area between poly and diff should not have capacitance extracted.
-.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8)
-.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).
-.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.
+,General (CAP.-),
+.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.),
+,,
+,MOS Devices (MOS.-),
+.mos.1,area between poly and diff should not have capacitance extracted.,
+.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8),
+.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).,
+.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.,
.mos.5,All 20V NMOS ISO DEFETs will have the parasitic diode included in the models.,This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub).
-.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.
+.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.,
.mos.7,The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor.,The model will over-write all other instance parameters from CAD extraction.
-
-,Resistors (RES.-)
-.res.1,short devices must not have capacitance calculated across the device.
-.res.2,fuse devices must have capacitance extracted.
-.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.
-.res.4,metops that are merged must have capacitance extracted.
-.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.
-.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).
-.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
-.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
-
-,Capacitors (PASSIVES.-)
-.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)"
-.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)"
-.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)"
-.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)"
-
-,Bipolar Devices
-,none
+,,
+,Resistors (RES.-),
+.res.1,short devices must not have capacitance calculated across the device.,
+.res.2,fuse devices must have capacitance extracted.,
+.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.,
+.res.4,metops that are merged must have capacitance extracted.,
+.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.,
+.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).,
+.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.",
+.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.",
+,,
+,Capacitors (PASSIVES.-),
+.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)",
+.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)",
+.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)",
+.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)",
+,,
+,Bipolar Devices,
+,none,
diff --git a/docs/rules/rcx/resistance.csv b/docs/rules/rcx/resistance-rules.csv
similarity index 72%
rename from docs/rules/rcx/resistance.csv
rename to docs/rules/rcx/resistance-rules.csv
index 04980a0..d7504ff 100644
--- a/docs/rules/rcx/resistance.csv
+++ b/docs/rules/rcx/resistance-rules.csv
@@ -1,26 +1,26 @@
- ,General (RES.-)
-.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.
-
-,Sheet Resistance (SR.-)
+,General (RES.-),
+.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.,
+,,
+,Sheet Resistance (SR.-),
.X,Calibre now extracts deltaW by bucketing the sheet rho based on different widths.,The accuracy of each bucket must be within 2% of the Sheet Rho Calc using deltaW.
-.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology)
-.met2,Parasitic resistance is calculated for all metal2.
-.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1
-.li1,Parasitic resistance is calculated for all li1.
-.poly.1,Parasitic resistance on gates is calculated to the center of the gate.
-.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.
-.diff.1,Parasitic resistance is not extracted for any diffusion regions.
-.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.
-.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.
-
-,contact-to-gate space (CT.-)
-.via,All vias will have parasitic resistance extracted.
-.mcon,All mcons will have parasitic resistance extracted.
-.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.
-.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.
-.licon.3,All licons that are connected to FETs will be extracted by RCX.
-.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.
-.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.
-.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.
-.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models."
-.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models."
+.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology),
+.met2,Parasitic resistance is calculated for all metal2.,
+.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1,
+.li1,Parasitic resistance is calculated for all li1.,
+.poly.1,Parasitic resistance on gates is calculated to the center of the gate.,
+.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.,
+.diff.1,Parasitic resistance is not extracted for any diffusion regions.,
+.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.,
+.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.,
+,,
+,contact-to-gate space (CT.-),
+.via,All vias will have parasitic resistance extracted.,
+.mcon,All mcons will have parasitic resistance extracted.,
+.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.,
+.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.,
+.licon.3,All licons that are connected to FETs will be extracted by RCX.,
+.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.,
+.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.,
+.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.,
+.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models.",
+.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models.",
diff --git a/docs/rules/rcx/resistance-values.tsv b/docs/rules/rcx/resistance-values.tsv
new file mode 100644
index 0000000..2f0b361
--- /dev/null
+++ b/docs/rules/rcx/resistance-values.tsv
@@ -0,0 +1,23 @@
+Layer Resistivity (mohms/sq)
+Poly 48200
+Local interconnect 12800
+Metal1 125
+Metal2 125
+Metal3 47
+Metal4 47
+Metal5 29
+Deep nwell 2200000
+Pwell (in deep nwell) 3050000
+Nwell 1700000
+N-diffusion 120000
+P-diffusion 197000
+HV N-diffusion 114000
+HV P-diffusion 191000
+XHR poly resistor 319800
+UHR poly resistor 2000000
+LICON contact 15000
+MCON contact 152000
+VIA 4500
+VIA2 3410
+VIA3 3410
+VIA4 380
