commit a5be8131c7a3954b2cd07fb9c9ae56a3c974298d
author Tim 'mithro' Ansell <tansell@google.com> Sun May 10 11:13:33 2020 -0700
committer Tim 'mithro' Ansell <tansell@google.com> Sun May 10 11:13:33 2020 -0700
tree 85feba1c48df096c5426f466f897ffd4cd7f780f
parent d6206f1f5d8532afda29b66c04b68f71413497d5

s/PNG/PIN/

scripts/python-skywater-pdk/generate_top_verilog.py

diff --git a/scripts/python-skywater-pdk/generate_top_verilog.py b/scripts/python-skywater-pdk/generate_top_verilog.py
index 94b01f5..e2df032 100755
--- a/scripts/python-skywater-pdk/generate_top_verilog.py
+++ b/scripts/python-skywater-pdk/generate_top_verilog.py
@@ -61,14 +61,14 @@
 //# {description}
 module {module_base_name}_{drive_value} (
     {module_signal_defports}
-`ifdef SC_USE_PG_PNG
+`ifdef SC_USE_PG_PIN
     {module_power_defports}
 `endif
 );
 
     {module_base_name} (
         {module_signal_ports}
-`ifdef SC_USE_PG_PNG
+`ifdef SC_USE_PG_PIN
         {module_power_ports}
 `endif
     );