diff --git a/scripts/python-skywater-pdk/generate_top_verilog.py b/scripts/python-skywater-pdk/generate_top_verilog.py
index 94b01f5..e2df032 100755
--- a/scripts/python-skywater-pdk/generate_top_verilog.py
+++ b/scripts/python-skywater-pdk/generate_top_verilog.py
@@ -61,14 +61,14 @@
 //# {description}
 module {module_base_name}_{drive_value} (
     {module_signal_defports}
-`ifdef SC_USE_PG_PNG
+`ifdef SC_USE_PG_PIN
     {module_power_defports}
 `endif
 );
 
     {module_base_name} (
         {module_signal_ports}
-`ifdef SC_USE_PG_PNG
+`ifdef SC_USE_PG_PIN
         {module_power_ports}
 `endif
     );