| commit | 328db21c872f7e37d567c3cfdaf16b35390e1ccc | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <tansell@google.com> | Sun May 10 21:24:33 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Sun May 10 21:24:33 2020 -0700 |
| tree | 528964501303af06f50f8014efdb5b2d44b52299 | |
| parent | 64016a5adaea68dbe6b235fabdfd15b16611f4fb [diff] |
Another hack.
diff --git a/scripts/python-skywater-pdk/generate_top_verilog.py b/scripts/python-skywater-pdk/generate_top_verilog.py index ef8d07c..a3f8976 100755 --- a/scripts/python-skywater-pdk/generate_top_verilog.py +++ b/scripts/python-skywater-pdk/generate_top_verilog.py
@@ -86,6 +86,9 @@ return drive_name, drive_value = drive + if not 'ports' in mdata: + return + module_signal_defports = [] module_signal_ports = [] for pname, ptype in mdata['ports']['signal']: