diff --git a/scripts/python-skywater-pdk/generate_top_verilog.py b/scripts/python-skywater-pdk/generate_top_verilog.py
index ef8d07c..a3f8976 100755
--- a/scripts/python-skywater-pdk/generate_top_verilog.py
+++ b/scripts/python-skywater-pdk/generate_top_verilog.py
@@ -86,6 +86,9 @@
             return
         drive_name, drive_value = drive
 
+        if not 'ports' in mdata:
+            return
+
         module_signal_defports = []
         module_signal_ports = []
         for pname, ptype in mdata['ports']['signal']: