libraries/sky130_fd_io/v0.2.0/cells/top_pwrdetv2/definition.json

{
 "description": "vddd and vddio power detectors.",
 "file_prefix": "sky130_fd_io__top_pwrdetv2",
 "library": "sky130_fd_io",
 "name": "top_pwrdetv2",
 "parameters": [
  [
   "STARTUP_DELAY",
   ""
  ],
  [
   "STARTUP_DELAY",
   ""
  ]
 ],
 "ports": [
  [
   "signal",
   "OUT1_VDDD_HV",
   "output",
   ""
  ],
  [
   "signal",
   "OUT1_VDDIO_HV",
   "output",
   ""
  ],
  [
   "signal",
   "OUT2_VDDD_HV",
   "output",
   ""
  ],
  [
   "signal",
   "OUT2_VDDIO_HV",
   "output",
   ""
  ],
  [
   "signal",
   "OUT3_VDDD_HV",
   "output",
   ""
  ],
  [
   "signal",
   "OUT3_VDDIO_HV",
   "output",
   ""
  ],
  [
   "signal",
   "TIE_LO_ESD",
   "output",
   ""
  ],
  [
   "signal",
   "VDDD_PRESENT_VDDIO_HV",
   "output",
   ""
  ],
  [
   "signal",
   "VDDIO_PRESENT_VDDD_HV",
   "output",
   ""
  ],
  [
   "signal",
   "IN1_VDDD_HV",
   "input",
   ""
  ],
  [
   "signal",
   "IN1_VDDIO_HV",
   "input",
   ""
  ],
  [
   "signal",
   "IN2_VDDD_HV",
   "input",
   ""
  ],
  [
   "signal",
   "IN2_VDDIO_HV",
   "input",
   ""
  ],
  [
   "signal",
   "IN3_VDDD_HV",
   "input",
   ""
  ],
  [
   "signal",
   "IN3_VDDIO_HV",
   "input",
   ""
  ],
  [
   "signal",
   "RST_POR_HV_N",
   "input",
   ""
  ],
  [
   "power",
   "VCCD",
   "inout",
   "supply1"
  ],
  [
   "power",
   "VDDD1",
   "inout",
   "supply1"
  ],
  [
   "power",
   "VDDD2",
   "inout",
   "supply1"
  ],
  [
   "power",
   "VDDIO_Q",
   "inout",
   "supply1"
  ],
  [
   "power",
   "VSSA",
   "inout",
   "supply0"
  ],
  [
   "power",
   "VSSD",
   "inout",
   "supply0"
  ],
  [
   "power",
   "VSSIO_Q",
   "inout",
   "supply0"
  ]
 ],
 "type": "cell",
 "verilog_name": "sky130_fd_io__top_pwrdetv2"
}